Index: kernel/arch/ia64/include/asm.h =================================================================== --- kernel/arch/ia64/include/asm.h (revision da52547b3a8fc0b23125d3adbd5622075264ee53) +++ kernel/arch/ia64/include/asm.h (revision bbfdf62eecb75fb74d785cdd587affc613b7ffe9) @@ -40,8 +40,9 @@ #include #include +#include #define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL -static inline void pio_write_8(ioport8_t *port, uint8_t v) +NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v) { uintptr_t prt = (uintptr_t) port; @@ -56,5 +57,5 @@ } -static inline void pio_write_16(ioport16_t *port, uint16_t v) +NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v) { uintptr_t prt = (uintptr_t) port; @@ -69,5 +70,5 @@ } -static inline void pio_write_32(ioport32_t *port, uint32_t v) +NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v) { uintptr_t prt = (uintptr_t) port; @@ -82,5 +83,5 @@ } -static inline uint8_t pio_read_8(ioport8_t *port) +NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port) { uintptr_t prt = (uintptr_t) port; @@ -95,5 +96,5 @@ } -static inline uint16_t pio_read_16(ioport16_t *port) +NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port) { uintptr_t prt = (uintptr_t) port; @@ -108,5 +109,5 @@ } -static inline uint32_t pio_read_32(ioport32_t *port) +NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port) { uintptr_t prt = (uintptr_t) port; @@ -126,21 +127,26 @@ * The stack is assumed to be STACK_SIZE long. * The stack must start on page boundary. - */ -static inline uintptr_t get_stack_base(void) -{ - uint64_t v; - - /* I'm not sure why but this code bad inlines in scheduler, - so THE shifts about 16B and causes kernel panic - - asm volatile ( - "and %[value] = %[mask], r12" - : [value] "=r" (v) - : [mask] "r" (~(STACK_SIZE - 1)) - ); - return v; - - This code have the same meaning but inlines well. - */ + * + */ +NO_TRACE static inline uintptr_t get_stack_base(void) +{ + uint64_t v; + + /* + * I'm not sure why but this code inlines badly + * in scheduler, resulting in THE shifting about + * 16B and causing kernel panic. + * + * asm volatile ( + * "and %[value] = %[mask], r12" + * : [value] "=r" (v) + * : [mask] "r" (~(STACK_SIZE - 1)) + * ); + * return v; + * + * The following code has the same semantics but + * inlines correctly. + * + */ asm volatile ( @@ -155,6 +161,7 @@ * * @return PSR. - */ -static inline uint64_t psr_read(void) + * + */ +NO_TRACE static inline uint64_t psr_read(void) { uint64_t v; @@ -171,6 +178,7 @@ * * @return Return location of interruption vector table. - */ -static inline uint64_t iva_read(void) + * + */ +NO_TRACE static inline uint64_t iva_read(void) { uint64_t v; @@ -187,6 +195,7 @@ * * @param v New location of interruption vector table. - */ -static inline void iva_write(uint64_t v) + * + */ +NO_TRACE static inline void iva_write(uint64_t v) { asm volatile ( @@ -196,10 +205,11 @@ } - /** Read IVR (External Interrupt Vector Register). * - * @return Highest priority, pending, unmasked external interrupt vector. - */ -static inline uint64_t ivr_read(void) + * @return Highest priority, pending, unmasked external + * interrupt vector. + * + */ +NO_TRACE static inline uint64_t ivr_read(void) { uint64_t v; @@ -213,5 +223,5 @@ } -static inline uint64_t cr64_read(void) +NO_TRACE static inline uint64_t cr64_read(void) { uint64_t v; @@ -225,10 +235,10 @@ } - /** Write ITC (Interval Timer Counter) register. * * @param v New counter value. - */ -static inline void itc_write(uint64_t v) + * + */ +NO_TRACE static inline void itc_write(uint64_t v) { asm volatile ( @@ -241,6 +251,7 @@ * * @return Current counter value. - */ -static inline uint64_t itc_read(void) + * + */ +NO_TRACE static inline uint64_t itc_read(void) { uint64_t v; @@ -257,6 +268,7 @@ * * @param v New match value. - */ -static inline void itm_write(uint64_t v) + * + */ +NO_TRACE static inline void itm_write(uint64_t v) { asm volatile ( @@ -269,6 +281,7 @@ * * @return Match value. - */ -static inline uint64_t itm_read(void) + * + */ +NO_TRACE static inline uint64_t itm_read(void) { uint64_t v; @@ -285,6 +298,7 @@ * * @return Current vector and mask bit. - */ -static inline uint64_t itv_read(void) + * + */ +NO_TRACE static inline uint64_t itv_read(void) { uint64_t v; @@ -301,6 +315,7 @@ * * @param v New vector and mask bit. - */ -static inline void itv_write(uint64_t v) + * + */ +NO_TRACE static inline void itv_write(uint64_t v) { asm volatile ( @@ -313,6 +328,7 @@ * * @param v This value is ignored. - */ -static inline void eoi_write(uint64_t v) + * + */ +NO_TRACE static inline void eoi_write(uint64_t v) { asm volatile ( @@ -325,6 +341,7 @@ * * @return Current value of TPR. - */ -static inline uint64_t tpr_read(void) + * + */ +NO_TRACE static inline uint64_t tpr_read(void) { uint64_t v; @@ -341,6 +358,7 @@ * * @param v New value of TPR. - */ -static inline void tpr_write(uint64_t v) + * + */ +NO_TRACE static inline void tpr_write(uint64_t v) { asm volatile ( @@ -356,6 +374,7 @@ * * @return Old interrupt priority level. - */ -static ipl_t interrupts_disable(void) + * + */ +NO_TRACE static ipl_t interrupts_disable(void) { uint64_t v; @@ -377,6 +396,7 @@ * * @return Old interrupt priority level. - */ -static ipl_t interrupts_enable(void) + * + */ +NO_TRACE static ipl_t interrupts_enable(void) { uint64_t v; @@ -399,6 +419,7 @@ * * @param ipl Saved interrupt priority level. - */ -static inline void interrupts_restore(ipl_t ipl) + * + */ +NO_TRACE static inline void interrupts_restore(ipl_t ipl) { if (ipl & PSR_I_MASK) @@ -411,6 +432,7 @@ * * @return PSR. - */ -static inline ipl_t interrupts_read(void) + * + */ +NO_TRACE static inline ipl_t interrupts_read(void) { return (ipl_t) psr_read(); @@ -422,5 +444,5 @@ * */ -static inline bool interrupts_disabled(void) +NO_TRACE static inline bool interrupts_disabled(void) { return !(psr_read() & PSR_I_MASK); @@ -428,5 +450,5 @@ /** Disable protection key checking. */ -static inline void pk_disable(void) +NO_TRACE static inline void pk_disable(void) { asm volatile ( Index: kernel/arch/ia64/include/atomic.h =================================================================== --- kernel/arch/ia64/include/atomic.h (revision da52547b3a8fc0b23125d3adbd5622075264ee53) +++ kernel/arch/ia64/include/atomic.h (revision bbfdf62eecb75fb74d785cdd587affc613b7ffe9) @@ -36,5 +36,7 @@ #define KERN_ia64_ATOMIC_H_ -static inline atomic_count_t test_and_set(atomic_t *val) +#include + +NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val) { atomic_count_t v; @@ -50,5 +52,5 @@ } -static inline void atomic_lock_arch(atomic_t *val) +NO_TRACE static inline void atomic_lock_arch(atomic_t *val) { do { @@ -57,5 +59,5 @@ } -static inline void atomic_inc(atomic_t *val) +NO_TRACE static inline void atomic_inc(atomic_t *val) { atomic_count_t v; @@ -68,5 +70,5 @@ } -static inline void atomic_dec(atomic_t *val) +NO_TRACE static inline void atomic_dec(atomic_t *val) { atomic_count_t v; @@ -79,5 +81,5 @@ } -static inline atomic_count_t atomic_preinc(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_preinc(atomic_t *val) { atomic_count_t v; @@ -92,5 +94,5 @@ } -static inline atomic_count_t atomic_predec(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_predec(atomic_t *val) { atomic_count_t v; @@ -105,5 +107,5 @@ } -static inline atomic_count_t atomic_postinc(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val) { atomic_count_t v; @@ -118,5 +120,5 @@ } -static inline atomic_count_t atomic_postdec(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val) { atomic_count_t v; Index: kernel/arch/ia64/include/cpu.h =================================================================== --- kernel/arch/ia64/include/cpu.h (revision da52547b3a8fc0b23125d3adbd5622075264ee53) +++ kernel/arch/ia64/include/cpu.h (revision bbfdf62eecb75fb74d785cdd587affc613b7ffe9) @@ -40,7 +40,13 @@ #include #include +#include -#define FAMILY_ITANIUM 0x7 -#define FAMILY_ITANIUM2 0x1f +#define FAMILY_ITANIUM 0x7 +#define FAMILY_ITANIUM2 0x1f + +#define CR64_ID_SHIFT 24 +#define CR64_ID_MASK 0xff000000 +#define CR64_EID_SHIFT 16 +#define CR64_EID_MASK 0xff0000 typedef struct { @@ -55,38 +61,35 @@ * * @return Value of CPUID[n] register. + * */ -static inline uint64_t cpuid_read(int n) +NO_TRACE static inline uint64_t cpuid_read(int n) { uint64_t v; - asm volatile ("mov %0 = cpuid[%1]\n" : "=r" (v) : "r" (n)); + asm volatile ( + "mov %[v] = cpuid[%[r]]\n" + : [v] "=r" (v) + : [r] "r" (n) + ); return v; } - -#define CR64_ID_SHIFT 24 -#define CR64_ID_MASK 0xff000000 -#define CR64_EID_SHIFT 16 -#define CR64_EID_MASK 0xff0000 - -static inline int ia64_get_cpu_id(void) +NO_TRACE static inline int ia64_get_cpu_id(void) { - uint64_t cr64=cr64_read(); - return ((CR64_ID_MASK)&cr64)>>CR64_ID_SHIFT; + uint64_t cr64 = cr64_read(); + return ((CR64_ID_MASK) &cr64) >> CR64_ID_SHIFT; } -static inline int ia64_get_cpu_eid(void) +NO_TRACE static inline int ia64_get_cpu_eid(void) { - uint64_t cr64=cr64_read(); - return ((CR64_EID_MASK)&cr64)>>CR64_EID_SHIFT; + uint64_t cr64 = cr64_read(); + return ((CR64_EID_MASK) &cr64) >> CR64_EID_SHIFT; } - -static inline void ipi_send_ipi(int id, int eid, int intno) +NO_TRACE static inline void ipi_send_ipi(int id, int eid, int intno) { (bootinfo->sapic)[2 * (id * 256 + eid)] = intno; srlz_d(); - } Index: kernel/arch/ia64/include/cycle.h =================================================================== --- kernel/arch/ia64/include/cycle.h (revision da52547b3a8fc0b23125d3adbd5622075264ee53) +++ kernel/arch/ia64/include/cycle.h (revision bbfdf62eecb75fb74d785cdd587affc613b7ffe9) @@ -36,5 +36,7 @@ #define KERN_ia64_CYCLE_H_ -static inline uint64_t get_cycle(void) +#include + +NO_TRACE static inline uint64_t get_cycle(void) { return 0; Index: kernel/arch/ia64/include/interrupt.h =================================================================== --- kernel/arch/ia64/include/interrupt.h (revision da52547b3a8fc0b23125d3adbd5622075264ee53) +++ kernel/arch/ia64/include/interrupt.h (revision bbfdf62eecb75fb74d785cdd587affc613b7ffe9) @@ -38,4 +38,5 @@ #include #include +#include /** ia64 has 256 INRs. */ @@ -133,5 +134,8 @@ } istate_t; -static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr) +extern void *ivt; + +NO_TRACE static inline void istate_set_retaddr(istate_t *istate, + uintptr_t retaddr) { istate->cr_iip = retaddr; @@ -139,29 +143,29 @@ } -static inline unative_t istate_get_pc(istate_t *istate) +NO_TRACE static inline unative_t istate_get_pc(istate_t *istate) { return istate->cr_iip; } -static inline unative_t istate_get_fp(istate_t *istate) +NO_TRACE static inline unative_t istate_get_fp(istate_t *istate) { - return 0; /* FIXME */ + /* FIXME */ + + return 0; } -static inline int istate_from_uspace(istate_t *istate) +NO_TRACE static inline int istate_from_uspace(istate_t *istate) { return (istate->cr_iip) < 0xe000000000000000ULL; } -extern void *ivt; +extern void general_exception(uint64_t, istate_t *); +extern int break_instruction(uint64_t, istate_t *); +extern void universal_handler(uint64_t, istate_t *); +extern void nop_handler(uint64_t, istate_t *); +extern void external_interrupt(uint64_t, istate_t *); +extern void disabled_fp_register(uint64_t, istate_t *); -extern void general_exception(uint64_t vector, istate_t *istate); -extern int break_instruction(uint64_t vector, istate_t *istate); -extern void universal_handler(uint64_t vector, istate_t *istate); -extern void nop_handler(uint64_t vector, istate_t *istate); -extern void external_interrupt(uint64_t vector, istate_t *istate); -extern void disabled_fp_register(uint64_t vector, istate_t *istate); - -extern void trap_virtual_enable_irqs(uint16_t irqmask); +extern void trap_virtual_enable_irqs(uint16_t); #endif Index: kernel/arch/ia64/include/mm/page.h =================================================================== --- kernel/arch/ia64/include/mm/page.h (revision da52547b3a8fc0b23125d3adbd5622075264ee53) +++ kernel/arch/ia64/include/mm/page.h (revision bbfdf62eecb75fb74d785cdd587affc613b7ffe9) @@ -208,5 +208,5 @@ * @return Address of the head of VHPT collision chain. */ -static inline uint64_t thash(uint64_t va) +NO_TRACE static inline uint64_t thash(uint64_t va) { uint64_t ret; @@ -230,5 +230,5 @@ * @return The unique tag for VPN and RID in the collision chain returned by thash(). */ -static inline uint64_t ttag(uint64_t va) +NO_TRACE static inline uint64_t ttag(uint64_t va) { uint64_t ret; @@ -249,5 +249,5 @@ * @return Current contents of rr[i]. */ -static inline uint64_t rr_read(size_t i) +NO_TRACE static inline uint64_t rr_read(size_t i) { uint64_t ret; @@ -269,5 +269,5 @@ * @param v Value to be written to rr[i]. */ -static inline void rr_write(size_t i, uint64_t v) +NO_TRACE static inline void rr_write(size_t i, uint64_t v) { ASSERT(i < REGION_REGISTERS); @@ -284,5 +284,5 @@ * @return Current value stored in PTA. */ -static inline uint64_t pta_read(void) +NO_TRACE static inline uint64_t pta_read(void) { uint64_t ret; @@ -300,5 +300,5 @@ * @param v New value to be stored in PTA. */ -static inline void pta_write(uint64_t v) +NO_TRACE static inline void pta_write(uint64_t v) { asm volatile (