Index: arch/mips32/include/mm/page.h
===================================================================
--- arch/mips32/include/mm/page.h	(revision 8c5e6c749daf4b1aaa266e21aed9b6fdc3809b02)
+++ arch/mips32/include/mm/page.h	(revision ba1b2194cc406f4d64bc3c4f97a11c045ca42d60)
@@ -63,13 +63,13 @@
 #define SET_PTL0_ADDRESS_ARCH(ptl0)		(PTL0 = (pte_t *)(ptl0))
 
-#define GET_PTL1_ADDRESS_ARCH(ptl0, i)		(((pte_t *)(ptl0))[(i)].pfn<<12)
+#define GET_PTL1_ADDRESS_ARCH(ptl0, i)		(((pte_t *)(ptl0))[(i)].lo.pfn<<12)
 #define GET_PTL2_ADDRESS_ARCH(ptl1, i)		(ptl1)
 #define GET_PTL3_ADDRESS_ARCH(ptl2, i)		(ptl2)
-#define GET_FRAME_ADDRESS_ARCH(ptl3, i)		(((pte_t *)(ptl3))[(i)].pfn<<12)
+#define GET_FRAME_ADDRESS_ARCH(ptl3, i)		(((pte_t *)(ptl3))[(i)].lo.pfn<<12)
 
-#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)	(((pte_t *)(ptl0))[(i)].pfn = (a)>>12)
+#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)	(((pte_t *)(ptl0))[(i)].lo.pfn = (a)>>12)
 #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
 #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
-#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)	(((pte_t *)(ptl3))[(i)].pfn = (a)>>12)
+#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)	(((pte_t *)(ptl3))[(i)].lo.pfn = (a)>>12)
 
 #define GET_PTL1_FLAGS_ARCH(ptl0, i)		get_pt_flags((pte_t *)(ptl0), (index_t)(i))
@@ -95,6 +95,6 @@
 	
 	return (
-		((p->c>PAGE_UNCACHED)<<PAGE_CACHEABLE_SHIFT) |
-		((!p->v)<<PAGE_PRESENT_SHIFT) |
+		((p->lo.c>PAGE_UNCACHED)<<PAGE_CACHEABLE_SHIFT) |
+		((!p->lo.v)<<PAGE_PRESENT_SHIFT) |
 		(1<<PAGE_USER_SHIFT) |
 		(1<<PAGE_READ_SHIFT) |
@@ -109,6 +109,6 @@
 	pte_t *p = &pt[i];
 	
-	p->c = (flags & PAGE_CACHEABLE) != 0 ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
-	p->v = !(flags & PAGE_NOT_PRESENT);
+	p->lo.c = (flags & PAGE_CACHEABLE) != 0 ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
+	p->lo.v = !(flags & PAGE_NOT_PRESENT);
 	p->w = (flags & PAGE_WRITE) != 0;
 }
Index: arch/mips32/include/mm/tlb.h
===================================================================
--- arch/mips32/include/mm/tlb.h	(revision 8c5e6c749daf4b1aaa266e21aed9b6fdc3809b02)
+++ arch/mips32/include/mm/tlb.h	(revision ba1b2194cc406f4d64bc3c4f97a11c045ca42d60)
@@ -31,4 +31,5 @@
 
 #include <arch/exception.h>
+#include <typedefs.h>
 
 #define TLB_SIZE	48
@@ -41,4 +42,9 @@
 #define PAGE_UNCACHED			2
 #define PAGE_CACHEABLE_EXC_WRITE	5
+
+typedef union entry_lo entry_lo_t;
+typedef union entry_hi entry_hi_t;
+typedef union page_mask page_mask_t;
+typedef union index tlb_index_t;
 
 union entry_lo {
@@ -54,13 +60,12 @@
 };
 
-struct pte {
-	unsigned g : 1; 	/* global bit */
-	unsigned v : 1; 	/* valid bit */
-	unsigned d : 1; 	/* dirty/write-protect bit */
-	unsigned c : 3; 	/* cache coherency attribute */
-	unsigned pfn : 24;	/* frame number */
-	unsigned w : 1;		/* writable */
-	unsigned a : 1;		/* accessed */
-} __attribute__ ((packed));
+union pte {
+	entry_lo_t lo;
+	struct {
+		unsigned : 30;
+		unsigned w : 1;		/* writable */
+		unsigned a : 1;		/* accessed */
+	} __attribute__ ((packed));
+};
 
 union entry_hi {
@@ -90,9 +95,4 @@
 	__u32 value;
 };
-
-typedef union entry_lo entry_lo_t;
-typedef union entry_hi entry_hi_t;
-typedef union page_mask page_mask_t;
-typedef union index tlb_index_t;
 
 /** Probe TLB for Matching Entry
Index: arch/mips32/include/types.h
===================================================================
--- arch/mips32/include/types.h	(revision 8c5e6c749daf4b1aaa266e21aed9b6fdc3809b02)
+++ arch/mips32/include/types.h	(revision ba1b2194cc406f4d64bc3c4f97a11c045ca42d60)
@@ -50,5 +50,5 @@
 typedef __u32 __native;
 
-typedef struct pte pte_t;
+typedef union pte pte_t;
 
 #endif