Index: kernel/arch/ia32/src/drivers/i8254.c
===================================================================
--- kernel/arch/ia32/src/drivers/i8254.c	(revision d99c1d2ba8c7b2c687d430f2e9fd237046606545)
+++ kernel/arch/ia32/src/drivers/i8254.c	(revision b7398c034409791e32e89439b6f1e7e895d99e10)
@@ -54,9 +54,12 @@
 #include <ddi/device.h>
 
-#define CLK_PORT1	((ioport8_t *)0x40)
-#define CLK_PORT4	((ioport8_t *)0x43)
+#define CLK_PORT1  ((ioport8_t *) 0x40)
+#define CLK_PORT4  ((ioport8_t *) 0x43)
 
-#define CLK_CONST	1193180
-#define MAGIC_NUMBER	1194
+#define CLK_CONST     1193180
+#define MAGIC_NUMBER  1194
+
+#define LOOPS  150000
+#define SHIFT  11
 
 static irq_t i8254_irq;
@@ -75,7 +78,7 @@
 	 * lock. We just release it, call clock() and then reacquire it again.
 	 */
-	spinlock_unlock(&irq->lock);
+	irq_spinlock_unlock(&irq->lock, false);
 	clock();
-	spinlock_lock(&irq->lock);
+	irq_spinlock_lock(&irq->lock, false);
 }
 
@@ -102,13 +105,6 @@
 }
 
-#define LOOPS 150000
-#define SHIFT 11
 void i8254_calibrate_delay_loop(void)
 {
-	uint64_t clk1, clk2;
-	uint32_t t1, t2, o1, o2;
-	uint8_t not_ok;
-
-
 	/*
 	 * One-shot timer. Count-down from 0xffff at 1193180Hz
@@ -118,5 +114,9 @@
 	pio_write_8(CLK_PORT1, 0xff);
 	pio_write_8(CLK_PORT1, 0xff);
-
+	
+	uint8_t not_ok;
+	uint32_t t1;
+	uint32_t t2;
+	
 	do {
 		/* will read both status and count */
@@ -126,34 +126,34 @@
 		t1 |= pio_read_8(CLK_PORT1) << 8;
 	} while (not_ok);
-
+	
 	asm_delay_loop(LOOPS);
-
+	
 	pio_write_8(CLK_PORT4, 0xd2);
 	t2 = pio_read_8(CLK_PORT1);
 	t2 |= pio_read_8(CLK_PORT1) << 8;
-
+	
 	/*
 	 * We want to determine the overhead of the calibrating mechanism.
 	 */
 	pio_write_8(CLK_PORT4, 0xd2);
-	o1 = pio_read_8(CLK_PORT1);
+	uint32_t o1 = pio_read_8(CLK_PORT1);
 	o1 |= pio_read_8(CLK_PORT1) << 8;
-
+	
 	asm_fake_loop(LOOPS);
-
+	
 	pio_write_8(CLK_PORT4, 0xd2);
-	o2 = pio_read_8(CLK_PORT1);
+	uint32_t o2 = pio_read_8(CLK_PORT1);
 	o2 |= pio_read_8(CLK_PORT1) << 8;
-
+	
 	CPU->delay_loop_const =
 	    ((MAGIC_NUMBER * LOOPS) / 1000) / ((t1 - t2) - (o1 - o2)) +
 	    (((MAGIC_NUMBER * LOOPS) / 1000) % ((t1 - t2) - (o1 - o2)) ? 1 : 0);
-
-	clk1 = get_cycle();
+	
+	uint64_t clk1 = get_cycle();
 	delay(1 << SHIFT);
-	clk2 = get_cycle();
+	uint64_t clk2 = get_cycle();
 	
 	CPU->frequency_mhz = (clk2 - clk1) >> SHIFT;
-
+	
 	return;
 }
