Index: arch/sparc64/include/asm.h
===================================================================
--- arch/sparc64/include/asm.h	(revision 0d3ff9a3978f9e8a18d27ef1dd0ee2ea44191f3c)
+++ arch/sparc64/include/asm.h	(revision b6fba8431df1b966785360e74c0202b368c8d716)
@@ -237,4 +237,18 @@
 }
 
+/** Read Trap Program Counter register.
+ *
+ * @return Current value in TPC.
+ */
+static inline __u64 tpc_read(void)
+{
+	__u64 v;
+	
+	__asm__ volatile ("rdpr %%tpc, %0\n" : "=r" (v));
+	
+	return v;
+}
+
+
 /** Write Trap Base Address register.
  *
Index: arch/sparc64/include/mm/tlb.h
===================================================================
--- arch/sparc64/include/mm/tlb.h	(revision 0d3ff9a3978f9e8a18d27ef1dd0ee2ea44191f3c)
+++ arch/sparc64/include/mm/tlb.h	(revision b6fba8431df1b966785360e74c0202b368c8d716)
@@ -47,4 +47,13 @@
 #define PAGESIZE_4M	3
 
+union tlb_context_reg {
+	__u64 v;
+	struct {
+		unsigned long : 51;
+		unsigned context : 13;		/**< Context/ASID. */
+	} __attribute__ ((packed));
+};
+typedef union tlb_context_reg tlb_context_reg_t;
+
 /** I-/D-TLB Data In/Access Register type. */
 typedef tte_data_t tlb_data_t;
@@ -95,4 +104,62 @@
 typedef union tlb_demap_addr tlb_demap_addr_t;
 
+/** TLB Synchronous Fault Status Register. */
+union tlb_sfsr_reg {
+	__u64 value;
+	struct {
+		unsigned long : 39;	/**< Implementation dependent. */
+		unsigned nf : 1;	/**< Nonfaulting load. */
+		unsigned asi : 8;	/**< ASI. */
+		unsigned tm : 1;	/**< TLB miss. */
+		unsigned : 3;
+		unsigned ft : 5;	/**< Fault type. */
+		unsigned e : 1;		/**< Side-effect bit. */
+		unsigned ct : 2;	/**< Context Register selection. */
+		unsigned pr : 1;	/**< Privilege bit. */
+		unsigned w : 1;		/**< Write bit. */
+		unsigned ow : 1;	/**< Overwrite bit. */
+		unsigned fv : 1;	/**< Fayult Valid bit. */
+	} __attribute__ ((packed));
+};
+typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
+
+/** Read MMU Primary Context Register.
+ *
+ * @return Current value of Primary Context Register.
+ */
+static inline __u64 mmu_primary_context_read(void)
+{
+	return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
+}
+
+/** Write MMU Primary Context Register.
+ *
+ * @param v New value of Primary Context Register.
+ */
+static inline void mmu_primary_context_write(__u64 v)
+{
+	asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
+	flush();
+}
+
+/** Read MMU Secondary Context Register.
+ *
+ * @return Current value of Secondary Context Register.
+ */
+static inline __u64 mmu_secondary_context_read(void)
+{
+	return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
+}
+
+/** Write MMU Primary Context Register.
+ *
+ * @param v New value of Primary Context Register.
+ */
+static inline void mmu_secondary_context_write(__u64 v)
+{
+	asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
+	flush();
+}
+
 /** Read IMMU TLB Data Access Register.
  *
@@ -225,4 +292,51 @@
 }
 
+/** Read ITLB Synchronous Fault Status Register.
+ *
+ * @return Current content of I-SFSR register.
+ */
+static inline __u64 itlb_sfsr_read(void)
+{
+	return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
+}
+
+/** Write ITLB Synchronous Fault Status Register.
+ *
+ * @param v New value of I-SFSR register.
+ */
+static inline void itlb_sfsr_write(__u64 v)
+{
+	asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
+	flush();
+}
+
+/** Read DTLB Synchronous Fault Status Register.
+ *
+ * @return Current content of D-SFSR register.
+ */
+static inline __u64 dtlb_sfsr_read(void)
+{
+	return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
+}
+
+/** Write DTLB Synchronous Fault Status Register.
+ *
+ * @param v New value of D-SFSR register.
+ */
+static inline void dtlb_sfsr_write(__u64 v)
+{
+	asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
+	flush();
+}
+
+/** Read DTLB Synchronous Fault Address Register.
+ *
+ * @return Current content of D-SFAR register.
+ */
+static inline __u64 dtlb_sfar_read(void)
+{
+	return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
+}
+
 /** Perform IMMU TLB Demap Operation.
  *
Index: arch/sparc64/src/mm/memory_init.c
===================================================================
--- arch/sparc64/src/mm/memory_init.c	(revision 0d3ff9a3978f9e8a18d27ef1dd0ee2ea44191f3c)
+++ arch/sparc64/src/mm/memory_init.c	(revision b6fba8431df1b966785360e74c0202b368c8d716)
@@ -1,4 +1,4 @@
 /*
- * Copyright (C) 2005 Jakub Jermar
+ * Copyright (C) 2006 Jakub Jermar
  * All rights reserved.
  *
Index: arch/sparc64/src/mm/tlb.c
===================================================================
--- arch/sparc64/src/mm/tlb.c	(revision 0d3ff9a3978f9e8a18d27ef1dd0ee2ea44191f3c)
+++ arch/sparc64/src/mm/tlb.c	(revision b6fba8431df1b966785360e74c0202b368c8d716)
@@ -38,4 +38,13 @@
 #include <arch/trap/trap.h>
 #include <panic.h>
+#include <arch/asm.h>
+#include <symtab.h>
+
+char *context_encoding[] = {
+	"Primary",
+	"Secondary",
+	"Nucleus",
+	"Reserved"
+};
 
 /** Initialize ITLB and DTLB.
@@ -97,4 +106,29 @@
 	dmmu_enable();
 	immu_enable();
+	
+	/*
+	 * Quick hack: map frame buffer
+	 */
+	fr.address = 0x1C901000000ULL;
+	pg.address = 0xc0000000;
+
+	tag.value = 0;
+	tag.vpn = pg.vpn;
+
+	dtlb_tag_access_write(tag.value);
+
+	data.value = 0;
+	data.v = true;
+	data.size = PAGESIZE_4M;
+	data.pfn = fr.pfn;
+	data.l = true;
+	data.cp = 0;
+	data.cv = 0;
+	data.p = true;
+	data.w = true;
+	data.g = true;
+
+	dtlb_data_in_write(data.value);
+
 }
 
@@ -108,4 +142,16 @@
 void fast_data_access_mmu_miss(void)
 {
+	tlb_sfsr_reg_t status;
+	__address address, tpc;
+	char *tpc_str;
+	
+	status.value = dtlb_sfsr_read();
+	address = dtlb_sfar_read();
+	tpc = tpc_read();
+	tpc_str = get_symtab_entry(tpc);
+
+	printf("ASI=%B, Context=%s\n", status.asi, context_encoding[status.ct]);
+	printf("Faulting address: %P\n", dtlb_sfar_read());
+	printf("TPC=%P, (%s)\n", tpc, tpc_str ? tpc_str : "?");
 	panic("%s\n", __FUNCTION__);
 }