Index: arch/ia64/include/context.h
===================================================================
--- arch/ia64/include/context.h	(revision 50fe6209a60488b15153a65e9d3d222eae0168f9)
+++ arch/ia64/include/context.h	(revision b6d4566fc9565b3a6eff5c6344350e4dbf778359)
@@ -37,5 +37,5 @@
 
 /*
- * context_save() and context_restore() are both leaf procedures.
+ * context_save_arch() and context_restore_arch() are both leaf procedures.
  * No need to allocate scratch area.
  *
@@ -48,10 +48,12 @@
 #endif
 
-/*RSE stack should begin under bottom of stack @ kernel*/
-#define context_set(c, _pc, stack, size) 								\
-	(c)->pc = (__address) _pc;									\
-	(c)->bsp = ((__address) stack) + ALIGN_UP((size), STACK_ALIGNMENT) ;	\
-	(c)->ar_pfs &= PFM_MASK; 									\
-	(c)->sp = ((__address) stack) + ALIGN_UP((size), STACK_ALIGNMENT) - SP_DELTA;
+/* RSE stack starts at the bottom of memory stack. */
+#define context_set(c, _pc, stack, size)								\
+	do {												\
+		(c)->pc = (__address) _pc;								\
+		(c)->bsp = ((__address) stack) + ALIGN_UP((size), REGISTER_STACK_ALIGNMENT);		\
+		(c)->ar_pfs &= PFM_MASK; 								\
+		(c)->sp = ((__address) stack) + ALIGN_UP((size), STACK_ALIGNMENT) - SP_DELTA;		\
+	} while (0);
 
 /*
@@ -123,5 +125,3 @@
 };
 
-
-
 #endif
Index: arch/ia64/include/mm/tlb.h
===================================================================
--- arch/ia64/include/mm/tlb.h	(revision 50fe6209a60488b15153a65e9d3d222eae0168f9)
+++ arch/ia64/include/mm/tlb.h	(revision b6d4566fc9565b3a6eff5c6344350e4dbf778359)
@@ -42,5 +42,6 @@
 #define DTR_KERNEL	0
 #define ITR_KERNEL	0
-#define DTR_KSTACK	1
+#define DTR_KSTACK1	1
+#define DTR_KSTACK2	2
 
 /** Portion of TLB insertion format data structure. */
Index: arch/ia64/src/ivt.S
===================================================================
--- arch/ia64/src/ivt.S	(revision 50fe6209a60488b15153a65e9d3d222eae0168f9)
+++ arch/ia64/src/ivt.S	(revision b6d4566fc9565b3a6eff5c6344350e4dbf778359)
@@ -33,9 +33,6 @@
 #include <align.h>
 
-
 #define FRS_TO_SAVE 30
 #define STACK_ITEMS		(19 + FRS_TO_SAVE*2)
-//#define STACK_ITEMS		19 		
-	/* 30*2 for FPU registers */
 #define STACK_FRAME_SIZE	ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
 
Index: arch/ia64/src/proc/scheduler.c
===================================================================
--- arch/ia64/src/proc/scheduler.c	(revision 50fe6209a60488b15153a65e9d3d222eae0168f9)
+++ arch/ia64/src/proc/scheduler.c	(revision b6d4566fc9565b3a6eff5c6344350e4dbf778359)
@@ -44,10 +44,11 @@
 	base = ALIGN_DOWN(config.base, 1<<KERNEL_PAGE_WIDTH);
 
-	if ((__address) THREAD->kstack < base || (__address) THREAD->kstack > base + (1<<KERNEL_PAGE_WIDTH)) {
+	if ((__address) THREAD->kstack < base || (__address) THREAD->kstack > base + (1<<(KERNEL_PAGE_WIDTH))) {
 		/*
 		 * Kernel stack of this thread is not mapped by DTR[TR_KERNEL].
-		 * Use DTR[TR_KSTACK] to map it.
+		 * Use DTR[TR_KSTACK1] and DTR[TR_KSTACK2] to map it.
 		 */
-		 dtlb_kernel_mapping_insert((__address) THREAD->kstack, KA2PA(THREAD->kstack), true, DTR_KSTACK);
+		dtlb_kernel_mapping_insert((__address) THREAD->kstack, KA2PA(THREAD->kstack), true, DTR_KSTACK1);
+		dtlb_kernel_mapping_insert((__address) THREAD->kstack + PAGE_SIZE, KA2PA(THREAD->kstack) + FRAME_SIZE, true, DTR_KSTACK2);
 	}