Index: kernel/arch/arm32/src/asm.S =================================================================== --- kernel/arch/arm32/src/asm.S (revision 93d8022e9ee8dcf2dc81eb3c64004042947f578c) +++ kernel/arch/arm32/src/asm.S (revision b66cc977e145eaa74a7e9fe52a4a2e995c81ad02) @@ -27,14 +27,10 @@ */ +#include + .text -.global memcpy_from_uspace -.global memcpy_to_uspace -.global memcpy_from_uspace_failover_address -.global memcpy_to_uspace_failover_address -.global early_putchar - -memcpy_from_uspace: -memcpy_to_uspace: +FUNCTION_BEGIN(memcpy_from_uspace) +FUNCTION_BEGIN(memcpy_to_uspace) add r3, r1, #3 bic r3, r3, #3 @@ -94,10 +90,14 @@ bne 7b b 3b +FUNCTION_END(memcpy_from_uspace) +FUNCTION_END(memcpy_to_uspace) -memcpy_from_uspace_failover_address: -memcpy_to_uspace_failover_address: +SYMBOL(memcpy_from_uspace_failover_address) +SYMBOL(memcpy_to_uspace_failover_address) mov r0, #0 ldmia sp!, {r4, r5, pc} -early_putchar: +FUNCTION_BEGIN(early_putchar) mov pc, lr +FUNCTION_END(early_putchar) + Index: kernel/arch/arm32/src/context.S =================================================================== --- kernel/arch/arm32/src/context.S (revision 93d8022e9ee8dcf2dc81eb3c64004042947f578c) +++ kernel/arch/arm32/src/context.S (revision b66cc977e145eaa74a7e9fe52a4a2e995c81ad02) @@ -27,10 +27,9 @@ # +#include + .text -.global context_save_arch -.global context_restore_arch - -context_save_arch: +FUNCTION_BEGIN(context_save_arch) stmfd sp!, {r1} mrs r1, cpsr @@ -44,7 +43,7 @@ mov r0, #1 mov pc, lr +FUNCTION_END(context_save_arch) - -context_restore_arch: +FUNCTION_BEGIN(context_restore_arch) ldmia r0!, {r4} mrs r5, cpsr @@ -58,2 +57,4 @@ mov r0, #0 mov pc, lr +FUNCTION_END(context_restore_arch) + Index: kernel/arch/arm32/src/debug/stacktrace_asm.S =================================================================== --- kernel/arch/arm32/src/debug/stacktrace_asm.S (revision 93d8022e9ee8dcf2dc81eb3c64004042947f578c) +++ kernel/arch/arm32/src/debug/stacktrace_asm.S (revision b66cc977e145eaa74a7e9fe52a4a2e995c81ad02) @@ -27,14 +27,16 @@ # +#include + .text -.global frame_pointer_get -.global program_counter_get - -frame_pointer_get: +FUNCTION_BEGIN(frame_pointer_get) mov r0, fp mov pc, lr +FUNCTION_END(frame_pointer_get) -program_counter_get: +FUNCTION_BEGIN(program_counter_get) mov r0, lr mov pc, lr +FUNCTION_END(program_counter_get) + Index: kernel/arch/arm32/src/dummy.S =================================================================== --- kernel/arch/arm32/src/dummy.S (revision 93d8022e9ee8dcf2dc81eb3c64004042947f578c) +++ kernel/arch/arm32/src/dummy.S (revision b66cc977e145eaa74a7e9fe52a4a2e995c81ad02) @@ -27,21 +27,21 @@ # +#include + .text -.global calibrate_delay_loop -.global asm_delay_loop +FUNCTION_BEGIN(calibrate_delay_loop) + mov pc, lr +FUNCTION_END(calibrate_delay_loop) -.global sys_tls_set -.global dummy - -calibrate_delay_loop: +FUNCTION_BEGIN(asm_delay_loop) mov pc, lr - -asm_delay_loop: - mov pc, lr +FUNCTION_END(asm_delay_loop) # not used on ARM -sys_tls_set: +FUNCTION_BEGIN(sys_tls_set) +FUNCTION_BEGIN(dummy) + mov pc, lr +FUNCTION_END(dummy) +FUNCTION_END(sys_tls_set) -dummy: - mov pc, lr Index: kernel/arch/arm32/src/eabi.S =================================================================== --- kernel/arch/arm32/src/eabi.S (revision 93d8022e9ee8dcf2dc81eb3c64004042947f578c) +++ kernel/arch/arm32/src/eabi.S (revision b66cc977e145eaa74a7e9fe52a4a2e995c81ad02) @@ -27,28 +27,23 @@ # +#include + .text -.global __aeabi_idiv -.global __aeabi_uidiv - -.global __aeabi_idivmod -.global __aeabi_uidivmod - -.global __aeabi_ldivmod -.global __aeabi_uldivmod - -__aeabi_idiv: +FUNCTION_BEGIN(__aeabi_idiv) push {lr} bl __divsi3 pop {lr} mov pc, lr +FUNCTION_END(__aeabi_idiv) -__aeabi_uidiv: +FUNCTION_BEGIN(__aeabi_uidiv) push {lr} bl __udivsi3 pop {lr} mov pc, lr +FUNCTION_END(__aeabi_uidiv) -__aeabi_idivmod: +FUNCTION_BEGIN(__aeabi_idivmod) push {lr} sub sp, sp, #12 @@ -59,6 +54,7 @@ pop {lr} mov pc, lr +FUNCTION_END(__aeabi_idivmod) -__aeabi_uidivmod: +FUNCTION_BEGIN(__aeabi_uidivmod) push {lr} sub sp, sp, #12 @@ -69,6 +65,7 @@ pop {lr} mov pc, lr +FUNCTION_END(__aeabi_uidivmod) -__aeabi_ldivmod: +FUNCTION_BEGIN(__aeabi_ldivmod) push {lr} sub sp, sp, #24 @@ -80,6 +77,7 @@ pop {lr} mov pc, lr +FUNCTION_END(__aeabi_ldivmod) -__aeabi_uldivmod: +FUNCTION_BEGIN(__aeabi_uldivmod) push {lr} sub sp, sp, #24 @@ -91,2 +89,4 @@ pop {lr} mov pc, lr +FUNCTION_END(__aeabi_uldivmod) + Index: kernel/arch/arm32/src/exc_handler.S =================================================================== --- kernel/arch/arm32/src/exc_handler.S (revision 93d8022e9ee8dcf2dc81eb3c64004042947f578c) +++ kernel/arch/arm32/src/exc_handler.S (revision b66cc977e145eaa74a7e9fe52a4a2e995c81ad02) @@ -27,14 +27,7 @@ # +#include + .text - -.global irq_exception_entry -.global fiq_exception_entry -.global data_abort_exception_entry -.global prefetch_abort_exception_entry -.global undef_instr_exception_entry -.global swi_exception_entry -.global reset_exception_entry - # Switches to kernel stack and saves all registers there. @@ -156,5 +149,5 @@ .endm -reset_exception_entry: +SYMBOL(reset_exception_entry) SAVE_REGS_TO_STACK mov r0, #0 @@ -163,5 +156,5 @@ LOAD_REGS_FROM_STACK -irq_exception_entry: +SYMBOL(irq_exception_entry) sub lr, lr, #4 SAVE_REGS_TO_STACK @@ -171,5 +164,5 @@ LOAD_REGS_FROM_STACK -fiq_exception_entry: +SYMBOL(fiq_exception_entry) sub lr, lr, #4 SAVE_REGS_TO_STACK @@ -179,5 +172,5 @@ LOAD_REGS_FROM_STACK -undef_instr_exception_entry: +SYMBOL(undef_instr_exception_entry) SAVE_REGS_TO_STACK mov r0, #1 @@ -186,5 +179,5 @@ LOAD_REGS_FROM_STACK -prefetch_abort_exception_entry: +SYMBOL(prefetch_abort_exception_entry) sub lr, lr, #4 SAVE_REGS_TO_STACK @@ -194,5 +187,5 @@ LOAD_REGS_FROM_STACK -data_abort_exception_entry: +SYMBOL(data_abort_exception_entry) sub lr, lr, #8 SAVE_REGS_TO_STACK @@ -202,5 +195,5 @@ LOAD_REGS_FROM_STACK -swi_exception_entry: +SYMBOL(swi_exception_entry) ldr r13, =exc_stack SAVE_REGS_TO_STACK Index: kernel/arch/arm32/src/fpu.S =================================================================== --- kernel/arch/arm32/src/fpu.S (revision b66cc977e145eaa74a7e9fe52a4a2e995c81ad02) +++ kernel/arch/arm32/src/fpu.S (revision b66cc977e145eaa74a7e9fe52a4a2e995c81ad02) @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2013 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +.text + +FUNCTION_BEGIN(fpsid_read) + vmrs r0, fpsid + mov pc, lr +FUNCTION_END(fpsid_read) + +FUNCTION_BEGIN(mvfr0_read) + vmrs r0, mvfr0 + mov pc, lr +FUNCTION_END(mvfr0_read) + +FUNCTION_BEGIN(fpscr_read) + vmrs r0, fpscr + mov pc, lr +FUNCTION_END(fpscr_read) + +FUNCTION_BEGIN(fpscr_write) + vmsr fpscr, r0 + mov pc, lr +FUNCTION_END(fpscr_write) + +FUNCTION_BEGIN(fpexc_read) + vmrs r0, fpexc + mov pc, lr +FUNCTION_END(fpexc_read) + +FUNCTION_BEGIN(fpexc_write) + vmsr fpexc, r0 + mov pc, lr +FUNCTION_END(fpexc_write) + +FUNCTION_BEGIN(fpu_context_save_s32) + vmrs r1, fpexc + vmrs r2, fpscr + stmia r0!, {r1, r2} + vstmia r0!, {s0-s31} + mov pc, lr +FUNCTION_END(fpu_context_save_s32) + +FUNCTION_BEGIN(fpu_context_restore_s32) + ldmia r0!, {r1, r2} + vmsr fpexc, r1 + vmsr fpscr, r2 + vldmia r0!, {s0-s31} + mov pc, lr +FUNCTION_END(fpu_context_restore_s32) + +FUNCTION_BEGIN(fpu_context_save_d16) + vmrs r1, fpexc + vmrs r2, fpscr + stmia r0!, {r1, r2} + vstmia r0!, {d0-d15} + mov pc, lr +FUNCTION_END(fpu_context_save_d16) + +FUNCTION_BEGIN(fpu_context_restore_d16) + ldmia r0!, {r1, r2} + vmsr fpexc, r1 + vmsr fpscr, r2 + vldmia r0!, {d0-d15} + mov pc, lr +FUNCTION_END(fpu_context_restore_d16) + +FUNCTION_BEGIN(fpu_context_save_d32) + vmrs r1, fpexc + stmia r0!, {r1} + vmrs r1, fpscr + stmia r0!, {r1} + vstmia r0!, {d0-d15} + vstmia r0!, {d16-d31} + mov pc, lr +FUNCTION_END(fpu_context_save_d32) + +FUNCTION_BEGIN(fpu_context_restore_d32) + ldmia r0!, {r1, r2} + vmsr fpexc, r1 + vmsr fpscr, r2 + vldmia r0!, {d0-d15} + vldmia r0!, {d16-d31} + mov pc, lr +FUNCTION_END(fpu_context_restore_d32) + Index: kernel/arch/arm32/src/fpu.s =================================================================== --- kernel/arch/arm32/src/fpu.s (revision 93d8022e9ee8dcf2dc81eb3c64004042947f578c) +++ (revision ) @@ -1,115 +1,0 @@ -/* - * Copyright (c) 2013 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -.text - -.global fpsid_read -.global mvfr0_read -.global fpscr_read -.global fpscr_write -.global fpexc_read -.global fpexc_write - -.global fpu_context_save_s32 -.global fpu_context_restore_s32 -.global fpu_context_save_d16 -.global fpu_context_restore_d16 -.global fpu_context_save_d32 -.global fpu_context_restore_d32 - -fpsid_read: - vmrs r0, fpsid - mov pc, lr - -mvfr0_read: - vmrs r0, mvfr0 - mov pc, lr - -fpscr_read: - vmrs r0, fpscr - mov pc, lr - -fpscr_write: - vmsr fpscr, r0 - mov pc, lr - -fpexc_read: - vmrs r0, fpexc - mov pc, lr - -fpexc_write: - vmsr fpexc, r0 - mov pc, lr - -fpu_context_save_s32: - vmrs r1, fpexc - vmrs r2, fpscr - stmia r0!, {r1, r2} - vstmia r0!, {s0-s31} - mov pc, lr - -fpu_context_restore_s32: - ldmia r0!, {r1, r2} - vmsr fpexc, r1 - vmsr fpscr, r2 - vldmia r0!, {s0-s31} - mov pc, lr - -fpu_context_save_d16: - vmrs r1, fpexc - vmrs r2, fpscr - stmia r0!, {r1, r2} - vstmia r0!, {d0-d15} - mov pc, lr - -fpu_context_restore_d16: - ldmia r0!, {r1, r2} - vmsr fpexc, r1 - vmsr fpscr, r2 - vldmia r0!, {d0-d15} - mov pc, lr - -fpu_context_save_d32: - vmrs r1, fpexc - stmia r0!, {r1} - vmrs r1, fpscr - stmia r0!, {r1} - vstmia r0!, {d0-d15} - vstmia r0!, {d16-d31} - mov pc, lr - -fpu_context_restore_d32: - ldmia r0!, {r1, r2} - vmsr fpexc, r1 - vmsr fpscr, r2 - vldmia r0!, {d0-d15} - vldmia r0!, {d16-d31} - mov pc, lr - - - Index: kernel/arch/arm32/src/start.S =================================================================== --- kernel/arch/arm32/src/start.S (revision 93d8022e9ee8dcf2dc81eb3c64004042947f578c) +++ kernel/arch/arm32/src/start.S (revision b66cc977e145eaa74a7e9fe52a4a2e995c81ad02) @@ -27,14 +27,10 @@ # +#include #include .text -.global kernel_image_start -.global exc_stack -.global supervisor_sp - -kernel_image_start: - +SYMBOL(kernel_image_start) # initialize Stack pointer for exception modes mrs r4, cpsr @@ -83,6 +79,6 @@ .space 1024 -exc_stack: +SYMBOL(exc_stack) -supervisor_sp: +SYMBOL(supervisor_sp) .space 4