Index: arch/ia64/src/mm/frame.c
===================================================================
--- arch/ia64/src/mm/frame.c	(revision 071a8ae65d845056114dc46ddf5f627eb2d83640)
+++ arch/ia64/src/mm/frame.c	(revision b5e0bb89845d4997122e319a7f34a8545ed548ff)
@@ -45,4 +45,5 @@
 	 */
 	frame_region_not_free(ROM_BASE, ROM_SIZE);
-        zone_create_in_region(0, config.memory_size & ~(FRAME_SIZE-1));
+	
+	zone_create_in_region(0, config.memory_size & ~(FRAME_SIZE-1));
 }
Index: arch/sparc64/include/barrier.h
===================================================================
--- arch/sparc64/include/barrier.h	(revision 071a8ae65d845056114dc46ddf5f627eb2d83640)
+++ arch/sparc64/include/barrier.h	(revision b5e0bb89845d4997122e319a7f34a8545ed548ff)
@@ -52,3 +52,8 @@
 }
 
+static inline void membar(void)
+{
+	__asm__ volatile ("membar #Sync\n");
+}
+
 #endif
Index: arch/sparc64/include/mm/mmu.h
===================================================================
--- arch/sparc64/include/mm/mmu.h	(revision 071a8ae65d845056114dc46ddf5f627eb2d83640)
+++ arch/sparc64/include/mm/mmu.h	(revision b5e0bb89845d4997122e319a7f34a8545ed548ff)
@@ -111,5 +111,5 @@
 	cr.im = enable;
 	asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value);
-	flush();
+	membar();
 }
 
@@ -122,5 +122,5 @@
 	cr.dm = enable;
 	asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value);
-	flush();
+	membar();
 }
 
Index: arch/sparc64/include/mm/page.h
===================================================================
--- arch/sparc64/include/mm/page.h	(revision 071a8ae65d845056114dc46ddf5f627eb2d83640)
+++ arch/sparc64/include/mm/page.h	(revision b5e0bb89845d4997122e319a7f34a8545ed548ff)
@@ -42,5 +42,5 @@
 
 /** Implementation of page hash table interface. */
-#define HT_WIDTH_ARCH			FRAME_WIDTH
+#define HT_WIDTH_ARCH			20	/* 1M */
 #define HT_HASH_ARCH(page, asid)	0
 #define HT_COMPARE_ARCH(page, asid, t)	0