Index: kernel/arch/sparc64/Makefile.inc =================================================================== --- kernel/arch/sparc64/Makefile.inc (revision 66e08d02d119283121b700c6a8f1a282651e2561) +++ kernel/arch/sparc64/Makefile.inc (revision b4655da89eb65d1571b8afdfdbbb34449add2ef7) @@ -64,5 +64,5 @@ ARCH_SOURCES = \ - arch/$(KARCH)/src/cpu/cpu.c \ + arch/$(KARCH)/src/cpu/$(USARCH)/cpu.c \ arch/$(KARCH)/src/asm.S \ arch/$(KARCH)/src/panic.S \ @@ -94,5 +94,6 @@ ifeq ($(USARCH),sun4v) ARCH_SOURCES += \ - arch/$(KARCH)/src/drivers/niagara.c + arch/$(KARCH)/src/drivers/niagara.c \ + arch/$(KARCH)/src/sun4v/md.c endif @@ -110,4 +111,4 @@ ifeq ($(CONFIG_TSB),y) ARCH_SOURCES += \ - arch/$(KARCH)/src/mm/tsb.c + arch/$(KARCH)/src/mm/$(USARCH)/tsb.c endif Index: kernel/arch/sparc64/include/drivers/tick.h =================================================================== --- kernel/arch/sparc64/include/drivers/tick.h (revision 66e08d02d119283121b700c6a8f1a282651e2561) +++ kernel/arch/sparc64/include/drivers/tick.h (revision b4655da89eb65d1571b8afdfdbbb34449add2ef7) @@ -36,8 +36,20 @@ #define KERN_sparc64_TICK_H_ +#include #include + +/* mask of the "counter" field of the Tick register */ +#define TICK_COUNTER_MASK (~(1l << 63)) extern void tick_init(void); extern void tick_interrupt(int n, istate_t *istate); + +/** + * Reads the Tick register counter. + */ +static inline uint64_t tick_counter_read(void) +{ + return TICK_COUNTER_MASK & tick_read(); +} #endif Index: kernel/arch/sparc64/include/mm/tte.h =================================================================== --- kernel/arch/sparc64/include/mm/tte.h (revision 66e08d02d119283121b700c6a8f1a282651e2561) +++ kernel/arch/sparc64/include/mm/tte.h (revision b4655da89eb65d1571b8afdfdbbb34449add2ef7) @@ -36,66 +36,9 @@ #define KERN_sparc64_TTE_H_ -#define TTE_G (1 << 0) -#define TTE_W (1 << 1) -#define TTE_P (1 << 2) -#define TTE_E (1 << 3) -#define TTE_CV (1 << 4) -#define TTE_CP (1 << 5) -#define TTE_L (1 << 6) - -#define TTE_V_SHIFT 63 -#define TTE_SIZE_SHIFT 61 - -#ifndef __ASM__ - -#include - -/* TTE tag's VA_tag field contains bits <63:VA_TAG_PAGE_SHIFT> of the VA */ -#define VA_TAG_PAGE_SHIFT 22 - -/** Translation Table Entry - Tag. */ -union tte_tag { - uint64_t value; - struct { - unsigned g : 1; /**< Global. */ - unsigned : 2; /**< Reserved. */ - unsigned context : 13; /**< Context identifier. */ - unsigned : 6; /**< Reserved. */ - uint64_t va_tag : 42; /**< Virtual Address Tag, bits 63:22. */ - } __attribute__ ((packed)); -}; - -typedef union tte_tag tte_tag_t; - -/** Translation Table Entry - Data. */ -union tte_data { - uint64_t value; - struct { - unsigned v : 1; /**< Valid. */ - unsigned size : 2; /**< Page size of this entry. */ - unsigned nfo : 1; /**< No-Fault-Only. */ - unsigned ie : 1; /**< Invert Endianness. */ - unsigned soft2 : 9; /**< Software defined field. */ -#if defined (US) - unsigned diag : 9; /**< Diagnostic data. */ - unsigned pfn : 28; /**< Physical Address bits, bits 40:13. */ -#elif defined (US3) - unsigned : 7; /**< Reserved. */ - unsigned pfn : 30; /**< Physical Address bits, bits 42:13 */ +#if defined (SUN4U) +#include +#elif defined (SUN4V) +#include #endif - unsigned soft : 6; /**< Software defined field. */ - unsigned l : 1; /**< Lock. */ - unsigned cp : 1; /**< Cacheable in physically indexed cache. */ - unsigned cv : 1; /**< Cacheable in virtually indexed cache. */ - unsigned e : 1; /**< Side-effect. */ - unsigned p : 1; /**< Privileged. */ - unsigned w : 1; /**< Writable. */ - unsigned g : 1; /**< Global. */ - } __attribute__ ((packed)); -}; - -typedef union tte_data tte_data_t; - -#endif /* !def __ASM__ */ #endif Index: kernel/arch/sparc64/src/cpu/cpu.c =================================================================== --- kernel/arch/sparc64/src/cpu/cpu.c (revision 66e08d02d119283121b700c6a8f1a282651e2561) +++ (revision ) @@ -1,189 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#include -#include -#include -#include -#include -#include -#include - -/** - * Finds out the clock frequency of the current CPU. - * - * @param node node representing the current CPU in the OFW tree - * @return clock frequency if "node" is the current CPU and no error - * occurs, -1 if "node" is not the current CPU or on error - */ -static int find_cpu_frequency(ofw_tree_node_t *node) -{ - ofw_tree_property_t *prop; - uint32_t mid; - - /* 'upa-portid' for US, 'portid' for US-III, 'cpuid' for US-IV */ - prop = ofw_tree_getprop(node, "upa-portid"); - if ((!prop) || (!prop->value)) - prop = ofw_tree_getprop(node, "portid"); - if ((!prop) || (!prop->value)) - prop = ofw_tree_getprop(node, "cpuid"); - - if (prop && prop->value) { - mid = *((uint32_t *) prop->value); - if (mid == CPU->arch.mid) { - prop = ofw_tree_getprop(node, "clock-frequency"); - if (prop && prop->value) { - return *((uint32_t *) prop->value); - } - } - } - - return -1; -} - -/** Perform sparc64 specific initialization of the processor structure for the - * current processor. - */ -void cpu_arch_init(void) -{ - ofw_tree_node_t *node; - uint32_t clock_frequency = 0; - - CPU->arch.mid = read_mid(); - - /* - * Detect processor frequency. - */ - if (is_us() || is_us_iii()) { - node = ofw_tree_find_child_by_device_type(cpus_parent(), "cpu"); - while (node) { - int f = find_cpu_frequency(node); - if (f != -1) - clock_frequency = (uint32_t) f; - node = ofw_tree_find_peer_by_device_type(node, "cpu"); - } - } else if (is_us_iv()) { - node = ofw_tree_find_child(cpus_parent(), "cmp"); - while (node) { - int f; - f = find_cpu_frequency( - ofw_tree_find_child(node, "cpu@0")); - if (f != -1) - clock_frequency = (uint32_t) f; - f = find_cpu_frequency( - ofw_tree_find_child(node, "cpu@1")); - if (f != -1) - clock_frequency = (uint32_t) f; - node = ofw_tree_find_peer_by_name(node, "cmp"); - } - } - - CPU->arch.clock_frequency = clock_frequency; - tick_init(); -} - -/** Read version information from the current processor. */ -void cpu_identify(void) -{ - CPU->arch.ver.value = ver_read(); -} - -/** Print version information for a processor. - * - * This function is called by the bootstrap processor. - * - * @param m Processor structure of the CPU for which version information is to - * be printed. - */ -void cpu_print_report(cpu_t *m) -{ - char *manuf, *impl; - - switch (m->arch.ver.manuf) { - case MANUF_FUJITSU: - manuf = "Fujitsu"; - break; - case MANUF_ULTRASPARC: - manuf = "UltraSPARC"; - break; - case MANUF_SUN: - manuf = "Sun"; - break; - default: - manuf = "Unknown"; - break; - } - - switch (CPU->arch.ver.impl) { - case IMPL_ULTRASPARCI: - impl = "UltraSPARC I"; - break; - case IMPL_ULTRASPARCII: - impl = "UltraSPARC II"; - break; - case IMPL_ULTRASPARCII_I: - impl = "UltraSPARC IIi"; - break; - case IMPL_ULTRASPARCII_E: - impl = "UltraSPARC IIe"; - break; - case IMPL_ULTRASPARCIII: - impl = "UltraSPARC III"; - break; - case IMPL_ULTRASPARCIII_PLUS: - impl = "UltraSPARC III+"; - break; - case IMPL_ULTRASPARCIII_I: - impl = "UltraSPARC IIIi"; - break; - case IMPL_ULTRASPARCIV: - impl = "UltraSPARC IV"; - break; - case IMPL_ULTRASPARCIV_PLUS: - impl = "UltraSPARC IV+"; - break; - case IMPL_SPARC64V: - impl = "SPARC 64V"; - break; - default: - impl = "Unknown"; - break; - } - - printf("cpu%d: manuf=%s, impl=%s, mask=%d (%d MHz)\n", m->id, manuf, - impl, m->arch.ver.mask, m->arch.clock_frequency / 1000000); -} - -/** @} - */ Index: kernel/arch/sparc64/src/drivers/tick.c =================================================================== --- kernel/arch/sparc64/src/drivers/tick.c (revision 66e08d02d119283121b700c6a8f1a282651e2561) +++ kernel/arch/sparc64/src/drivers/tick.c (revision b4655da89eb65d1571b8afdfdbbb34449add2ef7) @@ -54,10 +54,10 @@ interrupt_register(14, "tick_int", tick_interrupt); compare.int_dis = false; - compare.tick_cmpr = CPU->arch.clock_frequency / HZ; + compare.tick_cmpr = tick_counter_read() + + CPU->arch.clock_frequency / HZ; CPU->arch.next_tick_cmpr = compare.tick_cmpr; tick_compare_write(compare.value); - tick_write(0); -#if defined (US3) +#if defined (US3) || defined (SUN4V) /* disable STICK interrupts and clear any pending ones */ tick_compare_reg_t stick_compare; @@ -111,10 +111,10 @@ * overflow only in 146 years. */ - drift = tick_read() - CPU->arch.next_tick_cmpr; + drift = tick_counter_read() - CPU->arch.next_tick_cmpr; while (drift > CPU->arch.clock_frequency / HZ) { drift -= CPU->arch.clock_frequency / HZ; CPU->missed_clock_ticks++; } - CPU->arch.next_tick_cmpr = tick_read() + + CPU->arch.next_tick_cmpr = tick_counter_read() + (CPU->arch.clock_frequency / HZ) - drift; tick_compare_write(CPU->arch.next_tick_cmpr); Index: kernel/arch/sparc64/src/mm/sun4v/tlb.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4v/tlb.c (revision 66e08d02d119283121b700c6a8f1a282651e2561) +++ kernel/arch/sparc64/src/mm/sun4v/tlb.c (revision b4655da89eb65d1571b8afdfdbbb34449add2ef7) @@ -37,7 +37,9 @@ #include #include +#include #include #include -#include +#include +#include #include #include @@ -70,18 +72,17 @@ }; +/** Invalidate all unlocked ITLB and DTLB entries. */ +void tlb_invalidate_all(void) +{ + uint64_t errno = __hypercall_fast3(MMU_DEMAP_ALL, 0, 0, + MMU_FLAG_DTLB | MMU_FLAG_ITLB); + if (errno != EOK) { + panic("Error code = %d.\n", errno); + } +} + void tlb_arch_init(void) { - /* - * Invalidate all non-locked DTLB and ITLB entries. - */ - //MH - //tlb_invalidate_all(); - - /* - * Clear both SFSRs. - */ - //MH - //dtlb_sfsr_write(0); - //itlb_sfsr_write(0); + tlb_invalidate_all(); } @@ -97,4 +98,5 @@ bool locked, bool cacheable) { +#if 0 tlb_tag_access_reg_t tag; tlb_data_t data; @@ -124,4 +126,5 @@ dtlb_data_in_write(data.value); +#endif } @@ -135,4 +138,5 @@ void dtlb_pte_copy(pte_t *t, size_t index, bool ro) { +#if 0 tlb_tag_access_reg_t tag; tlb_data_t data; @@ -163,4 +167,5 @@ dtlb_data_in_write(data.value); +#endif } @@ -172,4 +177,5 @@ void itlb_pte_copy(pte_t *t, size_t index) { +#if 0 tlb_tag_access_reg_t tag; tlb_data_t data; @@ -197,4 +203,5 @@ itlb_data_in_write(data.value); +#endif } @@ -362,4 +369,5 @@ static void print_tlb_entry(int i, tlb_tag_read_reg_t t, tlb_data_t d) { +#if 0 printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, " "ie=%d, soft2=%#x, pfn=%#x, soft=%#x, l=%d, " @@ -367,4 +375,5 @@ t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g); +#endif } @@ -502,55 +511,4 @@ } -#if defined (US) -/** Invalidate all unlocked ITLB and DTLB entries. */ -void tlb_invalidate_all(void) -{ - int i; - - /* - * Walk all ITLB and DTLB entries and remove all unlocked mappings. - * - * The kernel doesn't use global mappings so any locked global mappings - * found must have been created by someone else. Their only purpose now - * is to collide with proper mappings. Invalidate immediately. It should - * be safe to invalidate them as late as now. - */ - - tlb_data_t d; - tlb_tag_read_reg_t t; - - for (i = 0; i < ITLB_ENTRY_COUNT; i++) { - d.value = itlb_data_access_read(i); - if (!d.l || d.g) { - t.value = itlb_tag_read_read(i); - d.v = false; - itlb_tag_access_write(t.value); - itlb_data_access_write(i, d.value); - } - } - - for (i = 0; i < DTLB_ENTRY_COUNT; i++) { - d.value = dtlb_data_access_read(i); - if (!d.l || d.g) { - t.value = dtlb_tag_read_read(i); - d.v = false; - dtlb_tag_access_write(t.value); - dtlb_data_access_write(i, d.value); - } - } - -} - -#elif defined (US3) - -/** Invalidate all unlocked ITLB and DTLB entries. */ -void tlb_invalidate_all(void) -{ - itlb_demap(TLB_DEMAP_ALL, 0, 0); - dtlb_demap(TLB_DEMAP_ALL, 0, 0); -} - -#endif - /** Invalidate all ITLB and DTLB entries that belong to specified ASID * (Context). Index: kernel/arch/sparc64/src/mm/tsb.c =================================================================== --- kernel/arch/sparc64/src/mm/tsb.c (revision 66e08d02d119283121b700c6a8f1a282651e2561) +++ (revision ) @@ -1,177 +1,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define TSB_INDEX_MASK ((1 << (21 + 1 + TSB_SIZE - MMU_PAGE_WIDTH)) - 1) - -/** Invalidate portion of TSB. - * - * We assume that the address space is already locked. Note that respective - * portions of both TSBs are invalidated at a time. - * - * @param as Address space. - * @param page First page to invalidate in TSB. - * @param pages Number of pages to invalidate. Value of (size_t) -1 means the - * whole TSB. - */ -void tsb_invalidate(as_t *as, uintptr_t page, size_t pages) -{ - size_t i0; - size_t i; - size_t cnt; - - ASSERT(as->arch.itsb && as->arch.dtsb); - - i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK; - ASSERT(i0 < ITSB_ENTRY_COUNT && i0 < DTSB_ENTRY_COUNT); - - if (pages == (size_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT) - cnt = ITSB_ENTRY_COUNT; - else - cnt = pages * 2; - - for (i = 0; i < cnt; i++) { - as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid = - true; - as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid = - true; - } -} - -/** Copy software PTE to ITSB. - * - * @param t Software PTE. - * @param index Zero if lower 8K-subpage, one if higher 8K subpage. - */ -void itsb_pte_copy(pte_t *t, size_t index) -{ - as_t *as; - tsb_entry_t *tsb; - size_t entry; - - ASSERT(index <= 1); - - as = t->as; - entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK; - ASSERT(entry < ITSB_ENTRY_COUNT); - tsb = &as->arch.itsb[entry]; - - /* - * We use write barriers to make sure that the TSB load - * won't use inconsistent data or that the fault will - * be repeated. - */ - - tsb->tag.invalid = true; /* invalidate the entry - * (tag target has this - * set to 0) */ - - write_barrier(); - - tsb->tag.context = as->asid; - /* the shift is bigger than PAGE_WIDTH, do not bother with index */ - tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT; - tsb->data.value = 0; - tsb->data.size = PAGESIZE_8K; - tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index; - tsb->data.cp = t->c; /* cp as cache in phys.-idxed, c as cacheable */ - tsb->data.p = t->k; /* p as privileged, k as kernel */ - tsb->data.v = t->p; /* v as valid, p as present */ - - write_barrier(); - - tsb->tag.invalid = false; /* mark the entry as valid */ -} - -/** Copy software PTE to DTSB. - * - * @param t Software PTE. - * @param index Zero if lower 8K-subpage, one if higher 8K-subpage. - * @param ro If true, the mapping is copied read-only. - */ -void dtsb_pte_copy(pte_t *t, size_t index, bool ro) -{ - as_t *as; - tsb_entry_t *tsb; - size_t entry; - - ASSERT(index <= 1); - - as = t->as; - entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK; - ASSERT(entry < DTSB_ENTRY_COUNT); - tsb = &as->arch.dtsb[entry]; - - /* - * We use write barriers to make sure that the TSB load - * won't use inconsistent data or that the fault will - * be repeated. - */ - - tsb->tag.invalid = true; /* invalidate the entry - * (tag target has this - * set to 0) */ - - write_barrier(); - - tsb->tag.context = as->asid; - /* the shift is bigger than PAGE_WIDTH, do not bother with index */ - tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT; - tsb->data.value = 0; - tsb->data.size = PAGESIZE_8K; - tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index; - tsb->data.cp = t->c; -#ifdef CONFIG_VIRT_IDX_DCACHE - tsb->data.cv = t->c; -#endif /* CONFIG_VIRT_IDX_DCACHE */ - tsb->data.p = t->k; /* p as privileged */ - tsb->data.w = ro ? false : t->w; - tsb->data.v = t->p; - - write_barrier(); - - tsb->tag.invalid = false; /* mark the entry as valid */ -} - -/** @} - */ - Index: kernel/arch/sparc64/src/sun4v/sparc64.c =================================================================== --- kernel/arch/sparc64/src/sun4v/sparc64.c (revision 66e08d02d119283121b700c6a8f1a282651e2561) +++ kernel/arch/sparc64/src/sun4v/sparc64.c (revision b4655da89eb65d1571b8afdfdbbb34449add2ef7) @@ -38,4 +38,5 @@ #include #include +#include #include #include @@ -68,4 +69,6 @@ bootinfo.taskmap.tasks[i].name); } + + md_init(); }