Index: kernel/arch/arm32/include/arch/mm/page.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/page.h	(revision e40b80662ddc08fed1ee4e0ac0dc40f4bea53eaa)
+++ kernel/arch/arm32/include/arch/mm/page.h	(revision b3f967c7d0fa49b20504658be82213be66b9dcfe)
@@ -41,4 +41,5 @@
 #include <arch/exception.h>
 #include <arch/barrier.h>
+#include <arch/cp15.h>
 #include <trace.h>
 
@@ -129,4 +130,7 @@
 	set_pt_level1_present((pte_t *) (ptl3), (size_t) (i))
 
+
+#define pt_coherence(page) pt_coherence_m(page, 1)
+
 #if defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_ARCH_armv7_a)
 #include "page_armv6.h"
@@ -137,4 +141,26 @@
 #endif
 
+/** Sets the address of level 0 page table.
+ *
+ * @param pt Pointer to the page table to set.
+ *
+ */
+NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
+{
+	TTBR0_write((uint32_t)pt);
+}
+
+NO_TRACE static inline void set_ptl1_addr(pte_t *pt, size_t i, uintptr_t address)
+{
+	pt[i].l0.coarse_table_addr = address >> 10;
+	pt_coherence(&pt[i].l0);
+}
+
+NO_TRACE static inline void set_ptl3_addr(pte_t *pt, size_t i, uintptr_t address)
+{
+	pt[i].l1.frame_base_addr = address >> 12;
+	pt_coherence(&pt[i].l1);
+}
+
 #endif
 
Index: kernel/arch/arm32/include/arch/mm/page_armv4.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/page_armv4.h	(revision e40b80662ddc08fed1ee4e0ac0dc40f4bea53eaa)
+++ kernel/arch/arm32/include/arch/mm/page_armv4.h	(revision b3f967c7d0fa49b20504658be82213be66b9dcfe)
@@ -41,6 +41,4 @@
 #error "Do not include arch specific page.h directly use generic page.h instead"
 #endif
-
-#include <arch/cp15.h>
 
 /* Macros for querying the last-level PTE entries. */
@@ -122,25 +120,5 @@
 #define PTE_DESCRIPTOR_SMALL_PAGE	2
 
-
-/** Sets the address of level 0 page table.
- *
- * @param pt Pointer to the page table to set.
- *
- */
-NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
-{
-	TTBR0_write((uint32_t)pt);
-}
-
-NO_TRACE static inline void set_ptl1_addr(pte_t *pt, size_t i, uintptr_t address)
-{
-	pt[i].l0.coarse_table_addr = address >> 10;
-}
-
-NO_TRACE static inline void set_ptl3_addr(pte_t *pt, size_t i, uintptr_t address)
-{
-	pt[i].l1.frame_base_addr = address >> 12;
-}
-
+#define pt_coherence_m(page, count)
 
 /** Returns level 0 page table entry flags.
Index: kernel/arch/arm32/include/arch/mm/page_armv6.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/page_armv6.h	(revision e40b80662ddc08fed1ee4e0ac0dc40f4bea53eaa)
+++ kernel/arch/arm32/include/arch/mm/page_armv6.h	(revision b3f967c7d0fa49b20504658be82213be66b9dcfe)
@@ -41,5 +41,4 @@
 #endif
 
-#include <arch/cp15.h>
 
 /* Macros for querying the last-level PTE entries. */
@@ -135,27 +134,4 @@
 	read_barrier(); \
 } while (0)
-#define pt_coherence(page) pt_coherence_m(page, 1)
-
-/** Sets the address of level 0 page table.
- *
- * @param pt Pointer to the page table to set.
- *
- */
-NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
-{
-	TTBR0_write((uint32_t)pt);
-}
-
-NO_TRACE static inline void set_ptl1_addr(pte_t *pt, size_t i, uintptr_t address)
-{
-	pt[i].l0.coarse_table_addr = address >> 10;
-	pt_coherence(&pt[i]);
-}
-
-NO_TRACE static inline void set_ptl3_addr(pte_t *pt, size_t i, uintptr_t address)
-{
-	pt[i].l1.frame_base_addr = address >> 12;
-	pt_coherence(&pt[i]);
-}