Changes in kernel/arch/mips32/src/mm/tlb.c [346b12a2:b2fa1204] in mainline
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kernel/arch/mips32/src/mm/tlb.c
r346b12a2 rb2fa1204 97 97 entry_lo_t lo; 98 98 uintptr_t badvaddr; 99 pte_t pte;99 pte_t *pte; 100 100 101 101 badvaddr = cp0_badvaddr_read(); 102 102 103 bool found = page_mapping_find(AS, badvaddr, true, &pte);104 if ( found && pte.p) {103 pte = page_mapping_find(AS, badvaddr, true); 104 if (pte && pte->p) { 105 105 /* 106 106 * Record access to PTE. 107 107 */ 108 pte.a = 1; 109 110 tlb_prepare_entry_lo(&lo, pte.g, pte.p, pte.d, 111 pte.cacheable, pte.pfn); 112 113 page_mapping_update(AS, badvaddr, true, &pte); 108 pte->a = 1; 109 110 tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, 111 pte->cacheable, pte->pfn); 114 112 115 113 /* … … 140 138 tlb_index_t index; 141 139 uintptr_t badvaddr; 142 pte_t pte;140 pte_t *pte; 143 141 144 142 /* … … 164 162 badvaddr = cp0_badvaddr_read(); 165 163 166 bool found = page_mapping_find(AS, badvaddr, true, &pte);167 if ( found && pte.p) {164 pte = page_mapping_find(AS, badvaddr, true); 165 if (pte && pte->p) { 168 166 /* 169 167 * Read the faulting TLB entry. … … 174 172 * Record access to PTE. 175 173 */ 176 pte.a = 1; 177 178 tlb_prepare_entry_lo(&lo, pte.g, pte.p, pte.d, 179 pte.cacheable, pte.pfn); 180 181 page_mapping_update(AS, badvaddr, true, &pte); 174 pte->a = 1; 175 176 tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, 177 pte->cacheable, pte->pfn); 182 178 183 179 /* … … 204 200 tlb_index_t index; 205 201 uintptr_t badvaddr; 206 pte_t pte;202 pte_t *pte; 207 203 208 204 badvaddr = cp0_badvaddr_read(); … … 228 224 } 229 225 230 bool found = page_mapping_find(AS, badvaddr, true, &pte);231 if ( found && pte.p && pte.w) {226 pte = page_mapping_find(AS, badvaddr, true); 227 if (pte && pte->p && pte->w) { 232 228 /* 233 229 * Read the faulting TLB entry. … … 238 234 * Record access and write to PTE. 239 235 */ 240 pte.a = 1; 241 pte.d = 1; 242 243 tlb_prepare_entry_lo(&lo, pte.g, pte.p, pte.w, 244 pte.cacheable, pte.pfn); 245 246 page_mapping_update(AS, badvaddr, true, &pte); 236 pte->a = 1; 237 pte->d = 1; 238 239 tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, 240 pte->cacheable, pte->pfn); 247 241 248 242 /*
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