Index: kernel/arch/sparc64/src/start.S
===================================================================
--- kernel/arch/sparc64/src/start.S	(revision b6e97d717db99cd0ea1752d7ad38b2d4d440fdd5)
+++ kernel/arch/sparc64/src/start.S	(revision b2e5e2505951aaa1c5f7f9f5c1ed146e2c5417c9)
@@ -330,8 +330,4 @@
  * used only for a very limited period of time, but we switch to it anyway,
  * just to be sure we are properly initialized.
- *
- * What is important is that this piece of memory is covered by the 4M DTLB
- * locked entry and therefore there will be no surprises like deadly
- * combinations of spill trap and and TLB miss on the stack address.
  */
 
Index: kernel/arch/sparc64/src/trap/trap_table.S
===================================================================
--- kernel/arch/sparc64/src/trap/trap_table.S	(revision b6e97d717db99cd0ea1752d7ad38b2d4d440fdd5)
+++ kernel/arch/sparc64/src/trap/trap_table.S	(revision b2e5e2505951aaa1c5f7f9f5c1ed146e2c5417c9)
@@ -630,8 +630,16 @@
  * handlers.
  *
- * This function can be entered either with interrupt globals or alternate globals.
- * Memory management trap handlers are obliged to switch to one of those global sets
- * prior to calling this function. Register window management functions are not
- * allowed to modify the alternate global registers.
+ * This function can be entered either with interrupt globals or alternate
+ * globals. Memory management trap handlers are obliged to switch to one of
+ * those global sets prior to calling this function. Register window management
+ * functions are not allowed to modify the alternate global registers.
+ *
+ * The kernel is designed to work on trap levels 0 - 4. For instance, the
+ * following can happen:
+ * TL0: kernel thread runs (CANSAVE=0, kernel stack not in DTLB)
+ * TL1: preemptible trap handler started after a tick interrupt
+ * TL2: preemptible trap handler did SAVE
+ * TL3: spill handler touched the kernel stack  
+ * TL4: hardware or software failure
  *
  * Input registers: