Index: arch/amd64/src/boot/boot.S
===================================================================
--- arch/amd64/src/boot/boot.S	(revision 2e5f7702dc81424f7b7355318fce5a2468b65a1d)
+++ arch/amd64/src/boot/boot.S	(revision b1cf98c8eda674680911446955a8d7273cd8f02e)
@@ -56,4 +56,5 @@
 	xorw %ax,%ax
 	movw %ax,%ds
+	movw %ax,%es
 	movw %ax,%ss            # initialize stack segment register
 	movl $(START_STACK), %esp	# initialize stack pointer
Index: arch/ia32/src/acpi/acpi.c
===================================================================
--- arch/ia32/src/acpi/acpi.c	(revision 2e5f7702dc81424f7b7355318fce5a2468b65a1d)
+++ arch/ia32/src/acpi/acpi.c	(revision b1cf98c8eda674680911446955a8d7273cd8f02e)
@@ -109,5 +109,5 @@
 
 rsdp_found:
-	printf("%L: ACPI Root System Description Pointer\n", acpi_rsdp);
+	printf("%P: ACPI Root System Description Pointer\n", acpi_rsdp);
 
 	acpi_rsdt = (struct acpi_rsdt *) (__native) acpi_rsdp->rsdt_address;
@@ -144,5 +144,5 @@
 					goto next;
 				*signature_map[j].sdt_ptr = h;
-				printf("%L: ACPI %s\n", *signature_map[j].sdt_ptr, signature_map[j].description);
+				printf("%P: ACPI %s\n", *signature_map[j].sdt_ptr, signature_map[j].description);
 			}
 		}
@@ -165,5 +165,5 @@
 					goto next;
 				*signature_map[j].sdt_ptr = h;
-				printf("%L: ACPI %s\n", *signature_map[j].sdt_ptr, signature_map[j].description);
+				printf("%P: ACPI %s\n", *signature_map[j].sdt_ptr, signature_map[j].description);
 			}
 		}
Index: arch/ia32/src/boot/boot.S
===================================================================
--- arch/ia32/src/boot/boot.S	(revision 2e5f7702dc81424f7b7355318fce5a2468b65a1d)
+++ arch/ia32/src/boot/boot.S	(revision b1cf98c8eda674680911446955a8d7273cd8f02e)
@@ -53,4 +53,5 @@
 	xorw %ax, %ax
 	movw %ax, %ds
+	movw %ax, %es
 	movw %ax, %ss							# initialize stack segment register
 	movl $BOOTSTRAP_OFFSET - 0x400, %esp				# initialize stack pointer
@@ -86,5 +87,5 @@
 	movw %ax, %ss
 	
-	movb $0xd1, %al							# enable A20 using the keyboard controller
+	movb $0xd1, %al							# enable A20 using i8042 controller
 	outb %al, $0x64
 	movb $0xdf, %al
Index: arch/ia32/src/boot/memmap.S
===================================================================
--- arch/ia32/src/boot/memmap.S	(revision 2e5f7702dc81424f7b7355318fce5a2468b65a1d)
+++ arch/ia32/src/boot/memmap.S	(revision b1cf98c8eda674680911446955a8d7273cd8f02e)
@@ -39,39 +39,36 @@
 
 memmap_arch_init:
-
 e820begin:
-	xorl	%ebx,%ebx	# during first call, ebx must be 0
-	movw	%bx,%ds
-	movw	%bx,%es
+	xorl	%ebx,%ebx			# during first call, ebx must be 0
 	movw	$e820table_boot,%di
 	movb	$MEMMAP_E820_MAX_RECORDS,e820counter_boot
 e820loop:	
-	movl	$E820_SMAP,%edx 	# control sequence "SMAP"
+	movl	$E820_SMAP,%edx 		# control sequence "SMAP"
 
-	movl	$0x0000e820,%eax	# service
+	movl	$0x0000e820,%eax		# service
 	movl	$MEMMAP_E820_RECORD_SIZE,%ecx
 	int 	$0x15
 	jc	e820err
 	
-	cmpl	$E820_SMAP,%eax		# verifying BIOS
+	cmpl	$E820_SMAP,%eax			# verifying BIOS
 	jne	e820err
 
 	cmpl	$MEMMAP_E820_RECORD_SIZE,%ecx
-	jne	e820err			# bad record size - bug in bios
+	jne	e820err				# bad record size - bug in bios
 	
-	movw	%di,%ax		# next record
+	movw	%di,%ax				# next record
 	addw	$MEMMAP_E820_RECORD_SIZE,%ax
 	movw	%ax,%di
 		
-	decb	e820counter_boot # buffer is full
+	decb	e820counter_boot 		# buffer is full
 	jz	e820end
 	
-	cmpl	$0,%ebx	
-	jne	e820loop
+	testl	%ebx,%ebx	
+	jnz	e820loop
 	
 e820end:
 	movb	$MEMMAP_E820_MAX_RECORDS,%al
 	subb	e820counter_boot,%al
-	movb	%al,e820counter_boot # store # of valid entries in e820counter
+	movb	%al,e820counter_boot 		# store # of valid entries in e820counter
 
 	jmp	e801begin
@@ -92,5 +89,5 @@
 	jc	e801end
 	
-			# fix problem with some BIOSes which use ax:bx rather than cx:dx
+	# fix problem with some BIOSes which use ax:bx rather than cx:dx
 	testw	%cx,%cx
 	jnz	e801cxdx
@@ -106,11 +103,13 @@
 	andl	$0xffff,%ecx
 	addl	%ecx,%edx
-	addl	$0x0400,%edx  # add lower 1 MB - it's not included by e801 method
+	addl	$0x0400,%edx  			# add lower 1 MB - it's not included by e801 method
 	movl	%edx,e801memorysize
 e801end:
 	ret
 
-	#memory size in 1 kb chunks
+
+.section K_DATA_START
+
+#memory size in 1 kb chunks
 e801memorysize:
 	.long	0
-
Index: arch/ia32/src/smp/mps.c
===================================================================
--- arch/ia32/src/smp/mps.c	(revision 2e5f7702dc81424f7b7355318fce5a2468b65a1d)
+++ arch/ia32/src/smp/mps.c	(revision b1cf98c8eda674680911446955a8d7273cd8f02e)
@@ -186,5 +186,5 @@
 	
 fs_found:
-	printf("%L: MPS Floating Pointer Structure\n", fs);
+	printf("%P: MPS Floating Pointer Structure\n", fs);
 
 	frame_not_free((__address) fs);
@@ -408,5 +408,5 @@
 		switch (cur[CT_EXT_ENTRY_TYPE]) {
 			default:
-				printf("%L: skipping MP Configuration Table extended entry type %d\n", cur, cur[CT_EXT_ENTRY_TYPE]);
+				printf("%P: skipping MP Configuration Table extended entry type %d\n", cur, cur[CT_EXT_ENTRY_TYPE]);
 				break;
 		}
Index: doc/arch/amd64
===================================================================
--- doc/arch/amd64	(revision 2e5f7702dc81424f7b7355318fce5a2468b65a1d)
+++ doc/arch/amd64	(revision b1cf98c8eda674680911446955a8d7273cd8f02e)
@@ -2,21 +2,25 @@
 ==========
 
-The fifth port, amd64 port, is heavily based on ia32 port.
-It was originally written by Ondrej Palkovsky.
-The goal is to support AMD64 or Intel Extended Memory PC's.
-The new 64-bit code makes use of portable parts of ia32.
+The fifth port, amd64 port, was originally written by Ondrej Palkovsky.
+The goal is to support AMD64 and Intel Extended Memory 64 Technology PC's.
+The port makes use of portable parts of ia32.
 Both uniprocessors and multiprocessors are supported.
-It has not been tested on real hardware, so far.
+The kernel runs on real hardware and in simulators too.
 
 HARDWARE REQUIREMENTS
-        o no real hardware supported
+        o AMD64 architecture processor
+	o Intel Extended Memory 64 Technology processor
+
+CPU
+	o Intel Xeon with Intel Extended Memory 64 Technology
 
 SMP COMPATIBILITY
         o Bochs 2.2.1
                 o 2x-8x AMD64 CPU
-        o Simics Simics 2.2.19
+        o Simics 2.2.19
                 o 2x-8x AMD hammer CPU
+	o HP ProLiant ML350 (HyperThreading)
 
 EMULATORS AND VIRTUALIZERS
-        o Bochs 2.2
-        o Simics Simics 2.2.19
+        o Bochs 2.2.1
+        o Simics 2.2.19
Index: doc/arch/ia32
===================================================================
--- doc/arch/ia32	(revision 2e5f7702dc81424f7b7355318fce5a2468b65a1d)
+++ doc/arch/ia32	(revision b1cf98c8eda674680911446955a8d7273cd8f02e)
@@ -6,5 +6,5 @@
 It is meant to support ordinary PC's based on IA-32 architecture.
 Both uniprocessor and multiprocessor modes are supported.
-It runs on both emulated environment and real hardware.
+It runs both in emulated environment and on real hardware.
 
 HARDWARE REQUIREMENTS
Index: doc/arch/mips32
===================================================================
--- doc/arch/mips32	(revision 2e5f7702dc81424f7b7355318fce5a2468b65a1d)
+++ doc/arch/mips32	(revision b1cf98c8eda674680911446955a8d7273cd8f02e)
@@ -11,4 +11,7 @@
         o emulated MIPS 4K CPU
 
+CPU
+	o QED R4600
+
 COMPILER REQUIREMENTS
         o mips binutils 2.16 and gcc 4.0.1 cross compiler