Changeset b187536 in mainline for uspace/srv/hw/netif/dp8390/dp8390.h
- Timestamp:
- 2011-01-06T19:10:01Z (14 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 39d70ec
- Parents:
- 37f0a29
- File:
-
- 1 edited
-
uspace/srv/hw/netif/dp8390/dp8390.h (modified) (7 diffs)
Legend:
- Unmodified
- Added
- Removed
-
uspace/srv/hw/netif/dp8390/dp8390.h
r37f0a29 rb187536 18 18 /* National Semiconductor DP8390 Network Interface Controller. */ 19 19 20 /* Page 0, for reading ------------- */ 21 #define DP_CR 0x0 /* Read side of Command Register */ 22 #define DP_CLDA0 0x1 /* Current Local Dma Address 0 */ 23 #define DP_CLDA1 0x2 /* Current Local Dma Address 1 */ 24 #define DP_BNRY 0x3 /* Boundary Pointer */ 25 #define DP_TSR 0x4 /* Transmit Status Register */ 26 #define DP_NCR 0x5 /* Number of Collisions Register */ 27 #define DP_FIFO 0x6 /* Fifo ?? */ 28 #define DP_ISR 0x7 /* Interrupt Status Register */ 29 #define DP_CRDA0 0x8 /* Current Remote Dma Address 0 */ 30 #define DP_CRDA1 0x9 /* Current Remote Dma Address 1 */ 31 #define DP_DUM1 0xA /* unused */ 32 #define DP_DUM2 0xB /* unused */ 33 #define DP_RSR 0xC /* Receive Status Register */ 34 #define DP_CNTR0 0xD /* Tally Counter 0 */ 35 #define DP_CNTR1 0xE /* Tally Counter 1 */ 36 #define DP_CNTR2 0xF /* Tally Counter 2 */ 37 38 /* Page 0, for writing ------------- */ 39 #define DP_CR 0x0 /* Write side of Command Register */ 40 #define DP_PSTART 0x1 /* Page Start Register */ 41 #define DP_PSTOP 0x2 /* Page Stop Register */ 42 #define DP_BNRY 0x3 /* Boundary Pointer */ 43 #define DP_TPSR 0x4 /* Transmit Page Start Register */ 44 #define DP_TBCR0 0x5 /* Transmit Byte Count Register 0 */ 45 #define DP_TBCR1 0x6 /* Transmit Byte Count Register 1 */ 46 #define DP_ISR 0x7 /* Interrupt Status Register */ 47 #define DP_RSAR0 0x8 /* Remote Start Address Register 0 */ 48 #define DP_RSAR1 0x9 /* Remote Start Address Register 1 */ 49 #define DP_RBCR0 0xA /* Remote Byte Count Register 0 */ 50 #define DP_RBCR1 0xB /* Remote Byte Count Register 1 */ 51 #define DP_RCR 0xC /* Receive Configuration Register */ 52 #define DP_TCR 0xD /* Transmit Configuration Register */ 53 #define DP_DCR 0xE /* Data Configuration Register */ 54 #define DP_IMR 0xF /* Interrupt Mask Register */ 55 56 /* Page 1, read/write -------------- */ 57 #define DP_CR 0x0 /* Command Register */ 20 /** Page 0, for reading */ 21 #define DP_CR 0x00 /**< Command Register */ 22 #define DP_CLDA0 0x01 /**< Current Local DMA Address 0 */ 23 #define DP_CLDA1 0x02 /**< Current Local DMA Address 1 */ 24 #define DP_BNRY 0x03 /**< Boundary Pointer */ 25 #define DP_TSR 0x04 /**< Transmit Status Register */ 26 #define DP_NCR 0x05 /**< Number of Collisions Register */ 27 #define DP_FIFO 0x06 /**< FIFO */ 28 #define DP_ISR 0x07 /**< Interrupt Status Register */ 29 #define DP_CRDA0 0x08 /**< Current Remote DMA Address 0 */ 30 #define DP_CRDA1 0x09 /**< Current Remote DMA Address 1 */ 31 #define DP_RSR 0x0c /**< Receive Status Register */ 32 #define DP_CNTR0 0x0d /**< Tally Counter 0 */ 33 #define DP_CNTR1 0x0e /**< Tally Counter 1 */ 34 #define DP_CNTR2 0x0f /**< Tally Counter 2 */ 35 36 /** Page 0, for writing */ 37 #define DP_PSTART 0x01 /**< Page Start Register*/ 38 #define DP_PSTOP 0x02 /**< Page Stop Register */ 39 #define DP_TPSR 0x04 /**< Transmit Page Start Register */ 40 #define DP_TBCR0 0x05 /**< Transmit Byte Count Register 0 */ 41 #define DP_TBCR1 0x06 /**< Transmit Byte Count Register 1 */ 42 #define DP_RSAR0 0x08 /**< Remote Start Address Register 0 */ 43 #define DP_RSAR1 0x09 /**< Remote Start Address Register 1 */ 44 #define DP_RBCR0 0x0a /**< Remote Byte Count Register 0 */ 45 #define DP_RBCR1 0x0b /**< Remote Byte Count Register 1 */ 46 #define DP_RCR 0x0c /**< Receive Configuration Register */ 47 #define DP_TCR 0x0d /**< Transmit Configuration Register */ 48 #define DP_DCR 0x0e /**< Data Configuration Register */ 49 #define DP_IMR 0x0f /**< Interrupt Mask Register */ 50 51 /** Page 1, read/write */ 58 52 #define DP_PAR0 0x1 /* Physical Address Register 0 */ 59 53 #define DP_PAR1 0x2 /* Physical Address Register 1 */ … … 184 178 #define DP_PAGESIZE 256 185 179 186 /** Read s1 byte from the zero page register.180 /** Read 1 byte from the zero page register. 187 181 * @param[in] dep The network interface structure. 188 182 * @param[in] reg The register offset. … … 191 185 #define inb_reg0(dep, reg) (inb(dep->de_dp8390_port + reg)) 192 186 193 /** Write s1 byte zero page register.187 /** Write 1 byte zero page register. 194 188 * @param[in] dep The network interface structure. 195 189 * @param[in] reg The register offset. … … 198 192 #define outb_reg0(dep, reg, data) (outb(dep->de_dp8390_port + reg, data)) 199 193 200 /** Read s1 byte from the first page register.194 /** Read 1 byte from the first page register. 201 195 * @param[in] dep The network interface structure. 202 196 * @param[in] reg The register offset. … … 205 199 #define inb_reg1(dep, reg) (inb(dep->de_dp8390_port + reg)) 206 200 207 /** Write s1 byte first page register.201 /** Write 1 byte first page register. 208 202 * @param[in] dep The network interface structure. 209 203 * @param[in] reg The register offset. … … 222 216 typedef void (*dp_getblock_t)(struct dpeth *dep, int page, size_t offset, size_t size, void *dst); 223 217 224 #define SENDQ_NR 1/* Maximum size of the send queue */218 #define SENDQ_NR 2 /* Maximum size of the send queue */ 225 219 #define SENDQ_PAGES 6 /* 6 * DP_PAGESIZE >= 1514 bytes */ 226 220 227 221 /** Maximum number of waiting packets to be sent or received. 228 222 */ 229 #define MAX_PACKETS 4223 #define MAX_PACKETS 1024 230 224 231 225 typedef struct dpeth { … … 291 285 } dpeth_t; 292 286 293 #define DEI_DEFAULT 0x8000294 295 287 #define DEF_EMPTY 0x000 296 288 #define DEF_PACK_SEND 0x001
Note:
See TracChangeset
for help on using the changeset viewer.
