Index: uspace/drv/uhci-hcd/hc.c
===================================================================
--- uspace/drv/uhci-hcd/hc.c	(revision 77d10f0e0c104e3c5426b9f3cf9c196940af3cb1)
+++ uspace/drv/uhci-hcd/hc.c	(revision af81980c9695b76a57ce275e167265faee365a68)
@@ -44,4 +44,7 @@
 #include "hc.h"
 
+#define UHCI_SUPPORTED_INTERRUPTS \
+    (UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET)
+
 static int hc_init_transfer_lists(hc_t *instance);
 static int hc_init_mem_structures(hc_t *instance);
@@ -135,5 +138,5 @@
 		/* Enable all interrupts, but resume interrupt */
 		pio_write_16(&instance->registers->usbintr,
-		    UHCI_INTR_CRC | UHCI_INTR_COMPLETE | UHCI_INTR_SHORT_PACKET);
+		    UHCI_SUPPORTED_INTERRUPTS);
 	}
 
@@ -170,4 +173,5 @@
 	instance->interrupt_code.cmds = instance->interrupt_commands;
 	{
+		/* Read status register */
 		instance->interrupt_commands[0].cmd = CMD_PIO_READ_16;
 		instance->interrupt_commands[0].dstarg = 1;
@@ -175,10 +179,25 @@
 		    &instance->registers->usbsts;
 
-		instance->interrupt_commands[1].cmd = CMD_PIO_WRITE_16;
-		instance->interrupt_commands[1].value = 0x1f;
-		instance->interrupt_commands[1].addr =
+		/* Test whether we are the interrupt cause */
+		instance->interrupt_commands[1].cmd = CMD_BTEST;
+		instance->interrupt_commands[1].value =
+		    UHCI_SUPPORTED_INTERRUPTS;
+		instance->interrupt_commands[1].srcarg = 1;
+		instance->interrupt_commands[1].dstarg = 2;
+
+		/* Predicate cleaning and accepting */
+		instance->interrupt_commands[2].cmd = CMD_PREDICATE;
+		instance->interrupt_commands[2].value = 2;
+		instance->interrupt_commands[2].srcarg = 2;
+
+		/* Write clean status register */
+		instance->interrupt_commands[3].cmd = CMD_PIO_WRITE_A_16;
+		instance->interrupt_commands[3].srcarg = 1;
+		instance->interrupt_commands[3].addr =
 		    &instance->registers->usbsts;
 
-		instance->interrupt_commands[2].cmd = CMD_ACCEPT;
+		/* Accept interrupt */
+		instance->interrupt_commands[4].cmd = CMD_ACCEPT;
+
 		instance->interrupt_code.cmdcount = UHCI_NEEDED_IRQ_COMMANDS;
 	}
Index: uspace/drv/uhci-hcd/hc.h
===================================================================
--- uspace/drv/uhci-hcd/hc.h	(revision 77d10f0e0c104e3c5426b9f3cf9c196940af3cb1)
+++ uspace/drv/uhci-hcd/hc.h	(revision af81980c9695b76a57ce275e167265faee365a68)
@@ -91,5 +91,5 @@
 #define UHCI_DEBUGER_TIMEOUT 5000000
 #define UHCI_ALLOWED_HW_FAIL 5
-#define UHCI_NEEDED_IRQ_COMMANDS 3
+#define UHCI_NEEDED_IRQ_COMMANDS 5
 
 /* Main HC driver structure */
Index: uspace/drv/uhci-hcd/pci.c
===================================================================
--- uspace/drv/uhci-hcd/pci.c	(revision 77d10f0e0c104e3c5426b9f3cf9c196940af3cb1)
+++ uspace/drv/uhci-hcd/pci.c	(revision af81980c9695b76a57ce275e167265faee365a68)
@@ -146,5 +146,5 @@
 	 * write all WC bits in USB legacy register */
 	sysarg_t address = 0xc0;
-	sysarg_t value = 0x8f00;
+	sysarg_t value = 0xaf00;
 
 	int rc = async_req_3_0(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),