Index: kernel/arch/xen32/Makefile.inc =================================================================== --- kernel/arch/xen32/Makefile.inc (revision 7b0599b7fa662f94a556da0427fe702bf0bc4676) +++ kernel/arch/xen32/Makefile.inc (revision aecf79fdaee472e18edbe8432718b356d591c455) @@ -77,10 +77,4 @@ DEFS += -DCONFIG_PAGE_PT -## Compile with i8042 controller support -# - -CONFIG_I8042 = y - - ## Accepted configuration directives # @@ -126,8 +120,5 @@ arch/$(ARCH)/src/mm/tlb.c \ arch/$(ARCH)/src/ddi/ddi.c \ - arch/$(ARCH)/src/drivers/i8254.c \ - arch/$(ARCH)/src/drivers/i8259.c \ - arch/$(ARCH)/src/drivers/ega.c \ - arch/$(ARCH)/src/drivers/vesa.c \ + arch/$(ARCH)/src/drivers/xconsole.c \ arch/$(ARCH)/src/boot/boot.S \ arch/$(ARCH)/src/fpu_context.c \ Index: kernel/arch/xen32/_link.ld.in =================================================================== --- kernel/arch/xen32/_link.ld.in (revision 7b0599b7fa662f94a556da0427fe702bf0bc4676) +++ kernel/arch/xen32/_link.ld.in (revision aecf79fdaee472e18edbe8432718b356d591c455) @@ -15,4 +15,5 @@ .image PA2KA(BOOT_OFFSET): { ktext_start = .; + *(K_TEXT_START); *(.text); ktext_end = .; Index: kernel/arch/xen32/include/asm.h =================================================================== --- kernel/arch/xen32/include/asm.h (revision 7b0599b7fa662f94a556da0427fe702bf0bc4676) +++ kernel/arch/xen32/include/asm.h (revision aecf79fdaee472e18edbe8432718b356d591c455) @@ -1,1 +1,300 @@ -../../ia32/include/asm.h +/* + * Copyright (C) 2001-2004 Jakub Jermar + * Copyright (C) 2005 Sergey Bondari + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup xen32 + * @{ + */ +/** @file + */ + +#ifndef __xen32_ASM_H__ +#define __xen32_ASM_H__ + +#include +#include +#include + +extern uint32_t interrupt_handler_size; + +extern void paging_on(void); + +extern void interrupt_handlers(void); + +extern void enable_l_apic_in_msr(void); + + +extern void asm_delay_loop(uint32_t t); +extern void asm_fake_loop(uint32_t t); + + +/** Halt CPU + * + * Halt the current CPU until interrupt event. + */ +static inline void cpu_halt(void) { __asm__("hlt\n"); }; +static inline void cpu_sleep(void) { __asm__("hlt\n"); }; + +#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ + { \ + unative_t res; \ + __asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \ + return res; \ + } + +#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ + { \ + __asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \ + } + +GEN_READ_REG(cr0); +GEN_READ_REG(cr2); +GEN_READ_REG(cr3); +GEN_WRITE_REG(cr3); + +GEN_READ_REG(dr0); +GEN_READ_REG(dr1); +GEN_READ_REG(dr2); +GEN_READ_REG(dr3); +GEN_READ_REG(dr6); +GEN_READ_REG(dr7); + +GEN_WRITE_REG(dr0); +GEN_WRITE_REG(dr1); +GEN_WRITE_REG(dr2); +GEN_WRITE_REG(dr3); +GEN_WRITE_REG(dr6); +GEN_WRITE_REG(dr7); + +/** Byte to port + * + * Output byte to port + * + * @param port Port to write to + * @param val Value to write + */ +static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } + +/** Word to port + * + * Output word to port + * + * @param port Port to write to + * @param val Value to write + */ +static inline void outw(uint16_t port, uint16_t val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); } + +/** Double word to port + * + * Output double word to port + * + * @param port Port to write to + * @param val Value to write + */ +static inline void outl(uint16_t port, uint32_t val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); } + +/** Byte from port + * + * Get byte from port + * + * @param port Port to read from + * @return Value read + */ +static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } + +/** Word from port + * + * Get word from port + * + * @param port Port to read from + * @return Value read + */ +static inline uint16_t inw(uint16_t port) { uint16_t val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; } + +/** Double word from port + * + * Get double word from port + * + * @param port Port to read from + * @return Value read + */ +static inline uint32_t inl(uint16_t port) { uint32_t val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; } + +/** Enable interrupts. + * + * Enable interrupts and return previous + * value of EFLAGS. + * + * @return Old interrupt priority level. + */ +static inline ipl_t interrupts_enable(void) +{ + ipl_t v; + __asm__ volatile ( + "pushf\n\t" + "popl %0\n\t" + "sti\n" + : "=r" (v) + ); + return v; +} + +/** Disable interrupts. + * + * Disable interrupts and return previous + * value of EFLAGS. + * + * @return Old interrupt priority level. + */ +static inline ipl_t interrupts_disable(void) +{ + ipl_t v; + __asm__ volatile ( + "pushf\n\t" + "popl %0\n\t" + "cli\n" + : "=r" (v) + ); + return v; +} + +/** Restore interrupt priority level. + * + * Restore EFLAGS. + * + * @param ipl Saved interrupt priority level. + */ +static inline void interrupts_restore(ipl_t ipl) +{ + __asm__ volatile ( + "pushl %0\n\t" + "popf\n" + : : "r" (ipl) + ); +} + +/** Return interrupt priority level. + * + * @return EFLAFS. + */ +static inline ipl_t interrupts_read(void) +{ + ipl_t v; + __asm__ volatile ( + "pushf\n\t" + "popl %0\n" + : "=r" (v) + ); + return v; +} + +/** Return base address of current stack + * + * Return the base address of the current stack. + * The stack is assumed to be STACK_SIZE bytes long. + * The stack must start on page boundary. + */ +static inline uintptr_t get_stack_base(void) +{ + uintptr_t v; + + __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1))); + + return v; +} + +static inline uint64_t rdtsc(void) +{ + uint64_t v; + + __asm__ volatile("rdtsc\n" : "=A" (v)); + + return v; +} + +/** Return current IP address */ +static inline uintptr_t * get_ip() +{ + uintptr_t *ip; + + __asm__ volatile ( + "mov %%eip, %0" + : "=r" (ip) + ); + return ip; +} + +/** Invalidate TLB Entry. + * + * @param addr Address on a page whose TLB entry is to be invalidated. + */ +static inline void invlpg(uintptr_t addr) +{ + __asm__ volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr)); +} + +/** Load GDTR register from memory. + * + * @param gdtr_reg Address of memory from where to load GDTR. + */ +static inline void gdtr_load(ptr_16_32_t *gdtr_reg) +{ + __asm__ volatile ("lgdtl %0\n" : : "m" (*gdtr_reg)); +} + +/** Store GDTR register to memory. + * + * @param gdtr_reg Address of memory to where to load GDTR. + */ +static inline void gdtr_store(ptr_16_32_t *gdtr_reg) +{ + __asm__ volatile ("sgdtl %0\n" : : "m" (*gdtr_reg)); +} + +/** Load IDTR register from memory. + * + * @param idtr_reg Address of memory from where to load IDTR. + */ +static inline void idtr_load(ptr_16_32_t *idtr_reg) +{ + __asm__ volatile ("lidtl %0\n" : : "m" (*idtr_reg)); +} + +/** Load TR from descriptor table. + * + * @param sel Selector specifying descriptor of TSS segment. + */ +static inline void tr_load(uint16_t sel) +{ + __asm__ volatile ("ltr %0" : : "r" (sel)); +} + +#endif + +/** @} + */ Index: kernel/arch/xen32/include/drivers/xconsole.h =================================================================== --- kernel/arch/xen32/include/drivers/xconsole.h (revision aecf79fdaee472e18edbe8432718b356d591c455) +++ kernel/arch/xen32/include/drivers/xconsole.h (revision aecf79fdaee472e18edbe8432718b356d591c455) @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2006 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup xen32 + * @{ + */ +/** @file + */ + +#ifndef __XCONSOLE_H__ +#define __XCONSOLE_H__ + +extern void xen_console_init(void); + +#endif + +/** @} + */ Index: kernel/arch/xen32/include/hypercall.h =================================================================== --- kernel/arch/xen32/include/hypercall.h (revision 7b0599b7fa662f94a556da0427fe702bf0bc4676) +++ kernel/arch/xen32/include/hypercall.h (revision aecf79fdaee472e18edbe8432718b356d591c455) @@ -31,4 +31,16 @@ #include +#include + + +#define XEN_CONSOLE_IO 18 + + +/* + * Commands for XEN_CONSOLE_IO + */ +#define CONSOLE_IO_WRITE 0 +#define CONSOLE_IO_READ 1 + #define hypercall0(id) \ @@ -83,5 +95,5 @@ : "1" (p1), \ "2" (p2), \ - "3" (p3), \ + "3" (p3) \ : "memory" \ ); \ @@ -102,5 +114,5 @@ "2" (p2), \ "3" (p3), \ - "4" (p4), \ + "4" (p4) \ : "memory" \ ); \ @@ -110,5 +122,5 @@ #define hypercall5(id, p1, p2, p3, p4, p5) \ ({ \ - unative_t ret, __ign1, __ign2, __ign3, __ign4, __ing5; \ + unative_t ret, __ign1, __ign2, __ign3, __ign4, __ign5; \ asm volatile ( \ "call hypercall_page + (" STRING(id) " * 32)\n" \ @@ -123,5 +135,5 @@ "3" (p3), \ "4" (p4), \ - "5" (p5), \ + "5" (p5) \ : "memory" \ ); \ @@ -130,5 +142,5 @@ -static inline int xen_console_io(int cmd, int count, char *str) +static inline int xen_console_io(const int cmd, const int count, const char *str) { return hypercall3(XEN_CONSOLE_IO, cmd, count, str); Index: kernel/arch/xen32/include/pm.h =================================================================== --- kernel/arch/xen32/include/pm.h (revision 7b0599b7fa662f94a556da0427fe702bf0bc4676) +++ kernel/arch/xen32/include/pm.h (revision aecf79fdaee472e18edbe8432718b356d591c455) @@ -1,1 +1,170 @@ -../../ia32/include/pm.h +/* + * Copyright (C) 2001-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup xen32 + * @{ + */ +/** @file + */ + +#ifndef __PM_H__ +#define __PM_H__ + +#define IDT_ITEMS 64 +#define GDT_ITEMS 7 + +#define NULL_DES 0 +#define KTEXT_DES 1 +#define KDATA_DES 2 +#define UTEXT_DES 3 +#define UDATA_DES 4 +#define TSS_DES 5 +#define TLS_DES 6 /* Pointer to Thread-Local-Storage data */ + +#define selector(des) ((des) << 3) + +#define PL_KERNEL 1 +#define PL_USER 3 + +#define AR_PRESENT (1<<7) +#define AR_DATA (2<<3) +#define AR_CODE (3<<3) +#define AR_WRITABLE (1<<1) +#define AR_INTERRUPT (0xe) +#define AR_TSS (0x9) + +#define DPL_KERNEL (PL_KERNEL<<5) +#define DPL_USER (PL_USER<<5) + +#define TSS_BASIC_SIZE 104 +#define TSS_IOMAP_SIZE (16*1024+1) /* 16K for bitmap + 1 terminating byte for convenience */ + +#define IO_PORTS (64*1024) + +#ifndef __ASM__ + +#include +#include +#include + +struct ptr_16_32 { + uint16_t limit; + uint32_t base; +} __attribute__ ((packed)); +typedef struct ptr_16_32 ptr_16_32_t; + +struct descriptor { + unsigned limit_0_15: 16; + unsigned base_0_15: 16; + unsigned base_16_23: 8; + unsigned access: 8; + unsigned limit_16_19: 4; + unsigned available: 1; + unsigned unused: 1; + unsigned special: 1; + unsigned granularity : 1; + unsigned base_24_31: 8; +} __attribute__ ((packed)); +typedef struct descriptor descriptor_t; + +struct idescriptor { + unsigned offset_0_15: 16; + unsigned selector: 16; + unsigned unused: 8; + unsigned access: 8; + unsigned offset_16_31: 16; +} __attribute__ ((packed)); +typedef struct idescriptor idescriptor_t; + +struct tss { + uint16_t link; + unsigned : 16; + uint32_t esp0; + uint16_t ss0; + unsigned : 16; + uint32_t esp1; + uint16_t ss1; + unsigned : 16; + uint32_t esp2; + uint16_t ss2; + unsigned : 16; + uint32_t cr3; + uint32_t eip; + uint32_t eflags; + uint32_t eax; + uint32_t ecx; + uint32_t edx; + uint32_t ebx; + uint32_t esp; + uint32_t ebp; + uint32_t esi; + uint32_t edi; + uint16_t es; + unsigned : 16; + uint16_t cs; + unsigned : 16; + uint16_t ss; + unsigned : 16; + uint16_t ds; + unsigned : 16; + uint16_t fs; + unsigned : 16; + uint16_t gs; + unsigned : 16; + uint16_t ldtr; + unsigned : 16; + unsigned : 16; + uint16_t iomap_base; + uint8_t iomap[TSS_IOMAP_SIZE]; +} __attribute__ ((packed)); +typedef struct tss tss_t; + +extern ptr_16_32_t gdtr; +extern ptr_16_32_t bootstrap_gdtr; +extern ptr_16_32_t protected_ap_gdtr; +extern struct tss *tss_p; + +extern descriptor_t gdt[]; + +extern void pm_init(void); + +extern void gdt_setbase(descriptor_t *d, uintptr_t base); +extern void gdt_setlimit(descriptor_t *d, uint32_t limit); + +extern void idt_init(void); +extern void idt_setoffset(idescriptor_t *d, uintptr_t offset); + +extern void tss_initialize(tss_t *t); +extern void set_tls_desc(uintptr_t tls); + +#endif /* __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/xen32/src/boot/boot.S =================================================================== --- kernel/arch/xen32/src/boot/boot.S (revision 7b0599b7fa662f94a556da0427fe702bf0bc4676) +++ kernel/arch/xen32/src/boot/boot.S (revision aecf79fdaee472e18edbe8432718b356d591c455) @@ -35,5 +35,5 @@ .ascii "GUEST_OS=HelenOS," .ascii "XEN_VER=xen-3.0," - .ascii "HYPERCALL_PAGE=0x0002," + .ascii "HYPERCALL_PAGE=0x0000," .ascii "LOADER=generic," .ascii "PT_MODE_WRITABLE" @@ -61,7 +61,7 @@ hlt +.section K_TEXT_START, "aw", @progbits .global hypercall_page - -.org (0x0002 * PAGE_SIZE) +.org 0 hypercall_page: .space PAGE_SIZE Index: kernel/arch/xen32/src/drivers/xconsole.c =================================================================== --- kernel/arch/xen32/src/drivers/xconsole.c (revision aecf79fdaee472e18edbe8432718b356d591c455) +++ kernel/arch/xen32/src/drivers/xconsole.c (revision aecf79fdaee472e18edbe8432718b356d591c455) @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2006 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup xen32 + * @{ + */ +/** + * @file + * @brief Xen32 console driver. + */ + +#include +#include +#include +#include +#include + +static void xen_putchar(chardev_t *d, const char ch); + +chardev_t xen_console; +static chardev_operations_t xen_ops = { + .write = xen_putchar +}; + +void xen_console_init(void) +{ + chardev_initialize("xen_out", &xen_console, &xen_ops); + stdout = &xen_console; +} + +void xen_putchar(chardev_t *d, const char ch) +{ + xen_console_io(CONSOLE_IO_WRITE, 1, &ch); +} + +/** @} + */ Index: kernel/arch/xen32/src/interrupt.c =================================================================== --- kernel/arch/xen32/src/interrupt.c (revision 7b0599b7fa662f94a556da0427fe702bf0bc4676) +++ kernel/arch/xen32/src/interrupt.c (revision aecf79fdaee472e18edbe8432718b356d591c455) @@ -1,1 +1,209 @@ -../../ia32/src/interrupt.c +/* + * Copyright (C) 2006 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup xen32interrupt + * @{ + */ +/** @file + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Interrupt and exception dispatching. + */ + +void (* disable_irqs_function)(uint16_t irqmask) = NULL; +void (* enable_irqs_function)(uint16_t irqmask) = NULL; +void (* eoi_function)(void) = NULL; + +void PRINT_INFO_ERRCODE(istate_t *istate) +{ + char *symbol = get_symtab_entry(istate->eip); + + if (!symbol) + symbol = ""; + + if (CPU) + printf("----------------EXCEPTION OCCURED (cpu%d)----------------\n", CPU->id); + else + printf("----------------EXCEPTION OCCURED----------------\n"); + + printf("%%eip: %#x (%s)\n",istate->eip,symbol); + printf("ERROR_WORD=%#x\n", istate->error_word); + printf("%%cs=%#x,flags=%#x\n", istate->cs, istate->eflags); + printf("%%eax=%#x, %%ecx=%#x, %%edx=%#x, %%esp=%#x\n", istate->eax,istate->ecx,istate->edx,&istate->stack[0]); +#ifdef CONFIG_DEBUG_ALLREGS + printf("%%esi=%#x, %%edi=%#x, %%ebp=%#x, %%ebx=%#x\n", istate->esi,istate->edi,istate->ebp,istate->ebx); +#endif + printf("stack: %#x, %#x, %#x, %#x\n", istate->stack[0], istate->stack[1], istate->stack[2], istate->stack[3]); + printf(" %#x, %#x, %#x, %#x\n", istate->stack[4], istate->stack[5], istate->stack[6], istate->stack[7]); +} + +void null_interrupt(int n, istate_t *istate) +{ + fault_if_from_uspace(istate, "unserviced interrupt: %d", n); + + PRINT_INFO_ERRCODE(istate); + panic("unserviced interrupt: %d\n", n); +} + +/** General Protection Fault. */ +void gp_fault(int n, istate_t *istate) +{ + if (TASK) { + count_t ver; + + spinlock_lock(&TASK->lock); + ver = TASK->arch.iomapver; + spinlock_unlock(&TASK->lock); + + if (CPU->arch.iomapver_copy != ver) { + /* + * This fault can be caused by an early access + * to I/O port because of an out-dated + * I/O Permission bitmap installed on CPU. + * Install the fresh copy and restart + * the instruction. + */ + io_perm_bitmap_install(); + return; + } + fault_if_from_uspace(istate, "general protection fault"); + } + + PRINT_INFO_ERRCODE(istate); + panic("general protection fault\n"); +} + +void ss_fault(int n, istate_t *istate) +{ + fault_if_from_uspace(istate, "stack fault"); + + PRINT_INFO_ERRCODE(istate); + panic("stack fault\n"); +} + +void simd_fp_exception(int n, istate_t *istate) +{ + uint32_t mxcsr; + asm + ( + "stmxcsr %0;\n" + :"=m"(mxcsr) + ); + fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR: %#zx", + (unative_t)mxcsr); + + PRINT_INFO_ERRCODE(istate); + printf("MXCSR: %#zx\n",(unative_t)(mxcsr)); + panic("SIMD FP exception(19)\n"); +} + +void nm_fault(int n, istate_t *istate) +{ +#ifdef CONFIG_FPU_LAZY + scheduler_fpu_lazy_request(); +#else + fault_if_from_uspace(istate, "fpu fault"); + panic("fpu fault"); +#endif +} + +void syscall(int n, istate_t *istate) +{ + panic("Obsolete syscall handler."); +} + +void tlb_shootdown_ipi(int n, istate_t *istate) +{ + trap_virtual_eoi(); + tlb_shootdown_ipi_recv(); +} + +void trap_virtual_enable_irqs(uint16_t irqmask) +{ + if (enable_irqs_function) + enable_irqs_function(irqmask); + else + panic("no enable_irqs_function\n"); +} + +void trap_virtual_disable_irqs(uint16_t irqmask) +{ + if (disable_irqs_function) + disable_irqs_function(irqmask); + else + panic("no disable_irqs_function\n"); +} + +void trap_virtual_eoi(void) +{ + if (eoi_function) + eoi_function(); + else + panic("no eoi_function\n"); + +} + +static void ipc_int(int n, istate_t *istate) +{ + ipc_irq_send_notif(n-IVT_IRQBASE); + trap_virtual_eoi(); +} + + +/* Reregister irq to be IPC-ready */ +void irq_ipc_bind_arch(unative_t irq) +{ + if (irq == IRQ_CLK) + return; + exc_register(IVT_IRQBASE+irq, "ipc_int", ipc_int); + trap_virtual_enable_irqs(1 << irq); +} + +/** @} + */ + Index: kernel/arch/xen32/src/mm/frame.c =================================================================== --- kernel/arch/xen32/src/mm/frame.c (revision 7b0599b7fa662f94a556da0427fe702bf0bc4676) +++ kernel/arch/xen32/src/mm/frame.c (revision aecf79fdaee472e18edbe8432718b356d591c455) @@ -52,19 +52,10 @@ void frame_arch_init(void) { - static pfn_t minconf; - if (config.cpu_active == 1) { - minconf = 1; -#ifdef CONFIG_SIMICS_FIX - minconf = max(minconf, ADDR2PFN(0x10000)); -#endif - - /* Reserve frame 0 (BIOS data) */ - frame_mark_unavailable(0, 1); + pfn_t start = ADDR2PFN(ALIGN_UP(KA2PA(start_info.pt_base), PAGE_SIZE)) + start_info.nr_pt_frames; + size_t size = start_info.nr_pages - start; -#ifdef CONFIG_SIMICS_FIX - /* Don't know why, but these addresses help */ - frame_mark_unavailable(0xd000 >> FRAME_WIDTH,3); -#endif + zone_create(start, size, start, 0); + last_frame = start + size; } } Index: kernel/arch/xen32/src/mm/page.c =================================================================== --- kernel/arch/xen32/src/mm/page.c (revision 7b0599b7fa662f94a556da0427fe702bf0bc4676) +++ kernel/arch/xen32/src/mm/page.c (revision aecf79fdaee472e18edbe8432718b356d591c455) @@ -78,42 +78,26 @@ } - -uintptr_t hw_map(uintptr_t physaddr, size_t size) -{ - if (last_frame + ALIGN_UP(size, PAGE_SIZE) > KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH)) - panic("Unable to map physical memory %p (%d bytes)", physaddr, size) - - uintptr_t virtaddr = PA2KA(last_frame); - pfn_t i; - for (i = 0; i < ADDR2PFN(ALIGN_UP(size, PAGE_SIZE)); i++) - page_mapping_insert(AS_KERNEL, virtaddr + PFN2ADDR(i), physaddr + PFN2ADDR(i), PAGE_NOT_CACHEABLE); - - last_frame = ALIGN_UP(last_frame + size, FRAME_SIZE); - - return virtaddr; -} - void page_fault(int n, istate_t *istate) { - uintptr_t page; + uintptr_t page; pf_access_t access; - page = read_cr2(); - - if (istate->error_word & PFERR_CODE_RSVD) + page = read_cr2(); + + if (istate->error_word & PFERR_CODE_RSVD) panic("Reserved bit set in page directory.\n"); - + if (istate->error_word & PFERR_CODE_RW) access = PF_ACCESS_WRITE; else access = PF_ACCESS_READ; - - if (as_page_fault(page, access, istate) == AS_PF_FAULT) { + + if (as_page_fault(page, access, istate) == AS_PF_FAULT) { fault_if_from_uspace(istate, "Page fault: %#x", page); - - PRINT_INFO_ERRCODE(istate); - printf("page fault address: %#x\n", page); - panic("page fault\n"); - } + + PRINT_INFO_ERRCODE(istate); + printf("page fault address: %#x\n", page); + panic("page fault\n"); + } } Index: kernel/arch/xen32/src/pm.c =================================================================== --- kernel/arch/xen32/src/pm.c (revision 7b0599b7fa662f94a556da0427fe702bf0bc4676) +++ kernel/arch/xen32/src/pm.c (revision aecf79fdaee472e18edbe8432718b356d591c455) @@ -74,8 +74,4 @@ /* TLS descriptor */ { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 }, - /* VESA Init descriptor */ -#ifdef CONFIG_FB - { 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 } -#endif }; @@ -153,12 +149,12 @@ static void clean_IOPL_NT_flags(void) { - __asm__ volatile ( - "pushfl\n" - "pop %%eax\n" - "and $0xffff8fff, %%eax\n" - "push %%eax\n" - "popfl\n" - : : : "eax" - ); +// __asm__ volatile ( +// "pushfl\n" +// "pop %%eax\n" +// "and $0xffff8fff, %%eax\n" +// "push %%eax\n" +// "popfl\n" +// : : : "eax" +// ); } @@ -166,10 +162,10 @@ static void clean_AM_flag(void) { - __asm__ volatile ( - "mov %%cr0, %%eax\n" - "and $0xfffbffff, %%eax\n" - "mov %%eax, %%cr0\n" - : : : "eax" - ); +// __asm__ volatile ( +// "mov %%cr0, %%eax\n" +// "and $0xfffbffff, %%eax\n" +// "mov %%eax, %%cr0\n" +// : : : "eax" +// ); } @@ -184,6 +180,6 @@ idtr.limit = sizeof(idt); idtr.base = (uintptr_t) idt; - gdtr_load(&gdtr); - idtr_load(&idtr); +// gdtr_load(&gdtr); +// idtr_load(&idtr); /* @@ -192,19 +188,19 @@ */ - if (config.cpu_active == 1) { - idt_init(); - /* - * NOTE: bootstrap CPU has statically allocated TSS, because - * the heap hasn't been initialized so far. - */ +// if (config.cpu_active == 1) { +// idt_init(); +// /* +// * NOTE: bootstrap CPU has statically allocated TSS, because +// * the heap hasn't been initialized so far. +// */ tss_p = &tss; - } - else { - tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC); - if (!tss_p) - panic("could not allocate TSS\n"); - } - - tss_initialize(tss_p); +// } +// else { +// tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC); +// if (!tss_p) +// panic("could not allocate TSS\n"); +// } + +// tss_initialize(tss_p); gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL; @@ -219,5 +215,5 @@ * to its own TSS. We just need to load the TR register. */ - tr_load(selector(TSS_DES)); +// tr_load(selector(TSS_DES)); clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels and clear NT flag. */ Index: kernel/arch/xen32/src/smp/smp.c =================================================================== --- kernel/arch/xen32/src/smp/smp.c (revision 7b0599b7fa662f94a556da0427fe702bf0bc4676) +++ kernel/arch/xen32/src/smp/smp.c (revision aecf79fdaee472e18edbe8432718b356d591c455) @@ -54,5 +54,4 @@ #include #include -#include #ifdef CONFIG_SMP @@ -119,5 +118,5 @@ outb(0x71,0xa); - pic_disable_irqs(0xffff); +// pic_disable_irqs(0xffff); apic_init(); Index: kernel/arch/xen32/src/xen32.c =================================================================== --- kernel/arch/xen32/src/xen32.c (revision 7b0599b7fa662f94a556da0427fe702bf0bc4676) +++ kernel/arch/xen32/src/xen32.c (revision aecf79fdaee472e18edbe8432718b356d591c455) @@ -40,9 +40,5 @@ #include -#include -#include -#include -#include -#include +#include #include @@ -68,10 +64,8 @@ void arch_pre_mm_init(void) { -// pm_init(); + pm_init(); if (config.cpu_active == 1) { // bios_init(); -// i8259_init(); /* PIC */ -// i8254_init(); /* hard clock */ // exc_register(VECTOR_SYSCALL, "syscall", (iroutine) syscall); @@ -87,13 +81,6 @@ { if (config.cpu_active == 1) { - -#ifdef CONFIG_FB - if (vesa_present()) - vesa_init(); - else -#endif - ega_init(); /* video */ - - + /* video */ + xen_console_init(); /* Enable debugger */ debugger_init(); @@ -116,10 +103,9 @@ void arch_post_smp_init(void) { - i8042_init(); /* keyboard controller */ } void calibrate_delay_loop(void) { - i8254_calibrate_delay_loop(); +// i8254_calibrate_delay_loop(); if (config.cpu_active == 1) { /* @@ -127,5 +113,5 @@ * On SMP, i8254 is not used for time keeping and its interrupt pin remains masked. */ - i8254_normal_operation(); +// i8254_normal_operation(); } } @@ -149,6 +135,6 @@ void arch_grab_console(void) { - i8042_grab(); } + /** Return console to userspace * @@ -156,5 +142,4 @@ void arch_release_console(void) { - i8042_release(); } Index: kernel/kernel.config =================================================================== --- kernel/kernel.config (revision 7b0599b7fa662f94a556da0427fe702bf0bc4676) +++ kernel/kernel.config (revision aecf79fdaee472e18edbe8432718b356d591c455) @@ -38,5 +38,5 @@ # Framebuffer support -! [(ARCH=mips32&MACHINE=lgxemul)|(ARCH=mips32&MACHINE=bgxemul)|(ARCH=ia32)|(ARCH=amd64)|(ARCH=xen32)] CONFIG_FB (y/n) +! [(ARCH=mips32&MACHINE=lgxemul)|(ARCH=mips32&MACHINE=bgxemul)|(ARCH=ia32)|(ARCH=amd64)] CONFIG_FB (y/n) # Framebuffer width @@ -50,5 +50,5 @@ @ "1600" @ "2048" -! [(ARCH=ia32|ARCH=amd64|ARCH=xen32)&CONFIG_FB=y] CONFIG_VESA_WIDTH (choice) +! [(ARCH=ia32|ARCH=amd64)&CONFIG_FB=y] CONFIG_VESA_WIDTH (choice) # Framebuffer height @@ -63,5 +63,5 @@ @ "1200" @ "1536" -! [(ARCH=ia32|ARCH=amd64|ARCH=xen32)&CONFIG_FB=y] CONFIG_VESA_HEIGHT (choice) +! [(ARCH=ia32|ARCH=amd64)&CONFIG_FB=y] CONFIG_VESA_HEIGHT (choice) # Framebuffer depth @@ -69,5 +69,5 @@ @ "16" @ "24" -! [(ARCH=ia32|ARCH=amd64|ARCH=xen32)&CONFIG_FB=y] CONFIG_VESA_BPP (choice) +! [(ARCH=ia32|ARCH=amd64)&CONFIG_FB=y] CONFIG_VESA_BPP (choice) # Support for SMP @@ -116,6 +116,6 @@ @ "synch/semaphore1" Semaphore test 1 @ "synch/semaphore2" Sempahore test 2 -@ [ARCH=ia32|ARCH=amd64|ARCH=ia64|ARCH=xen32] "fpu/fpu1" Intel fpu test 1 -@ [ARCH=ia32|ARCH=amd64|ARCH=xen32] "fpu/sse1" Intel Sse test 1 +@ [ARCH=ia32|ARCH=amd64|ARCH=ia64|ARCH=xen32] "fpu/fpu1" Intel FPU test 1 +@ [ARCH=ia32|ARCH=amd64|ARCH=xen32] "fpu/sse1" Intel SSE test 1 @ [ARCH=mips32&MACHINE!=msim&MACHINE!=simics] "fpu/mips1" MIPS FPU test 1 @ "print/print1" Printf test 1