Index: uspace/drv/audio/hdaudio/hdactl.c
===================================================================
--- uspace/drv/audio/hdaudio/hdactl.c	(revision 3fafe5e03bb501f8627b315f8e97330dd3996f86)
+++ uspace/drv/audio/hdaudio/hdactl.c	(revision ae7d03c05f24b857bbbdbcf3dafbf8ecc6c286ab)
@@ -516,7 +516,7 @@
 	    hda_reg16_read(&hda->regs->statests));
 	/**
-	  * Clear STATESTS bits so they don't generate an interrupt later
-	  * when we enable interrupts.
-	  */
+	 * Clear STATESTS bits so they don't generate an interrupt later
+	 * when we enable interrupts.
+	 */
 	hda_reg16_write(&hda->regs->statests, 0x7f);
 
Index: uspace/drv/block/ahci/ahci_hw.h
===================================================================
--- uspace/drv/block/ahci/ahci_hw.h	(revision 3fafe5e03bb501f8627b315f8e97330dd3996f86)
+++ uspace/drv/block/ahci/ahci_hw.h	(revision ae7d03c05f24b857bbbdbcf3dafbf8ecc6c286ab)
@@ -216,16 +216,16 @@
 typedef union {
 	struct {
-	/** Indicates the completion status of BIST
-	 * non-zero value indicates a failure.
-	 */
-	unsigned int cc : 4;
-	/** Reserved. */
-	unsigned int reserved : 2;
-	/** Software sets this bit to 1 to invoke BIST,
-	 * the HBA clears this bit to 0 when BIST is complete.
-	 */
-	unsigned int sb : 1;
-	/** BIST capable. */
-	unsigned int bc : 1;
+		/** Indicates the completion status of BIST
+		 * non-zero value indicates a failure.
+		 */
+		unsigned int cc : 4;
+		/** Reserved. */
+		unsigned int reserved : 2;
+		/** Software sets this bit to 1 to invoke BIST,
+		 * the HBA clears this bit to 0 when BIST is complete.
+		 */
+		unsigned int sb : 1;
+		/** BIST capable. */
+		unsigned int bc : 1;
 	};
 	uint8_t u8;
@@ -252,6 +252,5 @@
 
 /** AHCI PCI register Subsystem Identifiers. */
-typedef struct
-{
+typedef struct {
 	/** Sub system vendor identifier. */
 	uint8_t ssvid;
@@ -261,6 +260,5 @@
 
 /** AHCI PCI registers Expansion ROM Base Address. */
-typedef struct
-{
+typedef struct {
 	/** Indicates the base address of the HBA expansion ROM. */
 	uint32_t u32;
@@ -268,6 +266,5 @@
 
 /** AHCI PCI register Capabilities Pointer. */
-typedef struct
-{
+typedef struct {
 	/** Indicates the first capability pointer offset. */
 	uint8_t u8;
@@ -275,6 +272,5 @@
 
 /** AHCI PCI register Interrupt Information. */
-typedef struct
-{
+typedef struct {
 	/* Software written value to indicate which interrupt vector
 	 * the interrupt is connected to.
@@ -286,6 +282,5 @@
 
 /** AHCI PCI register Min Grant (Optional). */
-typedef struct
-{
+typedef struct {
 	/** Indicates the minimum grant time that the device
 	 * wishes grant asserted.
@@ -295,6 +290,5 @@
 
 /** AHCI PCI register Max Latency (Optional). */
-typedef struct
-{
+typedef struct {
 	/** Indicates the maximum latency that the device can withstand. */
 	uint8_t u8;
@@ -431,6 +425,5 @@
 
 /** AHCI Memory register Command completion coalescing ports. */
-typedef struct
-{
+typedef struct {
 	/** If a bit is set to 1, the corresponding port is
 	 * part of the command completion coalescing feature.
@@ -440,6 +433,5 @@
 
 /** AHCI Memory register Enclosure management location. */
-typedef struct
-{
+typedef struct {
 	/** Size of the transmit message buffer area in dwords. */
 	uint16_t sz;
@@ -525,6 +517,5 @@
 
 /** AHCI Memory register Generic Host Control. */
-typedef struct
-{
+typedef struct {
 	/** Host Capabilities */
 	uint32_t cap;
@@ -942,6 +933,5 @@
 
 /** AHCI Memory register Port. */
-typedef volatile struct
-{
+typedef volatile struct {
 	/** Port x Command List Base Address. */
 	uint32_t pxclb;
@@ -1010,5 +1000,5 @@
 	/** Physical Region Descriptor Byte Count. */
 	uint32_t bytesprocessed;
-	 /** Command Table Descriptor Base Address. */
+	/** Command Table Descriptor Base Address. */
 	uint32_t cmdtable;
 	/** Command Table Descriptor Base Address Upper 32-bits. */
Index: uspace/drv/block/ddisk/ddisk.c
===================================================================
--- uspace/drv/block/ddisk/ddisk.c	(revision 3fafe5e03bb501f8627b315f8e97330dd3996f86)
+++ uspace/drv/block/ddisk/ddisk.c	(revision ae7d03c05f24b857bbbdbcf3dafbf8ecc6c286ab)
@@ -495,6 +495,6 @@
 
 	/*
- 	 * Register IRQ handler.
- 	 */
+	 * Register IRQ handler.
+	 */
 	ddisk_regs_t *res_phys = (ddisk_regs_t *) res.base;
 	ddisk_irq_pio_ranges[0].base = res.base;
Index: uspace/drv/bus/pci/pciintel/pci.c
===================================================================
--- uspace/drv/bus/pci/pciintel/pci.c	(revision 3fafe5e03bb501f8627b315f8e97330dd3996f86)
+++ uspace/drv/bus/pci/pciintel/pci.c	(revision ae7d03c05f24b857bbbdbcf3dafbf8ecc6c286ab)
@@ -267,5 +267,5 @@
 		 * architectures do not support shorter PIO reads offset from
 		 * this register.
-	 	 */
+		 */
 		val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
 	} else {
@@ -301,11 +301,11 @@
 	 * Some architectures do not support shorter PIO writes offset from this
 	 * register.
- 	 */
+	 */
 
 	if (len < 4) {
 		/*
- 		 * We have fewer than full 32-bits, so we need to read the
- 		 * missing bits first.
- 		 */
+		 * We have fewer than full 32-bits, so we need to read the
+		 * missing bits first.
+		 */
 		if (bus->conf_addr_reg) {
 			pio_write_32(bus->conf_addr_reg,
@@ -534,6 +534,6 @@
 
 	/*
- 	 * Unimplemented BARs read back as all 0's.
- 	 */
+	 * Unimplemented BARs read back as all 0's.
+	 */
 	if (!bar)
 		return addr + (addrw64 ? 8 : 4);
Index: uspace/drv/bus/usb/xhci/hw_struct/trb.h
===================================================================
--- uspace/drv/bus/usb/xhci/hw_struct/trb.h	(revision 3fafe5e03bb501f8627b315f8e97330dd3996f86)
+++ uspace/drv/bus/usb/xhci/hw_struct/trb.h	(revision ae7d03c05f24b857bbbdbcf3dafbf8ecc6c286ab)
@@ -80,5 +80,5 @@
 	/*
 	 * Reserved: 24-31
-	*/
+	 */
 
 	/*
Index: uspace/drv/nic/ar9271/ar9271.c
===================================================================
--- uspace/drv/nic/ar9271/ar9271.c	(revision 3fafe5e03bb501f8627b315f8e97330dd3996f86)
+++ uspace/drv/nic/ar9271/ar9271.c	(revision ae7d03c05f24b857bbbdbcf3dafbf8ecc6c286ab)
@@ -801,5 +801,5 @@
 	 * This should initiate creating confirmation message in
 	 * device side buffer which we will check in htc_check_ready function.
-	*/
+	 */
 	usb_pipe_t *ctrl_pipe = usb_device_get_default_pipe(usb_device);
 	errno_t rc = usb_control_request_set(ctrl_pipe,
Index: uspace/drv/nic/rtl8139/driver.c
===================================================================
--- uspace/drv/nic/rtl8139/driver.c	(revision 3fafe5e03bb501f8627b315f8e97330dd3996f86)
+++ uspace/drv/nic/rtl8139/driver.c	(revision ae7d03c05f24b857bbbdbcf3dafbf8ecc6c286ab)
@@ -94,5 +94,5 @@
 
 #ifndef RXBUF_SIZE_FLAGS
-	/** Flags for receiver buffer - 16kB default */
+/** Flags for receiver buffer - 16kB default */
 #define RXBUF_SIZE_FLAGS RTL8139_RXFLAGS_SIZE_16
 #endif
Index: uspace/drv/nic/rtl8169/driver.c
===================================================================
--- uspace/drv/nic/rtl8169/driver.c	(revision 3fafe5e03bb501f8627b315f8e97330dd3996f86)
+++ uspace/drv/nic/rtl8169/driver.c	(revision ae7d03c05f24b857bbbdbcf3dafbf8ecc6c286ab)
@@ -1205,5 +1205,5 @@
 
 /** Main function of RTL8169 driver
-*
+ *
  *  Just initialize the driver structures and
  *  put it into the device drivers interface
Index: uspace/drv/platform/malta/malta.c
===================================================================
--- uspace/drv/platform/malta/malta.c	(revision 3fafe5e03bb501f8627b315f8e97330dd3996f86)
+++ uspace/drv/platform/malta/malta.c	(revision ae7d03c05f24b857bbbdbcf3dafbf8ecc6c286ab)
@@ -233,8 +233,8 @@
 
 	/*
- 	 * We need to disable byte swapping of the outgoing and incoming
- 	 * PCI data, because the PCI driver assumes no byte swapping behind
- 	 * the scenes and takes care of it itself.
- 	 */
+	 * We need to disable byte swapping of the outgoing and incoming
+	 * PCI data, because the PCI driver assumes no byte swapping behind
+	 * the scenes and takes care of it itself.
+	 */
 	ret = pio_enable((void *) GT_BASE, GT_SIZE, (void **) &gt);
 	if (ret != EOK)