Index: uspace/drv/bus/pci/pciintel/pci.c
===================================================================
--- uspace/drv/bus/pci/pciintel/pci.c	(revision 3fafe5e03bb501f8627b315f8e97330dd3996f86)
+++ uspace/drv/bus/pci/pciintel/pci.c	(revision ae7d03c05f24b857bbbdbcf3dafbf8ecc6c286ab)
@@ -267,5 +267,5 @@
 		 * architectures do not support shorter PIO reads offset from
 		 * this register.
-	 	 */
+		 */
 		val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
 	} else {
@@ -301,11 +301,11 @@
 	 * Some architectures do not support shorter PIO writes offset from this
 	 * register.
- 	 */
+	 */
 
 	if (len < 4) {
 		/*
- 		 * We have fewer than full 32-bits, so we need to read the
- 		 * missing bits first.
- 		 */
+		 * We have fewer than full 32-bits, so we need to read the
+		 * missing bits first.
+		 */
 		if (bus->conf_addr_reg) {
 			pio_write_32(bus->conf_addr_reg,
@@ -534,6 +534,6 @@
 
 	/*
- 	 * Unimplemented BARs read back as all 0's.
- 	 */
+	 * Unimplemented BARs read back as all 0's.
+	 */
 	if (!bar)
 		return addr + (addrw64 ? 8 : 4);
Index: uspace/drv/bus/usb/xhci/hw_struct/trb.h
===================================================================
--- uspace/drv/bus/usb/xhci/hw_struct/trb.h	(revision 3fafe5e03bb501f8627b315f8e97330dd3996f86)
+++ uspace/drv/bus/usb/xhci/hw_struct/trb.h	(revision ae7d03c05f24b857bbbdbcf3dafbf8ecc6c286ab)
@@ -80,5 +80,5 @@
 	/*
 	 * Reserved: 24-31
-	*/
+	 */
 
 	/*