Index: kernel/arch/amd64/src/userspace.c =================================================================== --- kernel/arch/amd64/src/userspace.c (revision b277bef17cacdcab109f936194b7f7b6e0d05213) +++ kernel/arch/amd64/src/userspace.c (revision ae7d03c05f24b857bbbdbcf3dafbf8ecc6c286ab) @@ -55,26 +55,27 @@ asm volatile ( - "pushq %[udata_des]\n" - "pushq %[stack_top]\n" - "pushq %[rflags]\n" - "pushq %[utext_des]\n" - "pushq %[entry]\n" - "movq %[uarg], %%rax\n" + "pushq %[udata_des]\n" + "pushq %[stack_top]\n" + "pushq %[rflags]\n" + "pushq %[utext_des]\n" + "pushq %[entry]\n" + "movq %[uarg], %%rax\n" - /* %rdi is defined to hold pcb_ptr - set it to 0 */ - "xorq %%rdi, %%rdi\n" - "iretq\n" - :: [udata_des] "i" (GDT_SELECTOR(UDATA_DES) | PL_USER), - [stack_top] "r" ((uint8_t *) kernel_uarg->uspace_stack + - kernel_uarg->uspace_stack_size), - [rflags] "r" (rflags), - [utext_des] "i" (GDT_SELECTOR(UTEXT_DES) | PL_USER), - [entry] "r" (kernel_uarg->uspace_entry), - [uarg] "r" (kernel_uarg->uspace_uarg) - : "rax" + /* %rdi is defined to hold pcb_ptr - set it to 0 */ + "xorq %%rdi, %%rdi\n" + "iretq\n" + :: [udata_des] "i" (GDT_SELECTOR(UDATA_DES) | PL_USER), + [stack_top] "r" ((uint8_t *) kernel_uarg->uspace_stack + + kernel_uarg->uspace_stack_size), + [rflags] "r" (rflags), + [utext_des] "i" (GDT_SELECTOR(UTEXT_DES) | PL_USER), + [entry] "r" (kernel_uarg->uspace_entry), + [uarg] "r" (kernel_uarg->uspace_uarg) + : "rax" ); /* Unreachable */ - while (true); + while (true) + ; } Index: kernel/arch/arm32/src/cpu/cpu.c =================================================================== --- kernel/arch/arm32/src/cpu/cpu.c (revision b277bef17cacdcab109f936194b7f7b6e0d05213) +++ kernel/arch/arm32/src/cpu/cpu.c (revision ae7d03c05f24b857bbbdbcf3dafbf8ecc6c286ab) @@ -169,10 +169,10 @@ #endif #ifdef PROCESSOR_ARCH_armv7_a - /* ICache coherency is elaborated on in barrier.h. - * VIPT and PIPT caches need maintenance only on code modify, - * so it should be safe for general use. - * Enable branch predictors too as they follow the same rules - * as ICache and they can be flushed together - */ + /* ICache coherency is elaborated on in barrier.h. + * VIPT and PIPT caches need maintenance only on code modify, + * so it should be safe for general use. + * Enable branch predictors too as they follow the same rules + * as ICache and they can be flushed together + */ if ((CTR_read() & CTR_L1I_POLICY_MASK) != CTR_L1I_POLICY_AIVIVT) { control_reg |= Index: kernel/arch/arm32/src/exception.c =================================================================== --- kernel/arch/arm32/src/exception.c (revision b277bef17cacdcab109f936194b7f7b6e0d05213) +++ kernel/arch/arm32/src/exception.c (revision ae7d03c05f24b857bbbdbcf3dafbf8ecc6c286ab) @@ -68,5 +68,5 @@ /* relative address (related to exc. vector) of the word * where handler's address is stored - */ + */ volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET; Index: kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c =================================================================== --- kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c (revision b277bef17cacdcab109f936194b7f7b6e0d05213) +++ kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c (revision ae7d03c05f24b857bbbdbcf3dafbf8ecc6c286ab) @@ -88,8 +88,8 @@ amdm37x_gpt_irq_ack(&beagleboard.timer); - /* - * We are holding a lock which prevents preemption. - * Release the lock, call clock() and reacquire the lock again. - */ + /* + * We are holding a lock which prevents preemption. + * Release the lock, call clock() and reacquire the lock again. + */ spinlock_unlock(&irq->lock); clock(); Index: kernel/arch/arm32/src/mach/integratorcp/integratorcp.c =================================================================== --- kernel/arch/arm32/src/mach/integratorcp/integratorcp.c (revision b277bef17cacdcab109f936194b7f7b6e0d05213) +++ kernel/arch/arm32/src/mach/integratorcp/integratorcp.c (revision ae7d03c05f24b857bbbdbcf3dafbf8ecc6c286ab) @@ -193,7 +193,7 @@ { /* - * We are holding a lock which prevents preemption. - * Release the lock, call clock() and reacquire the lock again. - */ + * We are holding a lock which prevents preemption. + * Release the lock, call clock() and reacquire the lock again. + */ spinlock_unlock(&irq->lock); Index: kernel/arch/ia32/src/userspace.c =================================================================== --- kernel/arch/ia32/src/userspace.c (revision b277bef17cacdcab109f936194b7f7b6e0d05213) +++ kernel/arch/ia32/src/userspace.c (revision ae7d03c05f24b857bbbdbcf3dafbf8ecc6c286ab) @@ -53,32 +53,33 @@ asm volatile ( - /* Set up GS register (virtual register segment) */ - "movl %[vreg_des], %%gs\n" + /* Set up GS register (virtual register segment) */ + "movl %[vreg_des], %%gs\n" - "pushl %[udata_des]\n" - "pushl %[stack_top]\n" - "pushl %[eflags]\n" - "pushl %[utext_des]\n" - "pushl %[entry]\n" - "movl %[uarg], %%eax\n" + "pushl %[udata_des]\n" + "pushl %[stack_top]\n" + "pushl %[eflags]\n" + "pushl %[utext_des]\n" + "pushl %[entry]\n" + "movl %[uarg], %%eax\n" - /* %edi is defined to hold pcb_ptr - set it to 0 */ - "xorl %%edi, %%edi\n" + /* %edi is defined to hold pcb_ptr - set it to 0 */ + "xorl %%edi, %%edi\n" - "iret\n" - : - : [eflags_mask] "i" (~EFLAGS_NT), - [udata_des] "i" (GDT_SELECTOR(UDATA_DES) | PL_USER), - [stack_top] "r" ((uint8_t *) kernel_uarg->uspace_stack + - kernel_uarg->uspace_stack_size), - [eflags] "r" ((eflags & ~(EFLAGS_NT)) | EFLAGS_IF), - [utext_des] "i" (GDT_SELECTOR(UTEXT_DES) | PL_USER), - [entry] "r" (kernel_uarg->uspace_entry), - [uarg] "r" (kernel_uarg->uspace_uarg), - [vreg_des] "r" (GDT_SELECTOR(VREG_DES)) - : "eax"); + "iret\n" + : + : [eflags_mask] "i" (~EFLAGS_NT), + [udata_des] "i" (GDT_SELECTOR(UDATA_DES) | PL_USER), + [stack_top] "r" ((uint8_t *) kernel_uarg->uspace_stack + + kernel_uarg->uspace_stack_size), + [eflags] "r" ((eflags & ~(EFLAGS_NT)) | EFLAGS_IF), + [utext_des] "i" (GDT_SELECTOR(UTEXT_DES) | PL_USER), + [entry] "r" (kernel_uarg->uspace_entry), + [uarg] "r" (kernel_uarg->uspace_uarg), + [vreg_des] "r" (GDT_SELECTOR(VREG_DES)) + : "eax"); /* Unreachable */ - while (true); + while (true) + ; } Index: kernel/arch/ia64/include/arch/mm/vhpt.h =================================================================== --- kernel/arch/ia64/include/arch/mm/vhpt.h (revision b277bef17cacdcab109f936194b7f7b6e0d05213) +++ kernel/arch/ia64/include/arch/mm/vhpt.h (revision ae7d03c05f24b857bbbdbcf3dafbf8ecc6c286ab) @@ -31,5 +31,5 @@ */ /** @file -*/ + */ #ifndef KERN_ia64_VHPT_H_ Index: kernel/arch/ia64/src/mm/vhpt.c =================================================================== --- kernel/arch/ia64/src/mm/vhpt.c (revision b277bef17cacdcab109f936194b7f7b6e0d05213) +++ kernel/arch/ia64/src/mm/vhpt.c (revision ae7d03c05f24b857bbbdbcf3dafbf8ecc6c286ab) @@ -1,28 +1,28 @@ /* -* Copyright (c) 2006 Jakub Vana -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* - The name of the author may not be used to endorse or promote products -* derived from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * Copyright (c) 2006 Jakub Vana + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -31,5 +31,5 @@ */ /** @file -*/ + */ #include