Index: boot/arch/arm32/src/mm.c
===================================================================
--- boot/arch/arm32/src/mm.c	(revision 3bacee1839e6f355100ab4ea86bb211e9ecf19ed)
+++ boot/arch/arm32/src/mm.c	(revision ae7d03c05f24b857bbbdbcf3dafbf8ecc6c286ab)
@@ -103,5 +103,5 @@
  *
  * @return	1 if the given section can be mapped as cacheable, 0 otherwise.
-*/
+ */
 static inline int section_cacheable(pfn_t section)
 {
@@ -203,17 +203,17 @@
 	 */
 	asm volatile (
-		/* Behave as a client of domains */
+	    /* Behave as a client of domains */
 	    "ldr r0, =0x55555555\n"
 	    "mcr p15, 0, r0, c3, c0, 0\n"
 
-		/* Current settings */
+	    /* Current settings */
 	    "mrc p15, 0, r0, c1, c0, 0\n"
 
-		/* Enable ICache, DCache, BPredictors and MMU,
-		 * we disable caches before jumping to kernel
-		 * so this is safe for all archs.
-		 * Enable VMSAv6 the bit (23) is only writable on ARMv6.
-		 * (and QEMU)
-		 */
+	    /* Enable ICache, DCache, BPredictors and MMU,
+	     * we disable caches before jumping to kernel
+	     * so this is safe for all archs.
+	     * Enable VMSAv6 the bit (23) is only writable on ARMv6.
+	     * (and QEMU)
+	     */
 #ifdef PROCESSOR_ARCH_armv6
 	    "ldr r1, =0x00801805\n"
@@ -224,10 +224,10 @@
 	    "orr r0, r0, r1\n"
 
-		/* Invalidate the TLB content before turning on the MMU.
-		 * ARMv7-A Reference manual, B3.10.3
-		 */
+	    /* Invalidate the TLB content before turning on the MMU.
+	     * ARMv7-A Reference manual, B3.10.3
+	     */
 	    "mcr p15, 0, r0, c8, c7, 0\n"
 
-		/* Store settings, enable the MMU */
+	    /* Store settings, enable the MMU */
 	    "mcr p15, 0, r0, c1, c0, 0\n"
 	    ::: "r0", "r1"