Changeset ae3a941 in mainline for uspace/drv/bus/usb/xhci


Ignore:
Timestamp:
2018-02-26T16:51:40Z (8 years ago)
Author:
Ondřej Hlavatý <aearsis@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
e773f58
Parents:
3692678
Message:

usb: cstyle

Location:
uspace/drv/bus/usb/xhci
Files:
14 edited

Legend:

Unmodified
Added
Removed
  • uspace/drv/bus/usb/xhci/bus.h

    r3692678 rae3a941  
    4545/** Endpoint management structure */
    4646typedef struct xhci_bus {
    47         bus_t base;             /**< Inheritance. Keep this first. */
    48 
    49         xhci_hc_t *hc;                          /**< Pointer to managing HC (to issue commands) */
    50 
    51         xhci_device_t **devices_by_slot;        /**< Devices by Slot ID */
     47        bus_t base; /**< Inheritance. Keep this first. */
     48        xhci_hc_t *hc; /**< Pointer to managing HC (to issue commands) */
     49        xhci_device_t **devices_by_slot; /**< Devices by Slot ID */
    5250} xhci_bus_t;
    5351
  • uspace/drv/bus/usb/xhci/commands.c

    r3692678 rae3a941  
    150150
    151151        while (cmd_link != NULL) {
    152                 xhci_cmd_t *cmd = list_get_instance(cmd_link, xhci_cmd_t, _header.link);
     152                xhci_cmd_t *cmd = list_get_instance(cmd_link, xhci_cmd_t,
     153                    _header.link);
    153154
    154155                if (cmd->_header.trb_phys == phys)
     
    158159        }
    159160
    160         return cmd_link ? list_get_instance(cmd_link, xhci_cmd_t, _header.link)
    161                 : NULL;
     161        return cmd_link
     162            ? list_get_instance(cmd_link, xhci_cmd_t, _header.link)
     163            : NULL;
    162164}
    163165
     
    167169
    168170        cr->state = state;
    169         if (state == XHCI_CR_STATE_OPEN
    170             || state == XHCI_CR_STATE_CLOSED)
     171        if (state == XHCI_CR_STATE_OPEN || state == XHCI_CR_STATE_CLOSED)
    171172                fibril_condvar_broadcast(&cr->state_cv);
    172173}
     
    206207        }
    207208
    208         usb_log_debug("Sending command %s", xhci_trb_str_type(TRB_TYPE(cmd->_header.trb)));
     209        usb_log_debug("Sending command %s",
     210            xhci_trb_str_type(TRB_TYPE(cmd->_header.trb)));
    209211
    210212        list_append(&cmd->_header.link, &cr->cmd_list);
     
    337339                usb_log_error("Command resulted in error: %s.", trb_codes[code]);
    338340        else
    339                 usb_log_error("Command resulted in reserved or vendor specific error.");
     341                usb_log_error("Command resulted in reserved or "
     342                    "vendor specific error.");
    340343}
    341344
     
    657660        }
    658661
    659         usb_log_error("Timeout while waiting for command: aborting current command.");
     662        usb_log_error("Timeout while waiting for command: "
     663            "aborting current command.");
    660664
    661665        cr_set_state(cr, XHCI_CR_STATE_CHANGING);
     
    663667        abort_command_ring(hc);
    664668
    665         fibril_condvar_wait_timeout(&cr->stopped_cv, &cr->guard, XHCI_CR_ABORT_TIMEOUT);
     669        fibril_condvar_wait_timeout(&cr->stopped_cv, &cr->guard,
     670            XHCI_CR_ABORT_TIMEOUT);
    666671
    667672        if (XHCI_REG_RD(hc->op_regs, XHCI_OP_CRR)) {
  • uspace/drv/bus/usb/xhci/commands.h

    r3692678 rae3a941  
    7070
    7171typedef enum {
    72         XHCI_CR_STATE_CLOSED,           /**< Commands are rejected with ENAK. */
    73         XHCI_CR_STATE_OPEN,             /**< Commands are enqueued normally. */
    74         XHCI_CR_STATE_CHANGING,         /**< Commands wait until state changes. */
    75         XHCI_CR_STATE_FULL,             /**< Commands wait until something completes. */
     72        XHCI_CR_STATE_CLOSED,   /**< Commands are rejected with ENAK. */
     73        XHCI_CR_STATE_OPEN,     /**< Commands are enqueued normally. */
     74        XHCI_CR_STATE_CHANGING, /**< Commands wait until state changes. */
     75        XHCI_CR_STATE_FULL,     /**< Commands wait until something completes. */
    7676} xhci_cr_state_t;
    7777
  • uspace/drv/bus/usb/xhci/debug.h

    r3692678 rae3a941  
    6363extern void xhci_dump_slot_ctx(const struct xhci_slot_ctx *);
    6464extern void xhci_dump_endpoint_ctx(const struct xhci_endpoint_ctx *);
    65 extern void xhci_dump_input_ctx(const struct xhci_hc *, const struct xhci_input_ctx *);
     65extern void xhci_dump_input_ctx(const struct xhci_hc *,
     66    const struct xhci_input_ctx *);
    6667
    6768#endif
  • uspace/drv/bus/usb/xhci/device.h

    r3692678 rae3a941  
    6262
    6363#define XHCI_DEV_FMT  "(%s, slot %d)"
    64 #define XHCI_DEV_ARGS(dev)               ddf_fun_get_name((dev).base.fun), (dev).slot_id
     64#define XHCI_DEV_ARGS(dev)      ddf_fun_get_name((dev).base.fun), (dev).slot_id
    6565
    6666/* Bus callbacks */
     
    7272void xhci_setup_slot_context(xhci_device_t *, xhci_slot_ctx_t *);
    7373
    74 static inline xhci_device_t * xhci_device_get(device_t *dev)
     74static inline xhci_device_t *xhci_device_get(device_t *dev)
    7575{
    7676        assert(dev);
  • uspace/drv/bus/usb/xhci/endpoint.h

    r3692678 rae3a941  
    7676        xhci_trb_ring_t ring;
    7777
    78         /** Primary stream context data array (or NULL if endpoint doesn't use streams). */
     78        /**
     79         * Primary stream context data array
     80         * (or NULL if endpoint doesn't use streams).
     81         */
    7982        xhci_stream_data_t *primary_stream_data_array;
    8083
     
    8386        dma_buffer_t primary_stream_ctx_dma;
    8487
    85         /** Size of the allocated primary stream data array (and context array). */
     88        /** Size of the allocated primary stream data and context array. */
    8689        uint16_t primary_stream_data_size;
    8790
     
    8992        uint32_t max_streams;
    9093
    91         /** Maximum number of consecutive USB transactions (0-15) that should be executed per scheduling opportunity */
     94        /**
     95         * Maximum number of consecutive USB transactions (0-15) that
     96         * should be executed per scheduling opportunity
     97         */
    9298        uint8_t max_burst;
    9399
    94         /** Maximum number of bursts within an interval that this endpoint supports */
     100        /**
     101         * Maximum number of bursts within an interval that
     102         * this endpoint supports
     103         */
    95104        uint8_t mult;
    96105
    97         /** Scheduling interval for periodic endpoints, as a number of 125us units. (0 - 2^16) */
     106        /**
     107         * Scheduling interval for periodic endpoints,
     108         * as a number of 125us units. (0 - 2^16)
     109         */
    98110        uint32_t interval;
    99111
    100         /** This field is a valid pointer for (and only for) isochronous transfers. */
     112        /**
     113         * This field is a valid pointer for (and only for) isochronous
     114         * endpoints.
     115         */
    101116        xhci_isoch_t isoch [0];
    102117} xhci_endpoint_t;
     
    111126extern int xhci_endpoint_type(xhci_endpoint_t *ep);
    112127
    113 extern endpoint_t *xhci_endpoint_create(device_t *, const usb_endpoint_descriptors_t *);
     128extern endpoint_t *xhci_endpoint_create(device_t *,
     129    const usb_endpoint_descriptors_t *);
    114130extern errno_t xhci_endpoint_register(endpoint_t *);
    115131extern void xhci_endpoint_unregister(endpoint_t *);
     
    122138extern errno_t xhci_endpoint_clear_halt(xhci_endpoint_t *, unsigned);
    123139
    124 static inline xhci_endpoint_t * xhci_endpoint_get(endpoint_t *ep)
     140static inline xhci_endpoint_t *xhci_endpoint_get(endpoint_t *ep)
    125141{
    126142        assert(ep);
     
    128144}
    129145
    130 static inline xhci_device_t * xhci_ep_to_dev(xhci_endpoint_t *ep)
     146static inline xhci_device_t *xhci_ep_to_dev(xhci_endpoint_t *ep)
    131147{
    132148        assert(ep);
  • uspace/drv/bus/usb/xhci/hc.h

    r3692678 rae3a941  
    9595        bool ac64;
    9696        bool csz;
    97         uint64_t wrap_time;             /** The last time when mfindex wrap happened */
    98         uint64_t wrap_count;    /** Amount of mfindex wraps HC has done */
    99         unsigned ist;                   /**< IST in microframes */
     97        uint64_t wrap_time;     /**< The last time when mfindex wrap happened */
     98        uint64_t wrap_count;    /**< Amount of mfindex wraps HC has done */
     99        unsigned ist;           /**< IST in microframes */
    100100
    101101        /** Port speed mapping */
  • uspace/drv/bus/usb/xhci/hw_struct/context.h

    r3692678 rae3a941  
    179179#define XHCI_CTX_SIZE_SMALL 32
    180180#define XHCI_ONE_CTX_SIZE(hc) (XHCI_CTX_SIZE_SMALL << hc->csz)
    181 #define XHCI_GET_CTX_FIELD(type, ctx, hc, ci) (xhci_##type##_ctx_to_charptr(ctx) + (ci) * XHCI_ONE_CTX_SIZE(hc))
     181#define XHCI_GET_CTX_FIELD(type, ctx, hc, ci) \
     182    (xhci_##type##_ctx_to_charptr(ctx) + (ci) * XHCI_ONE_CTX_SIZE(hc))
    182183
    183184/**
     
    185186 */
    186187#define XHCI_DEVICE_CTX_SIZE(hc) ((1 + XHCI_EP_COUNT) * XHCI_ONE_CTX_SIZE(hc))
    187 #define XHCI_GET_EP_CTX(dev_ctx, hc, dci) ((xhci_ep_ctx_t *)   XHCI_GET_CTX_FIELD(device, (dev_ctx), (hc), (dci)))
    188 #define XHCI_GET_SLOT_CTX(dev_ctx, hc)    ((xhci_slot_ctx_t *) XHCI_GET_CTX_FIELD(device, (dev_ctx), (hc), 0))
     188#define XHCI_GET_EP_CTX(dev_ctx, hc, dci) \
     189    ((xhci_ep_ctx_t *)   XHCI_GET_CTX_FIELD(device, (dev_ctx), (hc), (dci)))
     190#define XHCI_GET_SLOT_CTX(dev_ctx, hc) \
     191    ((xhci_slot_ctx_t *) XHCI_GET_CTX_FIELD(device, (dev_ctx), (hc), 0))
    189192
    190193/**
     
    210213typedef struct xhci_stream_ctx {
    211214        uint64_t data [2];
    212 #define XHCI_STREAM_DCS(ctx)       XHCI_QWORD_EXTRACT((ctx).data[0],  0, 0)
    213 #define XHCI_STREAM_SCT(ctx)       XHCI_QWORD_EXTRACT((ctx).data[0],  3, 1)
    214 #define XHCI_STREAM_DEQ_PTR(ctx)   (XHCI_QWORD_EXTRACT((ctx).data[0], 63, 4) << 4)
    215 #define XHCI_STREAM_EDTLA(ctx)     XHCI_QWORD_EXTRACT((ctx).data[1], 24, 0)
     215#define XHCI_STREAM_DCS(ctx)     XHCI_QWORD_EXTRACT((ctx).data[0],  0, 0)
     216#define XHCI_STREAM_SCT(ctx)     XHCI_QWORD_EXTRACT((ctx).data[0],  3, 1)
     217#define XHCI_STREAM_DEQ_PTR(ctx) (XHCI_QWORD_EXTRACT((ctx).data[0], 63, 4) << 4)
     218#define XHCI_STREAM_EDTLA(ctx)   XHCI_QWORD_EXTRACT((ctx).data[1], 24, 0)
    216219
    217220#define XHCI_STREAM_SCT_SET(ctx, val) \
     
    232235        uint32_t data [8];
    233236#define XHCI_INPUT_CTRL_CTX_DROP(ctx, idx) \
    234         XHCI_DWORD_EXTRACT((ctx).data[0], (idx), (idx))
     237    XHCI_DWORD_EXTRACT((ctx).data[0], (idx), (idx))
    235238
    236239#define XHCI_INPUT_CTRL_CTX_DROP_SET(ctx, idx) (ctx).data[0] |= (1 << (idx))
     
    238241
    239242#define XHCI_INPUT_CTRL_CTX_ADD(ctx, idx) \
    240         XHCI_DWORD_EXTRACT((ctx).data[1], (idx), (idx))
     243    XHCI_DWORD_EXTRACT((ctx).data[1], (idx), (idx))
    241244
    242245#define XHCI_INPUT_CTRL_CTX_ADD_SET(ctx, idx) (ctx).data[1] |= (1 << (idx))
    243246#define XHCI_INPUT_CTRL_CTX_ADD_CLEAR(ctx, idx) (ctx).data[1] &= ~(1 << (idx))
    244247
    245 #define XHCI_INPUT_CTRL_CTX_CONFIG_VALUE(ctx)   XHCI_DWORD_EXTRACT((ctx).data[7],  7,  0)
    246 #define XHCI_INPUT_CTRL_CTX_IFACE_NUMBER(ctx)   XHCI_DWORD_EXTRACT((ctx).data[7], 15,  8)
    247 #define XHCI_INPUT_CTRL_CTX_ALTER_SETTING(ctx)  XHCI_DWORD_EXTRACT((ctx).data[7], 23, 16)
     248#define XHCI_INPUT_CTRL_CTX_CONFIG_VALUE(ctx) \
     249    XHCI_DWORD_EXTRACT((ctx).data[7],  7,  0)
     250#define XHCI_INPUT_CTRL_CTX_IFACE_NUMBER(ctx) \
     251    XHCI_DWORD_EXTRACT((ctx).data[7], 15,  8)
     252#define XHCI_INPUT_CTRL_CTX_ALTER_SETTING(ctx) \
     253    XHCI_DWORD_EXTRACT((ctx).data[7], 23, 16)
    248254} __attribute__((packed)) xhci_input_ctrl_ctx_t;
    249255
     
    252258 */
    253259#define XHCI_INPUT_CTX_SIZE(hc) (XHCI_ONE_CTX_SIZE(hc) + XHCI_DEVICE_CTX_SIZE(hc))
    254 #define XHCI_GET_CTRL_CTX(ictx, hc)  ((xhci_input_ctrl_ctx_t *) XHCI_GET_CTX_FIELD(input, (ictx), (hc), 0))
    255 #define XHCI_GET_DEVICE_CTX(dev_ctx, hc) ((xhci_device_ctx_t *) XHCI_GET_CTX_FIELD(input, (ictx), (hc), 1))
     260#define XHCI_GET_CTRL_CTX(ictx, hc) \
     261    ((xhci_input_ctrl_ctx_t *) XHCI_GET_CTX_FIELD(input, (ictx), (hc), 0))
     262#define XHCI_GET_DEVICE_CTX(dev_ctx, hc) \
     263    ((xhci_device_ctx_t *) XHCI_GET_CTX_FIELD(input, (ictx), (hc), 1))
    256264
    257265typedef struct xhci_input_ctx {
  • uspace/drv/bus/usb/xhci/hw_struct/trb.h

    r3692678 rae3a941  
    160160 * The Chain bit is valid only in specific TRB types.
    161161 */
    162 static inline bool xhci_trb_is_chained(xhci_trb_t *trb) {
     162static inline bool xhci_trb_is_chained(xhci_trb_t *trb)
     163{
    163164        const int type = TRB_TYPE(*trb);
    164165        const bool chain_bit = XHCI_DWORD_EXTRACT(trb->control, 4, 4);
  • uspace/drv/bus/usb/xhci/isoch.h

    r3692678 rae3a941  
    8484        fibril_timer_t *reset_timer;
    8585
    86         /** The maximum size of an isochronous transfer and therefore the size of buffers */
     86        /**
     87         * The maximum size of an isochronous transfer
     88         * and therefore the size of buffers
     89         */
    8790        size_t max_size;
    8891
     
    123126extern errno_t isoch_schedule_out(xhci_transfer_t *);
    124127extern errno_t isoch_schedule_in(xhci_transfer_t *);
    125 extern void isoch_handle_transfer_event(xhci_hc_t *, xhci_endpoint_t *, xhci_trb_t *);
     128extern void isoch_handle_transfer_event(xhci_hc_t *, xhci_endpoint_t *,
     129    xhci_trb_t *);
    126130
    127131#endif
  • uspace/drv/bus/usb/xhci/main.c

    r3692678 rae3a941  
    6868}
    6969
    70 static errno_t hcd_irq_code_gen(irq_code_t *code, hc_device_t *hcd, const hw_res_list_parsed_t *hw_res, int *irq)
     70static errno_t hcd_irq_code_gen(irq_code_t *code, hc_device_t *hcd,
     71    const hw_res_list_parsed_t *hw_res, int *irq)
    7172{
    7273        xhci_hc_t *hc = hcd_to_hc(hcd);
  • uspace/drv/bus/usb/xhci/streams.h

    r3692678 rae3a941  
    4848        xhci_trb_ring_t ring;
    4949
    50         /** Pointer to the array of secondary stream context data for primary data. */
     50        /**
     51         * Pointer to the array of secondary stream context data for primary
     52         * data.
     53         */
    5154        xhci_stream_data_t *secondary_data;
    5255
     
    6164} xhci_stream_data_t;
    6265
    63 extern xhci_stream_data_t *xhci_get_stream_ctx_data(xhci_endpoint_t *ep, uint32_t stream_id);
    64 extern void xhci_stream_free_ds(xhci_endpoint_t *xhci_ep);
     66extern xhci_stream_data_t *xhci_get_stream_ctx_data(xhci_endpoint_t *, uint32_t);
     67extern void xhci_stream_free_ds(xhci_endpoint_t *);
    6568
    66 extern errno_t xhci_endpoint_remove_streams(xhci_hc_t *hc, xhci_device_t *dev, xhci_endpoint_t *xhci_ep);
    67 extern errno_t xhci_endpoint_request_primary_streams(xhci_hc_t *hc, xhci_device_t *dev,
    68     xhci_endpoint_t *xhci_ep, unsigned count);
    69 extern errno_t xhci_endpoint_request_secondary_streams(xhci_hc_t *hc, xhci_device_t *dev,
    70     xhci_endpoint_t *xhci_ep, unsigned *sizes, unsigned count);
     69extern errno_t xhci_endpoint_remove_streams(xhci_hc_t *, xhci_device_t *,
     70    xhci_endpoint_t *);
     71extern errno_t xhci_endpoint_request_primary_streams(xhci_hc_t *,
     72    xhci_device_t *, xhci_endpoint_t *, unsigned);
     73extern errno_t xhci_endpoint_request_secondary_streams(xhci_hc_t *,
     74    xhci_device_t *, xhci_endpoint_t *, unsigned *, unsigned);
    7175
    7276#endif
  • uspace/drv/bus/usb/xhci/transfers.h

    r3692678 rae3a941  
    5959extern void xhci_transfer_destroy(usb_transfer_batch_t *);
    6060
    61 static inline xhci_transfer_t *xhci_transfer_from_batch(usb_transfer_batch_t *batch)
     61static inline xhci_transfer_t *xhci_transfer_from_batch(
     62    usb_transfer_batch_t *batch)
    6263{
    6364        assert(batch);
  • uspace/drv/bus/usb/xhci/trb_ring.h

    r3692678 rae3a941  
    5757 */
    5858typedef struct xhci_trb_ring {
    59         list_t segments;                /* List of assigned segments */
    60         int segment_count;              /* Number of segments assigned */
     59        list_t segments;                /**< List of assigned segments */
     60        int segment_count;              /**< Number of segments assigned */
    6161
    62         /*
    63          * As the link TRBs connect physical addresses, we need to keep track of
    64          * active segment in virtual memory. The enqueue ptr should always belong
    65          * to the enqueue segment.
     62        /**
     63         * As the link TRBs connect physical addresses, we need to keep track
     64         * of active segment in virtual memory. The enqueue ptr should always
     65         * belong to the enqueue segment.
    6666         */
    6767        trb_segment_t *enqueue_segment;
    6868        xhci_trb_t *enqueue_trb;
    6969
    70         uintptr_t dequeue;              /* Last reported position of the dequeue pointer */
    71         bool pcs;                       /* Producer Cycle State: section 4.9.2 */
     70        uintptr_t dequeue; /**< Last reported position of the dequeue pointer */
     71        bool pcs;          /**< Producer Cycle State: section 4.9.2 */
    7272
    7373        fibril_mutex_t guard;
     
    7676extern errno_t xhci_trb_ring_init(xhci_trb_ring_t *, size_t);
    7777extern void xhci_trb_ring_fini(xhci_trb_ring_t *);
    78 extern errno_t xhci_trb_ring_enqueue(xhci_trb_ring_t *, xhci_trb_t *, uintptr_t *);
    79 extern errno_t xhci_trb_ring_enqueue_multiple(xhci_trb_ring_t *, xhci_trb_t *, size_t, uintptr_t *);
     78extern errno_t xhci_trb_ring_enqueue(xhci_trb_ring_t *, xhci_trb_t *,
     79    uintptr_t *);
     80extern errno_t xhci_trb_ring_enqueue_multiple(xhci_trb_ring_t *, xhci_trb_t *,
     81    size_t, uintptr_t *);
    8082extern size_t xhci_trb_ring_size(xhci_trb_ring_t *);
    8183
    82 extern void xhci_trb_ring_reset_dequeue_state(xhci_trb_ring_t *ring, uintptr_t *addr);
     84extern void xhci_trb_ring_reset_dequeue_state(xhci_trb_ring_t *, uintptr_t *);
    8385
    8486/**
     
    8688 * pointer inside the ring. Otherwise, the ring will soon show up as full.
    8789 */
    88 static inline void xhci_trb_ring_update_dequeue(xhci_trb_ring_t *ring, uintptr_t phys)
     90static inline void xhci_trb_ring_update_dequeue(xhci_trb_ring_t *ring,
     91    uintptr_t phys)
    8992{
    9093        ring->dequeue = phys;
     
    9598 */
    9699typedef struct xhci_event_ring {
    97         list_t segments;                /* List of assigned segments */
    98         int segment_count;              /* Number of segments assigned */
     100        list_t segments;                /**< List of assigned segments */
     101        int segment_count;              /**< Number of segments assigned */
    99102
    100         trb_segment_t *dequeue_segment; /* Current segment of the dequeue ptr */
    101         xhci_trb_t *dequeue_trb;        /* Next TRB to be processed */
    102         uintptr_t dequeue_ptr;          /* Physical address of the ERDP to be reported to the HC */
     103        trb_segment_t *dequeue_segment; /**< Current segment */
     104        xhci_trb_t *dequeue_trb;        /**< Next TRB to be processed */
     105        uintptr_t dequeue_ptr;  /**< Physical ERDP to be reported to the HC */
    103106
    104         dma_buffer_t erst;              /* ERST given to the HC */
     107        dma_buffer_t erst;      /**< ERST given to the HC */
    105108
    106         bool ccs;                       /* Consumer Cycle State: section 4.9.2 */
     109        bool ccs;               /**< Consumer Cycle State: section 4.9.2 */
    107110
    108111        fibril_mutex_t guard;
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