Changeset ae3a941 in mainline for uspace/drv/bus/usb/xhci
- Timestamp:
- 2018-02-26T16:51:40Z (8 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- e773f58
- Parents:
- 3692678
- Location:
- uspace/drv/bus/usb/xhci
- Files:
-
- 14 edited
-
bus.h (modified) (1 diff)
-
commands.c (modified) (7 diffs)
-
commands.h (modified) (1 diff)
-
debug.h (modified) (1 diff)
-
device.h (modified) (2 diffs)
-
endpoint.h (modified) (6 diffs)
-
hc.h (modified) (1 diff)
-
hw_struct/context.h (modified) (6 diffs)
-
hw_struct/trb.h (modified) (1 diff)
-
isoch.h (modified) (2 diffs)
-
main.c (modified) (1 diff)
-
streams.h (modified) (2 diffs)
-
transfers.h (modified) (1 diff)
-
trb_ring.h (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/bus/usb/xhci/bus.h
r3692678 rae3a941 45 45 /** Endpoint management structure */ 46 46 typedef struct xhci_bus { 47 bus_t base; /**< Inheritance. Keep this first. */ 48 49 xhci_hc_t *hc; /**< Pointer to managing HC (to issue commands) */ 50 51 xhci_device_t **devices_by_slot; /**< Devices by Slot ID */ 47 bus_t base; /**< Inheritance. Keep this first. */ 48 xhci_hc_t *hc; /**< Pointer to managing HC (to issue commands) */ 49 xhci_device_t **devices_by_slot; /**< Devices by Slot ID */ 52 50 } xhci_bus_t; 53 51 -
uspace/drv/bus/usb/xhci/commands.c
r3692678 rae3a941 150 150 151 151 while (cmd_link != NULL) { 152 xhci_cmd_t *cmd = list_get_instance(cmd_link, xhci_cmd_t, _header.link); 152 xhci_cmd_t *cmd = list_get_instance(cmd_link, xhci_cmd_t, 153 _header.link); 153 154 154 155 if (cmd->_header.trb_phys == phys) … … 158 159 } 159 160 160 return cmd_link ? list_get_instance(cmd_link, xhci_cmd_t, _header.link) 161 : NULL; 161 return cmd_link 162 ? list_get_instance(cmd_link, xhci_cmd_t, _header.link) 163 : NULL; 162 164 } 163 165 … … 167 169 168 170 cr->state = state; 169 if (state == XHCI_CR_STATE_OPEN 170 || state == XHCI_CR_STATE_CLOSED) 171 if (state == XHCI_CR_STATE_OPEN || state == XHCI_CR_STATE_CLOSED) 171 172 fibril_condvar_broadcast(&cr->state_cv); 172 173 } … … 206 207 } 207 208 208 usb_log_debug("Sending command %s", xhci_trb_str_type(TRB_TYPE(cmd->_header.trb))); 209 usb_log_debug("Sending command %s", 210 xhci_trb_str_type(TRB_TYPE(cmd->_header.trb))); 209 211 210 212 list_append(&cmd->_header.link, &cr->cmd_list); … … 337 339 usb_log_error("Command resulted in error: %s.", trb_codes[code]); 338 340 else 339 usb_log_error("Command resulted in reserved or vendor specific error."); 341 usb_log_error("Command resulted in reserved or " 342 "vendor specific error."); 340 343 } 341 344 … … 657 660 } 658 661 659 usb_log_error("Timeout while waiting for command: aborting current command."); 662 usb_log_error("Timeout while waiting for command: " 663 "aborting current command."); 660 664 661 665 cr_set_state(cr, XHCI_CR_STATE_CHANGING); … … 663 667 abort_command_ring(hc); 664 668 665 fibril_condvar_wait_timeout(&cr->stopped_cv, &cr->guard, XHCI_CR_ABORT_TIMEOUT); 669 fibril_condvar_wait_timeout(&cr->stopped_cv, &cr->guard, 670 XHCI_CR_ABORT_TIMEOUT); 666 671 667 672 if (XHCI_REG_RD(hc->op_regs, XHCI_OP_CRR)) { -
uspace/drv/bus/usb/xhci/commands.h
r3692678 rae3a941 70 70 71 71 typedef enum { 72 XHCI_CR_STATE_CLOSED, /**< Commands are rejected with ENAK. */73 XHCI_CR_STATE_OPEN, /**< Commands are enqueued normally. */74 XHCI_CR_STATE_CHANGING, /**< Commands wait until state changes. */75 XHCI_CR_STATE_FULL, /**< Commands wait until something completes. */72 XHCI_CR_STATE_CLOSED, /**< Commands are rejected with ENAK. */ 73 XHCI_CR_STATE_OPEN, /**< Commands are enqueued normally. */ 74 XHCI_CR_STATE_CHANGING, /**< Commands wait until state changes. */ 75 XHCI_CR_STATE_FULL, /**< Commands wait until something completes. */ 76 76 } xhci_cr_state_t; 77 77 -
uspace/drv/bus/usb/xhci/debug.h
r3692678 rae3a941 63 63 extern void xhci_dump_slot_ctx(const struct xhci_slot_ctx *); 64 64 extern void xhci_dump_endpoint_ctx(const struct xhci_endpoint_ctx *); 65 extern void xhci_dump_input_ctx(const struct xhci_hc *, const struct xhci_input_ctx *); 65 extern void xhci_dump_input_ctx(const struct xhci_hc *, 66 const struct xhci_input_ctx *); 66 67 67 68 #endif -
uspace/drv/bus/usb/xhci/device.h
r3692678 rae3a941 62 62 63 63 #define XHCI_DEV_FMT "(%s, slot %d)" 64 #define XHCI_DEV_ARGS(dev) ddf_fun_get_name((dev).base.fun), (dev).slot_id64 #define XHCI_DEV_ARGS(dev) ddf_fun_get_name((dev).base.fun), (dev).slot_id 65 65 66 66 /* Bus callbacks */ … … 72 72 void xhci_setup_slot_context(xhci_device_t *, xhci_slot_ctx_t *); 73 73 74 static inline xhci_device_t * xhci_device_get(device_t *dev)74 static inline xhci_device_t *xhci_device_get(device_t *dev) 75 75 { 76 76 assert(dev); -
uspace/drv/bus/usb/xhci/endpoint.h
r3692678 rae3a941 76 76 xhci_trb_ring_t ring; 77 77 78 /** Primary stream context data array (or NULL if endpoint doesn't use streams). */ 78 /** 79 * Primary stream context data array 80 * (or NULL if endpoint doesn't use streams). 81 */ 79 82 xhci_stream_data_t *primary_stream_data_array; 80 83 … … 83 86 dma_buffer_t primary_stream_ctx_dma; 84 87 85 /** Size of the allocated primary stream data a rray (and context array). */88 /** Size of the allocated primary stream data and context array. */ 86 89 uint16_t primary_stream_data_size; 87 90 … … 89 92 uint32_t max_streams; 90 93 91 /** Maximum number of consecutive USB transactions (0-15) that should be executed per scheduling opportunity */ 94 /** 95 * Maximum number of consecutive USB transactions (0-15) that 96 * should be executed per scheduling opportunity 97 */ 92 98 uint8_t max_burst; 93 99 94 /** Maximum number of bursts within an interval that this endpoint supports */ 100 /** 101 * Maximum number of bursts within an interval that 102 * this endpoint supports 103 */ 95 104 uint8_t mult; 96 105 97 /** Scheduling interval for periodic endpoints, as a number of 125us units. (0 - 2^16) */ 106 /** 107 * Scheduling interval for periodic endpoints, 108 * as a number of 125us units. (0 - 2^16) 109 */ 98 110 uint32_t interval; 99 111 100 /** This field is a valid pointer for (and only for) isochronous transfers. */ 112 /** 113 * This field is a valid pointer for (and only for) isochronous 114 * endpoints. 115 */ 101 116 xhci_isoch_t isoch [0]; 102 117 } xhci_endpoint_t; … … 111 126 extern int xhci_endpoint_type(xhci_endpoint_t *ep); 112 127 113 extern endpoint_t *xhci_endpoint_create(device_t *, const usb_endpoint_descriptors_t *); 128 extern endpoint_t *xhci_endpoint_create(device_t *, 129 const usb_endpoint_descriptors_t *); 114 130 extern errno_t xhci_endpoint_register(endpoint_t *); 115 131 extern void xhci_endpoint_unregister(endpoint_t *); … … 122 138 extern errno_t xhci_endpoint_clear_halt(xhci_endpoint_t *, unsigned); 123 139 124 static inline xhci_endpoint_t * xhci_endpoint_get(endpoint_t *ep)140 static inline xhci_endpoint_t *xhci_endpoint_get(endpoint_t *ep) 125 141 { 126 142 assert(ep); … … 128 144 } 129 145 130 static inline xhci_device_t * xhci_ep_to_dev(xhci_endpoint_t *ep)146 static inline xhci_device_t *xhci_ep_to_dev(xhci_endpoint_t *ep) 131 147 { 132 148 assert(ep); -
uspace/drv/bus/usb/xhci/hc.h
r3692678 rae3a941 95 95 bool ac64; 96 96 bool csz; 97 uint64_t wrap_time; /**The last time when mfindex wrap happened */98 uint64_t wrap_count; /** Amount of mfindex wraps HC has done */99 unsigned ist; /**< IST in microframes */97 uint64_t wrap_time; /**< The last time when mfindex wrap happened */ 98 uint64_t wrap_count; /**< Amount of mfindex wraps HC has done */ 99 unsigned ist; /**< IST in microframes */ 100 100 101 101 /** Port speed mapping */ -
uspace/drv/bus/usb/xhci/hw_struct/context.h
r3692678 rae3a941 179 179 #define XHCI_CTX_SIZE_SMALL 32 180 180 #define XHCI_ONE_CTX_SIZE(hc) (XHCI_CTX_SIZE_SMALL << hc->csz) 181 #define XHCI_GET_CTX_FIELD(type, ctx, hc, ci) (xhci_##type##_ctx_to_charptr(ctx) + (ci) * XHCI_ONE_CTX_SIZE(hc)) 181 #define XHCI_GET_CTX_FIELD(type, ctx, hc, ci) \ 182 (xhci_##type##_ctx_to_charptr(ctx) + (ci) * XHCI_ONE_CTX_SIZE(hc)) 182 183 183 184 /** … … 185 186 */ 186 187 #define XHCI_DEVICE_CTX_SIZE(hc) ((1 + XHCI_EP_COUNT) * XHCI_ONE_CTX_SIZE(hc)) 187 #define XHCI_GET_EP_CTX(dev_ctx, hc, dci) ((xhci_ep_ctx_t *) XHCI_GET_CTX_FIELD(device, (dev_ctx), (hc), (dci))) 188 #define XHCI_GET_SLOT_CTX(dev_ctx, hc) ((xhci_slot_ctx_t *) XHCI_GET_CTX_FIELD(device, (dev_ctx), (hc), 0)) 188 #define XHCI_GET_EP_CTX(dev_ctx, hc, dci) \ 189 ((xhci_ep_ctx_t *) XHCI_GET_CTX_FIELD(device, (dev_ctx), (hc), (dci))) 190 #define XHCI_GET_SLOT_CTX(dev_ctx, hc) \ 191 ((xhci_slot_ctx_t *) XHCI_GET_CTX_FIELD(device, (dev_ctx), (hc), 0)) 189 192 190 193 /** … … 210 213 typedef struct xhci_stream_ctx { 211 214 uint64_t data [2]; 212 #define XHCI_STREAM_DCS(ctx) XHCI_QWORD_EXTRACT((ctx).data[0], 0, 0)213 #define XHCI_STREAM_SCT(ctx) XHCI_QWORD_EXTRACT((ctx).data[0], 3, 1)214 #define XHCI_STREAM_DEQ_PTR(ctx) (XHCI_QWORD_EXTRACT((ctx).data[0], 63, 4) << 4)215 #define XHCI_STREAM_EDTLA(ctx) XHCI_QWORD_EXTRACT((ctx).data[1], 24, 0)215 #define XHCI_STREAM_DCS(ctx) XHCI_QWORD_EXTRACT((ctx).data[0], 0, 0) 216 #define XHCI_STREAM_SCT(ctx) XHCI_QWORD_EXTRACT((ctx).data[0], 3, 1) 217 #define XHCI_STREAM_DEQ_PTR(ctx) (XHCI_QWORD_EXTRACT((ctx).data[0], 63, 4) << 4) 218 #define XHCI_STREAM_EDTLA(ctx) XHCI_QWORD_EXTRACT((ctx).data[1], 24, 0) 216 219 217 220 #define XHCI_STREAM_SCT_SET(ctx, val) \ … … 232 235 uint32_t data [8]; 233 236 #define XHCI_INPUT_CTRL_CTX_DROP(ctx, idx) \ 234 XHCI_DWORD_EXTRACT((ctx).data[0], (idx), (idx))237 XHCI_DWORD_EXTRACT((ctx).data[0], (idx), (idx)) 235 238 236 239 #define XHCI_INPUT_CTRL_CTX_DROP_SET(ctx, idx) (ctx).data[0] |= (1 << (idx)) … … 238 241 239 242 #define XHCI_INPUT_CTRL_CTX_ADD(ctx, idx) \ 240 XHCI_DWORD_EXTRACT((ctx).data[1], (idx), (idx))243 XHCI_DWORD_EXTRACT((ctx).data[1], (idx), (idx)) 241 244 242 245 #define XHCI_INPUT_CTRL_CTX_ADD_SET(ctx, idx) (ctx).data[1] |= (1 << (idx)) 243 246 #define XHCI_INPUT_CTRL_CTX_ADD_CLEAR(ctx, idx) (ctx).data[1] &= ~(1 << (idx)) 244 247 245 #define XHCI_INPUT_CTRL_CTX_CONFIG_VALUE(ctx) XHCI_DWORD_EXTRACT((ctx).data[7], 7, 0) 246 #define XHCI_INPUT_CTRL_CTX_IFACE_NUMBER(ctx) XHCI_DWORD_EXTRACT((ctx).data[7], 15, 8) 247 #define XHCI_INPUT_CTRL_CTX_ALTER_SETTING(ctx) XHCI_DWORD_EXTRACT((ctx).data[7], 23, 16) 248 #define XHCI_INPUT_CTRL_CTX_CONFIG_VALUE(ctx) \ 249 XHCI_DWORD_EXTRACT((ctx).data[7], 7, 0) 250 #define XHCI_INPUT_CTRL_CTX_IFACE_NUMBER(ctx) \ 251 XHCI_DWORD_EXTRACT((ctx).data[7], 15, 8) 252 #define XHCI_INPUT_CTRL_CTX_ALTER_SETTING(ctx) \ 253 XHCI_DWORD_EXTRACT((ctx).data[7], 23, 16) 248 254 } __attribute__((packed)) xhci_input_ctrl_ctx_t; 249 255 … … 252 258 */ 253 259 #define XHCI_INPUT_CTX_SIZE(hc) (XHCI_ONE_CTX_SIZE(hc) + XHCI_DEVICE_CTX_SIZE(hc)) 254 #define XHCI_GET_CTRL_CTX(ictx, hc) ((xhci_input_ctrl_ctx_t *) XHCI_GET_CTX_FIELD(input, (ictx), (hc), 0)) 255 #define XHCI_GET_DEVICE_CTX(dev_ctx, hc) ((xhci_device_ctx_t *) XHCI_GET_CTX_FIELD(input, (ictx), (hc), 1)) 260 #define XHCI_GET_CTRL_CTX(ictx, hc) \ 261 ((xhci_input_ctrl_ctx_t *) XHCI_GET_CTX_FIELD(input, (ictx), (hc), 0)) 262 #define XHCI_GET_DEVICE_CTX(dev_ctx, hc) \ 263 ((xhci_device_ctx_t *) XHCI_GET_CTX_FIELD(input, (ictx), (hc), 1)) 256 264 257 265 typedef struct xhci_input_ctx { -
uspace/drv/bus/usb/xhci/hw_struct/trb.h
r3692678 rae3a941 160 160 * The Chain bit is valid only in specific TRB types. 161 161 */ 162 static inline bool xhci_trb_is_chained(xhci_trb_t *trb) { 162 static inline bool xhci_trb_is_chained(xhci_trb_t *trb) 163 { 163 164 const int type = TRB_TYPE(*trb); 164 165 const bool chain_bit = XHCI_DWORD_EXTRACT(trb->control, 4, 4); -
uspace/drv/bus/usb/xhci/isoch.h
r3692678 rae3a941 84 84 fibril_timer_t *reset_timer; 85 85 86 /** The maximum size of an isochronous transfer and therefore the size of buffers */ 86 /** 87 * The maximum size of an isochronous transfer 88 * and therefore the size of buffers 89 */ 87 90 size_t max_size; 88 91 … … 123 126 extern errno_t isoch_schedule_out(xhci_transfer_t *); 124 127 extern errno_t isoch_schedule_in(xhci_transfer_t *); 125 extern void isoch_handle_transfer_event(xhci_hc_t *, xhci_endpoint_t *, xhci_trb_t *); 128 extern void isoch_handle_transfer_event(xhci_hc_t *, xhci_endpoint_t *, 129 xhci_trb_t *); 126 130 127 131 #endif -
uspace/drv/bus/usb/xhci/main.c
r3692678 rae3a941 68 68 } 69 69 70 static errno_t hcd_irq_code_gen(irq_code_t *code, hc_device_t *hcd, const hw_res_list_parsed_t *hw_res, int *irq) 70 static errno_t hcd_irq_code_gen(irq_code_t *code, hc_device_t *hcd, 71 const hw_res_list_parsed_t *hw_res, int *irq) 71 72 { 72 73 xhci_hc_t *hc = hcd_to_hc(hcd); -
uspace/drv/bus/usb/xhci/streams.h
r3692678 rae3a941 48 48 xhci_trb_ring_t ring; 49 49 50 /** Pointer to the array of secondary stream context data for primary data. */ 50 /** 51 * Pointer to the array of secondary stream context data for primary 52 * data. 53 */ 51 54 xhci_stream_data_t *secondary_data; 52 55 … … 61 64 } xhci_stream_data_t; 62 65 63 extern xhci_stream_data_t *xhci_get_stream_ctx_data(xhci_endpoint_t * ep, uint32_t stream_id);64 extern void xhci_stream_free_ds(xhci_endpoint_t * xhci_ep);66 extern xhci_stream_data_t *xhci_get_stream_ctx_data(xhci_endpoint_t *, uint32_t); 67 extern void xhci_stream_free_ds(xhci_endpoint_t *); 65 68 66 extern errno_t xhci_endpoint_remove_streams(xhci_hc_t *hc, xhci_device_t *dev, xhci_endpoint_t *xhci_ep); 67 extern errno_t xhci_endpoint_request_primary_streams(xhci_hc_t *hc, xhci_device_t *dev, 68 xhci_endpoint_t *xhci_ep, unsigned count); 69 extern errno_t xhci_endpoint_request_secondary_streams(xhci_hc_t *hc, xhci_device_t *dev, 70 xhci_endpoint_t *xhci_ep, unsigned *sizes, unsigned count); 69 extern errno_t xhci_endpoint_remove_streams(xhci_hc_t *, xhci_device_t *, 70 xhci_endpoint_t *); 71 extern errno_t xhci_endpoint_request_primary_streams(xhci_hc_t *, 72 xhci_device_t *, xhci_endpoint_t *, unsigned); 73 extern errno_t xhci_endpoint_request_secondary_streams(xhci_hc_t *, 74 xhci_device_t *, xhci_endpoint_t *, unsigned *, unsigned); 71 75 72 76 #endif -
uspace/drv/bus/usb/xhci/transfers.h
r3692678 rae3a941 59 59 extern void xhci_transfer_destroy(usb_transfer_batch_t *); 60 60 61 static inline xhci_transfer_t *xhci_transfer_from_batch(usb_transfer_batch_t *batch) 61 static inline xhci_transfer_t *xhci_transfer_from_batch( 62 usb_transfer_batch_t *batch) 62 63 { 63 64 assert(batch); -
uspace/drv/bus/usb/xhci/trb_ring.h
r3692678 rae3a941 57 57 */ 58 58 typedef struct xhci_trb_ring { 59 list_t segments; /* List of assigned segments */60 int segment_count; /* Number of segments assigned */59 list_t segments; /**< List of assigned segments */ 60 int segment_count; /**< Number of segments assigned */ 61 61 62 /* 63 * As the link TRBs connect physical addresses, we need to keep track of64 * active segment in virtual memory. The enqueue ptr should always belong65 * to the enqueue segment.62 /** 63 * As the link TRBs connect physical addresses, we need to keep track 64 * of active segment in virtual memory. The enqueue ptr should always 65 * belong to the enqueue segment. 66 66 */ 67 67 trb_segment_t *enqueue_segment; 68 68 xhci_trb_t *enqueue_trb; 69 69 70 uintptr_t dequeue; /*Last reported position of the dequeue pointer */71 bool pcs; /*Producer Cycle State: section 4.9.2 */70 uintptr_t dequeue; /**< Last reported position of the dequeue pointer */ 71 bool pcs; /**< Producer Cycle State: section 4.9.2 */ 72 72 73 73 fibril_mutex_t guard; … … 76 76 extern errno_t xhci_trb_ring_init(xhci_trb_ring_t *, size_t); 77 77 extern void xhci_trb_ring_fini(xhci_trb_ring_t *); 78 extern errno_t xhci_trb_ring_enqueue(xhci_trb_ring_t *, xhci_trb_t *, uintptr_t *); 79 extern errno_t xhci_trb_ring_enqueue_multiple(xhci_trb_ring_t *, xhci_trb_t *, size_t, uintptr_t *); 78 extern errno_t xhci_trb_ring_enqueue(xhci_trb_ring_t *, xhci_trb_t *, 79 uintptr_t *); 80 extern errno_t xhci_trb_ring_enqueue_multiple(xhci_trb_ring_t *, xhci_trb_t *, 81 size_t, uintptr_t *); 80 82 extern size_t xhci_trb_ring_size(xhci_trb_ring_t *); 81 83 82 extern void xhci_trb_ring_reset_dequeue_state(xhci_trb_ring_t * ring, uintptr_t *addr);84 extern void xhci_trb_ring_reset_dequeue_state(xhci_trb_ring_t *, uintptr_t *); 83 85 84 86 /** … … 86 88 * pointer inside the ring. Otherwise, the ring will soon show up as full. 87 89 */ 88 static inline void xhci_trb_ring_update_dequeue(xhci_trb_ring_t *ring, uintptr_t phys) 90 static inline void xhci_trb_ring_update_dequeue(xhci_trb_ring_t *ring, 91 uintptr_t phys) 89 92 { 90 93 ring->dequeue = phys; … … 95 98 */ 96 99 typedef struct xhci_event_ring { 97 list_t segments; /* List of assigned segments */98 int segment_count; /* Number of segments assigned */100 list_t segments; /**< List of assigned segments */ 101 int segment_count; /**< Number of segments assigned */ 99 102 100 trb_segment_t *dequeue_segment; /* Current segment of the dequeue ptr*/101 xhci_trb_t *dequeue_trb; /* Next TRB to be processed */102 uintptr_t dequeue_ptr; /* Physical address of theERDP to be reported to the HC */103 trb_segment_t *dequeue_segment; /**< Current segment */ 104 xhci_trb_t *dequeue_trb; /**< Next TRB to be processed */ 105 uintptr_t dequeue_ptr; /**< Physical ERDP to be reported to the HC */ 103 106 104 dma_buffer_t erst; /*ERST given to the HC */107 dma_buffer_t erst; /**< ERST given to the HC */ 105 108 106 bool ccs; /*Consumer Cycle State: section 4.9.2 */109 bool ccs; /**< Consumer Cycle State: section 4.9.2 */ 107 110 108 111 fibril_mutex_t guard;
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