Changeset ad7a6c9 in mainline for kernel/arch
- Timestamp:
- 2011-03-30T13:10:24Z (15 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 4ae90f9
- Parents:
- 6e50466 (diff), d6b81941 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the(diff)links above to see all the changes relative to each parent. - Location:
- kernel/arch
- Files:
-
- 8 deleted
- 45 edited
-
abs32le/include/memstr.h (deleted)
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amd64/Makefile.inc (modified) (1 diff)
-
amd64/_link.ld.in (modified) (1 diff)
-
amd64/include/interrupt.h (modified) (2 diffs)
-
amd64/include/memstr.h (deleted)
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amd64/src/amd64.c (modified) (2 diffs)
-
amd64/src/asm.S (modified) (3 diffs)
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amd64/src/interrupt.c (modified) (1 diff)
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arm32/include/mach/integratorcp/integratorcp.h (modified) (1 diff)
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arm32/include/mach/testarm/testarm.h (modified) (1 diff)
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arm32/include/machine_func.h (modified) (1 diff)
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arm32/include/memstr.h (deleted)
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arm32/src/asm.S (modified) (2 diffs)
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arm32/src/exception.c (modified) (1 diff)
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arm32/src/mach/gta02/gta02.c (modified) (4 diffs)
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arm32/src/mach/integratorcp/integratorcp.c (modified) (4 diffs)
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arm32/src/mach/testarm/testarm.c (modified) (2 diffs)
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ia32/_link.ld.in (modified) (2 diffs)
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ia32/include/interrupt.h (modified) (2 diffs)
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ia32/include/memstr.h (deleted)
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ia32/src/asm.S (modified) (3 diffs)
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ia32/src/cpu/cpu.c (modified) (2 diffs)
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ia32/src/drivers/i8259.c (modified) (1 diff)
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ia32/src/ia32.c (modified) (2 diffs)
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ia32/src/interrupt.c (modified) (1 diff)
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ia32/src/smp/apic.c (modified) (1 diff)
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ia64/_link.ld.in (modified) (2 diffs)
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ia64/include/interrupt.h (modified) (1 diff)
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ia64/include/memstr.h (deleted)
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ia64/src/asm.S (modified) (4 diffs)
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ia64/src/ia64.c (modified) (2 diffs)
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ia64/src/mm/tlb.c (modified) (6 diffs)
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mips32/include/cp0.h (modified) (2 diffs)
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mips32/include/memstr.h (deleted)
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mips32/src/asm.S (modified) (1 diff)
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mips32/src/mips32.c (modified) (1 diff)
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mips32/src/mm/tlb.c (modified) (1 diff)
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ppc32/_link.ld.in (modified) (1 diff)
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ppc32/include/memstr.h (deleted)
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ppc32/src/asm.S (modified) (2 diffs)
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ppc32/src/ppc32.c (modified) (1 diff)
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sparc64/_link.ld.in (modified) (1 diff)
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sparc64/include/memstr.h (deleted)
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sparc64/src/asm.S (modified) (2 diffs)
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sparc64/src/drivers/niagara.c (modified) (2 diffs)
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sparc64/src/mm/sun4u/as.c (modified) (1 diff)
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sparc64/src/mm/sun4v/as.c (modified) (1 diff)
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sparc64/src/smp/sun4v/smp.c (modified) (2 diffs)
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sparc64/src/sun4u/sparc64.c (modified) (2 diffs)
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sparc64/src/sun4v/asm.S (modified) (1 diff)
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sparc64/src/sun4v/sparc64.c (modified) (2 diffs)
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sparc64/src/sun4v/start.S (modified) (1 diff)
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sparc64/src/trap/sun4v/interrupt.c (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/amd64/Makefile.inc
r6e50466 rad7a6c9 33 33 34 34 FPU_NO_CFLAGS = -mno-sse -mno-sse2 35 CMN1 = -m64 -mcmodel=large -mno-red-zone -fno-unwind-tables -fno-omit-frame-pointer 35 36 # 37 # FIXME: 38 # 39 # The -fno-optimize-sibling-calls should be removed as soon as a bug 40 # in GCC concerning the "large" memory model and tail call optimization 41 # is fixed. 42 # 43 # If GCC generates a code for tail call, instead of generating .. 44 # 45 # jmp *fnc 46 # 47 # it generates an assembly code with an illegal immediate prefix: 48 # 49 # jmp *$fnc 50 # 51 52 CMN1 = -m64 -mcmodel=large -mno-red-zone -fno-unwind-tables -fno-omit-frame-pointer -fno-optimize-sibling-calls 36 53 GCC_CFLAGS += $(CMN1) 37 54 ICC_CFLAGS += $(CMN1) -
kernel/arch/amd64/_link.ld.in
r6e50466 rad7a6c9 26 26 .mapped (PA2KA(BOOT_OFFSET)+SIZEOF(.unmapped)) : AT (SIZEOF(.unmapped)) { 27 27 ktext_start = .; 28 *(.text );28 *(.text .text.*); 29 29 ktext_end = .; 30 30 31 31 kdata_start = .; 32 *(.data); /* initialized data */33 *(.rodata *);/* string literals */32 *(.data); /* initialized data */ 33 *(.rodata .rodata.*); /* string literals */ 34 34 hardcoded_load_address = .; 35 35 QUAD(PA2KA(BOOT_OFFSET)); -
kernel/arch/amd64/include/interrupt.h
r6e50466 rad7a6c9 55 55 #define IRQ_PIC_SPUR 7 56 56 #define IRQ_MOUSE 12 57 #define IRQ_ DP8390 957 #define IRQ_NE2000 9 58 58 59 59 /* This one must have four least significant bits set to ones */ … … 74 74 extern void (* enable_irqs_function)(uint16_t); 75 75 extern void (* eoi_function)(void); 76 extern const char *irqs_info; 76 77 77 78 extern void interrupt_init(void); -
kernel/arch/amd64/src/amd64.c
r6e50466 rad7a6c9 199 199 void arch_post_smp_init(void) 200 200 { 201 /* Currently the only supported platform for amd64 is 'pc'. */ 202 static const char *platform = "pc"; 203 204 sysinfo_set_item_data("platform", NULL, (void *) platform, 205 str_size(platform)); 206 201 207 #ifdef CONFIG_PC_KBD 202 208 /* … … 229 235 #endif 230 236 231 /* 232 * This nasty hack should also go away ASAP. 233 */ 234 trap_virtual_enable_irqs(1 << IRQ_DP8390); 235 sysinfo_set_item_val("netif.dp8390.inr", NULL, IRQ_DP8390); 237 if (irqs_info != NULL) 238 sysinfo_set_item_val(irqs_info, NULL, true); 239 240 sysinfo_set_item_val("netif.ne2000.inr", NULL, IRQ_NE2000); 236 241 } 237 242 -
kernel/arch/amd64/src/asm.S
r6e50466 rad7a6c9 37 37 .global read_efer_flag 38 38 .global set_efer_flag 39 .global memsetb40 .global memsetw41 .global memcpy42 39 .global memcpy_from_uspace 43 40 .global memcpy_to_uspace … … 46 43 .global early_putchar 47 44 48 /* Wrapper for generic memsetb */49 memsetb:50 jmp _memsetb51 52 /* Wrapper for generic memsetw */53 memsetw:54 jmp _memsetw55 56 45 #define MEMCPY_DST %rdi 57 46 #define MEMCPY_SRC %rsi … … 74 63 * 75 64 */ 76 memcpy:77 65 memcpy_from_uspace: 78 66 memcpy_to_uspace: -
kernel/arch/amd64/src/interrupt.c
r6e50466 rad7a6c9 62 62 void (* enable_irqs_function)(uint16_t irqmask) = NULL; 63 63 void (* eoi_function)(void) = NULL; 64 const char *irqs_info = NULL; 64 65 65 66 void istate_decode(istate_t *istate) -
kernel/arch/arm32/include/mach/integratorcp/integratorcp.h
r6e50466 rad7a6c9 106 106 extern void icp_frame_init(void); 107 107 extern size_t icp_get_irq_count(void); 108 extern const char *icp_get_platform_name(void); 108 109 109 110 extern struct arm_machine_ops icp_machine_ops; -
kernel/arch/arm32/include/mach/testarm/testarm.h
r6e50466 rad7a6c9 74 74 extern void gxemul_frame_init(void); 75 75 extern size_t gxemul_get_irq_count(void); 76 extern const char *gxemul_get_platform_name(void); 76 77 77 78 extern struct arm_machine_ops gxemul_machine_ops; -
kernel/arch/arm32/include/machine_func.h
r6e50466 rad7a6c9 56 56 void (*machine_input_init)(void); 57 57 size_t (*machine_get_irq_count)(void); 58 const char *(*machine_get_platform_name)(void); 58 59 }; 59 60 -
kernel/arch/arm32/src/asm.S
r6e50466 rad7a6c9 29 29 .text 30 30 31 .global memsetb32 .global memsetw33 .global memcpy34 31 .global memcpy_from_uspace 35 32 .global memcpy_to_uspace … … 38 35 .global early_putchar 39 36 40 memsetb:41 b _memsetb42 43 memsetw:44 b _memsetw45 46 memcpy:47 37 memcpy_from_uspace: 48 38 memcpy_to_uspace: -
kernel/arch/arm32/src/exception.c
r6e50466 rad7a6c9 35 35 36 36 #include <arch/exception.h> 37 #include <arch/memstr.h>38 37 #include <arch/regutils.h> 39 38 #include <arch/machine_func.h> -
kernel/arch/arm32/src/mach/gta02/gta02.c
r6e50466 rad7a6c9 71 71 static void gta02_input_init(void); 72 72 static size_t gta02_get_irq_count(void); 73 static const char *gta02_get_platform_name(void); 73 74 74 75 static void gta02_timer_irq_init(void); … … 92 93 gta02_output_init, 93 94 gta02_input_init, 94 gta02_get_irq_count 95 gta02_get_irq_count, 96 gta02_get_platform_name 95 97 }; 96 98 … … 172 174 fb_parea.pbase = GTA02_FB_BASE; 173 175 fb_parea.frames = 150; 176 fb_parea.unpriv = false; 174 177 ddi_parea_register(&fb_parea); 175 178 } … … 235 238 } 236 239 240 const char *gta02_get_platform_name(void) 241 { 242 return "gta02"; 243 } 244 237 245 static void gta02_timer_irq_init(void) 238 246 { -
kernel/arch/arm32/src/mach/integratorcp/integratorcp.c
r6e50466 rad7a6c9 65 65 icp_output_init, 66 66 icp_input_init, 67 icp_get_irq_count 67 icp_get_irq_count, 68 icp_get_platform_name 68 69 }; 69 70 … … 291 292 .y = 480, 292 293 .scan = 2560, 293 .visual = VISUAL_ BGR_0_8_8_8,294 .visual = VISUAL_RGB_8_8_8_0, 294 295 }; 295 296 … … 299 300 fb_parea.pbase = ICP_FB; 300 301 fb_parea.frames = 300; 302 fb_parea.unpriv = false; 301 303 ddi_parea_register(&fb_parea); 302 304 } … … 342 344 } 343 345 346 const char *icp_get_platform_name(void) 347 { 348 return "integratorcp"; 349 } 350 344 351 /** @} 345 352 */ -
kernel/arch/arm32/src/mach/testarm/testarm.c
r6e50466 rad7a6c9 65 65 gxemul_output_init, 66 66 gxemul_input_init, 67 gxemul_get_irq_count 67 gxemul_get_irq_count, 68 gxemul_get_platform_name 68 69 }; 69 70 … … 132 133 } 133 134 135 const char *gxemul_get_platform_name(void) 136 { 137 return "gxemul"; 138 } 139 134 140 /** Starts gxemul Real Time Clock device, which asserts regular interrupts. 135 141 * -
kernel/arch/ia32/_link.ld.in
r6e50466 rad7a6c9 25 25 .mapped (PA2KA(BOOT_OFFSET)+SIZEOF(.unmapped)): AT (SIZEOF(.unmapped)) { 26 26 ktext_start = .; 27 *(.text );27 *(.text .text.*); 28 28 ktext_end = .; 29 29 30 30 kdata_start = .; 31 31 *(.data); /* initialized data */ 32 *(.rodata *);/* string literals */32 *(.rodata .rodata.*); /* string literals */ 33 33 *(COMMON); /* global variables */ 34 34 hardcoded_load_address = .; … … 49 49 } 50 50 51 #ifdef CONFIG_LINE_DEBUG 52 .comment 0 : { *(.comment); } 53 .debug_abbrev 0 : { *(.debug_abbrev); } 54 .debug_aranges 0 : { *(.debug_aranges); } 55 .debug_info 0 : { *(.debug_info); } 56 .debug_line 0 : { *(.debug_line); } 57 .debug_loc 0 : { *(.debug_loc); } 58 .debug_pubnames 0 : { *(.debug_pubnames); } 59 .debug_pubtypes 0 : { *(.debug_pubtypes); } 60 .debug_ranges 0 : { *(.debug_ranges); } 61 .debug_str 0 : { *(.debug_str); } 62 #endif 63 51 64 /DISCARD/ : { 52 *(.note.GNU-stack); 53 *(.comment); 65 *(*); 54 66 } 55 67 -
kernel/arch/ia32/include/interrupt.h
r6e50466 rad7a6c9 55 55 #define IRQ_PIC_SPUR 7 56 56 #define IRQ_MOUSE 12 57 #define IRQ_ DP8390 957 #define IRQ_NE2000 5 58 58 59 59 /* This one must have four least significant bits set to ones */ … … 74 74 extern void (* enable_irqs_function)(uint16_t); 75 75 extern void (* eoi_function)(void); 76 extern const char *irqs_info; 76 77 77 78 extern void interrupt_init(void); -
kernel/arch/ia32/src/asm.S
r6e50466 rad7a6c9 38 38 .global paging_on 39 39 .global enable_l_apic_in_msr 40 .global memsetb41 .global memsetw42 .global memcpy43 40 .global memcpy_from_uspace 44 41 .global memcpy_from_uspace_failover_address … … 47 44 .global early_putchar 48 45 49 /* Wrapper for generic memsetb */50 memsetb:51 jmp _memsetb52 53 /* Wrapper for generic memsetw */54 memsetw:55 jmp _memsetw56 57 46 #define MEMCPY_DST 4 58 47 #define MEMCPY_SRC 8 … … 74 63 * 75 64 */ 76 memcpy:77 65 memcpy_from_uspace: 78 66 memcpy_to_uspace: -
kernel/arch/ia32/src/cpu/cpu.c
r6e50466 rad7a6c9 92 92 void cpu_arch_init(void) 93 93 { 94 cpuid_extended_feature_info efi;95 94 cpu_info_t info; 96 95 uint32_t help = 0; … … 104 103 105 104 CPU->arch.fi.word = info.cpuid_edx; 106 efi.word = info.cpuid_ecx;107 105 108 106 if (CPU->arch.fi.bits.fxsr) -
kernel/arch/ia32/src/drivers/i8259.c
r6e50466 rad7a6c9 86 86 disable_irqs_function = pic_disable_irqs; 87 87 eoi_function = pic_eoi; 88 irqs_info = "i8259"; 88 89 89 90 pic_disable_irqs(0xffff); /* disable all irq's */ -
kernel/arch/ia32/src/ia32.c
r6e50466 rad7a6c9 157 157 void arch_post_smp_init(void) 158 158 { 159 /* Currently the only supported platform for ia32 is 'pc'. */ 160 static const char *platform = "pc"; 161 162 sysinfo_set_item_data("platform", NULL, (void *) platform, 163 str_size(platform)); 164 159 165 #ifdef CONFIG_PC_KBD 160 166 /* … … 187 193 #endif 188 194 189 /* 190 * This nasty hack should also go away ASAP. 191 */ 192 trap_virtual_enable_irqs(1 << IRQ_DP8390); 193 sysinfo_set_item_val("netif.dp8390.inr", NULL, IRQ_DP8390); 195 if (irqs_info != NULL) 196 sysinfo_set_item_val(irqs_info, NULL, true); 197 198 sysinfo_set_item_val("netif.ne2000.inr", NULL, IRQ_NE2000); 194 199 } 195 200 -
kernel/arch/ia32/src/interrupt.c
r6e50466 rad7a6c9 62 62 void (* enable_irqs_function)(uint16_t irqmask) = NULL; 63 63 void (* eoi_function)(void) = NULL; 64 const char *irqs_info = NULL; 64 65 65 66 void istate_decode(istate_t *istate) -
kernel/arch/ia32/src/smp/apic.c
r6e50466 rad7a6c9 178 178 disable_irqs_function = io_apic_disable_irqs; 179 179 eoi_function = l_apic_eoi; 180 irqs_info = "apic"; 180 181 181 182 /* -
kernel/arch/ia64/_link.ld.in
r6e50466 rad7a6c9 16 16 ktext_start = .; 17 17 *(K_TEXT_START); 18 *(.text )18 *(.text .text.*) 19 19 ktext_end = .; 20 20 … … 36 36 *(.bss) 37 37 *(COMMON); 38 38 39 39 . = ALIGN(8); 40 symbol_table = .;41 *(symtab.*); /* Symbol table, must be LAST symbol!*/42 40 symbol_table = .; 41 *(symtab.*); /* Symbol table, must be LAST symbol!*/ 42 43 43 kdata_end = .; 44 44 } 45 45 46 46 /DISCARD/ : { 47 47 *(*); 48 48 } 49 50 49 } -
kernel/arch/ia64/include/interrupt.h
r6e50466 rad7a6c9 61 61 #define IRQ_KBD (0x01 + LEGACY_INTERRUPT_BASE) 62 62 #define IRQ_MOUSE (0x0c + LEGACY_INTERRUPT_BASE) 63 #define IRQ_ DP8390 (0x09 + LEGACY_INTERRUPT_BASE)63 #define IRQ_NE2000 (0x09 + LEGACY_INTERRUPT_BASE) 64 64 65 65 /** General Exception codes. */ -
kernel/arch/ia64/src/asm.S
r6e50466 rad7a6c9 30 30 31 31 .text 32 .global memcpy33 32 .global memcpy_from_uspace 34 33 .global memcpy_to_uspace … … 39 38 * 40 39 * This memcpy() has been taken from the assembler output of 41 * the generic _memcpy() and modified to have the failover part. 40 * a plain C implementation of memcpy() modified to have the 41 * failover part. 42 42 * 43 43 * @param in0 Destination address. … … 46 46 * 47 47 */ 48 memcpy:49 48 memcpy_from_uspace: 50 49 memcpy_to_uspace: … … 141 140 br.ret.sptk.many rp 142 141 143 .global memsetb144 memsetb:145 br _memsetb146 147 .global memsetw148 memsetw:149 br _memsetw150 151 142 .global cpu_halt 152 143 cpu_halt: -
kernel/arch/ia64/src/ia64.c
r6e50466 rad7a6c9 147 147 void arch_post_smp_init(void) 148 148 { 149 static const char *platform; 150 151 /* Set platform name. */ 152 #ifdef MACHINE_ski 153 platform = "pc"; 154 #endif 155 #ifdef MACHINE_i460GX 156 platform = "i460GX"; 157 #endif 158 sysinfo_set_item_data("platform", NULL, (void *) platform, 159 str_size(platform)); 160 149 161 #ifdef MACHINE_ski 150 162 ski_instance_t *ski_instance = skiin_init(); … … 210 222 #endif 211 223 212 sysinfo_set_item_val("netif. dp8390.inr", NULL, IRQ_DP8390);224 sysinfo_set_item_val("netif.ne2000.inr", NULL, IRQ_NE2000); 213 225 214 226 sysinfo_set_item_val("ia64_iospace", NULL, true); -
kernel/arch/ia64/src/mm/tlb.c
r6e50466 rad7a6c9 475 475 void alternate_instruction_tlb_fault(uint64_t vector, istate_t *istate) 476 476 { 477 region_register_t rr;478 rid_t rid;479 477 uintptr_t va; 480 478 pte_t *t; 481 479 482 480 va = istate->cr_ifa; /* faulting address */ 483 rr.word = rr_read(VA2VRN(va));484 rid = rr.map.rid;485 481 486 482 page_table_lock(AS, true); … … 649 645 void data_dirty_bit_fault(uint64_t vector, istate_t *istate) 650 646 { 651 region_register_t rr;652 rid_t rid;653 647 uintptr_t va; 654 648 pte_t *t; 655 649 656 650 va = istate->cr_ifa; /* faulting address */ 657 rr.word = rr_read(VA2VRN(va));658 rid = rr.map.rid;659 651 660 652 page_table_lock(AS, true); … … 686 678 void instruction_access_bit_fault(uint64_t vector, istate_t *istate) 687 679 { 688 region_register_t rr;689 rid_t rid;690 680 uintptr_t va; 691 681 pte_t *t; 692 682 693 683 va = istate->cr_ifa; /* faulting address */ 694 rr.word = rr_read(VA2VRN(va));695 rid = rr.map.rid;696 684 697 685 page_table_lock(AS, true); … … 723 711 void data_access_bit_fault(uint64_t vector, istate_t *istate) 724 712 { 725 region_register_t rr;726 rid_t rid;727 713 uintptr_t va; 728 714 pte_t *t; 729 715 730 716 va = istate->cr_ifa; /* faulting address */ 731 rr.word = rr_read(VA2VRN(va));732 rid = rr.map.rid;733 717 734 718 page_table_lock(AS, true); … … 760 744 void data_access_rights_fault(uint64_t vector, istate_t *istate) 761 745 { 762 region_register_t rr;763 rid_t rid;764 746 uintptr_t va; 765 747 pte_t *t; 766 748 767 749 va = istate->cr_ifa; /* faulting address */ 768 rr.word = rr_read(VA2VRN(va));769 rid = rr.map.rid;770 750 771 751 /* … … 792 772 void page_not_present(uint64_t vector, istate_t *istate) 793 773 { 794 region_register_t rr;795 rid_t rid;796 774 uintptr_t va; 797 775 pte_t *t; 798 776 799 777 va = istate->cr_ifa; /* faulting address */ 800 rr.word = rr_read(VA2VRN(va));801 rid = rr.map.rid;802 778 803 779 page_table_lock(AS, true); -
kernel/arch/mips32/include/cp0.h
r6e50466 rad7a6c9 70 70 { \ 71 71 uint32_t retval; \ 72 asm ("mfc0 %0, $" #reg : "=r"(retval)); \72 asm volatile ("mfc0 %0, $" #reg : "=r"(retval)); \ 73 73 return retval; \ 74 74 } … … 76 76 #define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(uint32_t val) \ 77 77 { \ 78 asm ("mtc0 %0, $" #reg : : "r"(val) ); \78 asm volatile ("mtc0 %0, $" #reg : : "r"(val) ); \ 79 79 } 80 80 -
kernel/arch/mips32/src/asm.S
r6e50466 rad7a6c9 57 57 nop 58 58 59 .global memsetb60 memsetb:61 j _memsetb62 nop63 64 .global memsetw65 memsetw:66 j _memsetw67 nop68 69 .global memcpy70 59 .global memcpy_from_uspace 71 60 .global memcpy_to_uspace 72 61 .global memcpy_from_uspace_failover_address 73 62 .global memcpy_to_uspace_failover_address 74 memcpy:75 63 memcpy_from_uspace: 76 64 memcpy_to_uspace: -
kernel/arch/mips32/src/mips32.c
r6e50466 rad7a6c9 168 168 void arch_post_smp_init(void) 169 169 { 170 static const char *platform; 171 172 /* Set platform name. */ 173 #ifdef MACHINE_msim 174 platform = "msim"; 175 #endif 176 #ifdef MACHINE_bgxemul 177 platform = "gxemul"; 178 #endif 179 #ifdef MACHINE_lgxemul 180 platform = "gxemul"; 181 #endif 182 sysinfo_set_item_data("platform", NULL, (void *) platform, 183 str_size(platform)); 184 170 185 #ifdef CONFIG_MIPS_KBD 171 186 /* -
kernel/arch/mips32/src/mm/tlb.c
r6e50466 rad7a6c9 557 557 entry_hi_t hi, hi_save; 558 558 tlb_index_t index; 559 560 ASSERT(asid != ASID_INVALID); 559 560 if (asid == ASID_INVALID) 561 return; 561 562 562 563 hi_save.value = cp0_entry_hi_read(); -
kernel/arch/ppc32/_link.ld.in
r6e50466 rad7a6c9 36 36 kdata_start = .; 37 37 *(K_DATA_START); 38 *(.rodata); 39 *(.rodata.*); 38 *(.rodata .rodata.*); 40 39 *(.data); /* initialized data */ 41 40 *(.sdata); -
kernel/arch/ppc32/src/asm.S
r6e50466 rad7a6c9 35 35 .global iret 36 36 .global iret_syscall 37 .global memsetb38 .global memsetw39 .global memcpy40 37 .global memcpy_from_uspace 41 38 .global memcpy_to_uspace … … 208 205 rfi 209 206 210 memsetb:211 b _memsetb212 213 memsetw:214 b _memsetw215 216 memcpy:217 207 memcpy_from_uspace: 218 208 memcpy_to_uspace: -
kernel/arch/ppc32/src/ppc32.c
r6e50466 rad7a6c9 249 249 void arch_post_smp_init(void) 250 250 { 251 /* Currently the only supported platform for ppc32 is 'mac'. */ 252 static const char *platform = "mac"; 253 254 sysinfo_set_item_data("platform", NULL, (void *) platform, 255 str_size(platform)); 256 251 257 ofw_tree_walk_by_device_type("mac-io", macio_register, NULL); 252 258 } -
kernel/arch/sparc64/_link.ld.in
r6e50466 rad7a6c9 15 15 ktext_start = .; 16 16 *(K_TEXT_START) 17 *(.text );17 *(.text .text.*); 18 18 ktext_end = .; 19 19 20 20 kdata_start = .; 21 21 *(K_DATA_START) 22 *(.rodata); 23 *(.rodata.*); 22 *(.rodata .rodata.*); 24 23 *(.data); /* initialized data */ 25 24 *(.sdata); -
kernel/arch/sparc64/src/asm.S
r6e50466 rad7a6c9 34 34 .register %g2, #scratch 35 35 .register %g3, #scratch 36 37 /*38 * This is the assembly language version of our _memcpy() generated by gcc.39 */40 .global memcpy41 memcpy:42 mov %o0, %o3 /* save dst */43 add %o1, 7, %g144 and %g1, -8, %g145 cmp %o1, %g146 be,pn %xcc, 3f47 add %o0, 7, %g148 mov 0, %g349 50 0:51 52 brz,pn %o2, 2f53 mov 0, %g254 55 1:56 57 ldub [%g3 + %o1], %g158 add %g2, 1, %g259 cmp %o2, %g260 stb %g1, [%g3 + %o0]61 bne,pt %xcc, 1b62 mov %g2, %g363 64 2:65 66 jmp %o7 + 8 /* exit point */67 mov %o3, %o068 69 3:70 71 and %g1, -8, %g172 cmp %o0, %g173 bne,pt %xcc, 0b74 mov 0, %g375 srlx %o2, 3, %g476 brz,pn %g4, 5f77 mov 0, %g578 79 4:80 81 sllx %g3, 3, %g282 add %g5, 1, %g383 ldx [%o1 + %g2], %g184 mov %g3, %g585 cmp %g4, %g386 bne,pt %xcc, 4b87 stx %g1, [%o0 + %g2]88 89 5:90 91 and %o2, 7, %o292 brz,pn %o2, 2b93 sllx %g4, 3, %g194 mov 0, %g295 add %g1, %o0, %o096 add %g1, %o1, %g497 mov 0, %g398 99 6:100 101 ldub [%g2 + %g4], %g1102 stb %g1, [%g2 + %o0]103 add %g3, 1, %g2104 cmp %o2, %g2105 bne,pt %xcc, 6b106 mov %g2, %g3107 108 jmp %o7 + 8 /* exit point */109 mov %o3, %o0110 36 111 37 /* … … 264 190 mov %g0, %o0 /* return 0 on failure */ 265 191 266 .global memsetb267 memsetb:268 ba %xcc, _memsetb269 nop270 271 .global memsetw272 memsetw:273 ba %xcc, _memsetw274 nop275 276 192 .global early_putchar 277 193 early_putchar: -
kernel/arch/sparc64/src/drivers/niagara.c
r6e50466 rad7a6c9 216 216 outbuf_parea.pbase = (uintptr_t) (KA2PA(&output_buffer)); 217 217 outbuf_parea.frames = 1; 218 outbuf_parea.unpriv = false; 218 219 ddi_parea_register(&outbuf_parea); 219 220 … … 221 222 inbuf_parea.pbase = (uintptr_t) (KA2PA(&input_buffer)); 222 223 inbuf_parea.frames = 1; 224 inbuf_parea.unpriv = false; 223 225 ddi_parea_register(&inbuf_parea); 224 226 -
kernel/arch/sparc64/src/mm/sun4u/as.c
r6e50466 rad7a6c9 43 43 44 44 #include <arch/mm/tsb.h> 45 #include <arch/memstr.h>46 45 #include <arch/asm.h> 47 46 #include <mm/frame.h> -
kernel/arch/sparc64/src/mm/sun4v/as.c
r6e50466 rad7a6c9 46 46 47 47 #include <arch/mm/tsb.h> 48 #include <arch/memstr.h>49 48 #include <arch/asm.h> 50 49 #include <mm/frame.h> -
kernel/arch/sparc64/src/smp/sun4v/smp.c
r6e50466 rad7a6c9 1 1 /* 2 2 * Copyright (c) 2006 Jakub Jermar 3 * Copyright (c) 2009 Pavel Rimsky 3 * Copyright (c) 2009 Pavel Rimsky 4 4 * All rights reserved. 5 5 * … … 439 439 if (waitq_sleep_timeout(&ap_completion_wq, 10000000, SYNCH_FLAGS_NONE) == 440 440 ESYNCH_TIMEOUT) 441 printf("%s: waiting for processor (cpuid = %" PRIu 32") timed out\n",441 printf("%s: waiting for processor (cpuid = %" PRIu64 ") timed out\n", 442 442 __func__, cpuid); 443 443 -
kernel/arch/sparc64/src/sun4u/sparc64.c
r6e50466 rad7a6c9 50 50 #include <ddi/irq.h> 51 51 #include <str.h> 52 #include <sysinfo/sysinfo.h> 52 53 53 54 memmap_t memmap; … … 111 112 void arch_post_smp_init(void) 112 113 { 114 /* Currently the only supported platform for sparc64/sun4u is 'sun4u'. */ 115 static const char *platform = "sun4u"; 116 117 sysinfo_set_item_data("platform", NULL, (void *) platform, 118 str_size(platform)); 119 113 120 standalone_sparc64_console_init(); 114 121 } -
kernel/arch/sparc64/src/sun4v/asm.S
r6e50466 rad7a6c9 41 41 .global switch_to_userspace 42 42 switch_to_userspace: 43 wrpr PSTATE_PRIV_BIT, %pstate 44 save %o1, -STACK_WINDOW_SAVE_AREA_SIZE, %sp 43 save %o1, -(STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE), %sp 45 44 flushw 46 45 wrpr %g0, 0, %cleanwin ! avoid information leak -
kernel/arch/sparc64/src/sun4v/sparc64.c
r6e50466 rad7a6c9 52 52 #include <str.h> 53 53 #include <arch/drivers/niagara.h> 54 #include <sysinfo/sysinfo.h> 54 55 55 56 memmap_t memmap; … … 109 110 void arch_post_smp_init(void) 110 111 { 112 /* Currently the only supported platform for sparc64/sun4v is 'sun4v'. */ 113 static const char *platform = "sun4v"; 114 115 sysinfo_set_item_data("platform", NULL, (void *) platform, 116 str_size(platform)); 117 111 118 niagarain_init(); 112 119 } -
kernel/arch/sparc64/src/sun4v/start.S
r6e50466 rad7a6c9 296 296 * Create the first stack frame. 297 297 */ 298 save %sp, -(STACK_WIND WO_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE), %sp298 save %sp, -(STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE), %sp 299 299 flushw 300 300 add %g0, -STACK_BIAS, %fp -
kernel/arch/sparc64/src/trap/sun4v/interrupt.c
r6e50466 rad7a6c9 111 111 ((void (*)(void)) data1)(); 112 112 } else { 113 printf("Spurious interrupt on % d, data = %" PRIx64 ".\n",113 printf("Spurious interrupt on %" PRIu64 ", data = %" PRIx64 ".\n", 114 114 CPU->arch.id, data1); 115 115 }
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