Index: kernel/genarch/src/kbd/z8530.c
===================================================================
--- kernel/genarch/src/kbd/z8530.c	(revision f9a56c06291b17dff86c61d294ec807828f33f96)
+++ kernel/genarch/src/kbd/z8530.c	(revision ab1ae2d9f7221f74f7542354c35540bbba78eb6a)
@@ -42,4 +42,5 @@
 #include <arch/drivers/z8530.h>
 #include <arch/interrupt.h>
+#include <arch/drivers/kbd.h>
 #include <cpu.h>
 #include <arch/asm.h>
@@ -49,4 +50,6 @@
 #include <console/console.h>
 #include <interrupt.h>
+#include <sysinfo/sysinfo.h>
+#include <print.h>
 
 /*
@@ -54,4 +57,6 @@
  */
 #define IGNORE_CODE	0x7f		/* all keys up */
+
+bool z8530_belongs_to_kernel = true;
 
 static void z8530_suspend(chardev_t *);
@@ -70,4 +75,5 @@
 void z8530_grab(void)
 {
+	z8530_belongs_to_kernel = true;
 }
 
@@ -75,4 +81,5 @@
 void z8530_release(void)
 {
+	z8530_belongs_to_kernel = false;
 }
 
@@ -83,12 +90,22 @@
 	stdin = &kbrd;
 
+	sysinfo_set_item_val("kbd", NULL, true);
+	sysinfo_set_item_val("kbd.irq", NULL, 0);
+	sysinfo_set_item_val("kbd.address.virtual", NULL, (uintptr_t) kbd_virt_address);
+
 	(void) z8530_read_a(RR8);
 
-	z8530_write_a(WR1, WR1_IARCSC);	/* interrupt on all characters */
+	/*
+	 * Clear any pending TX interrupts or we never manage
+	 * to set FHC UART interrupt state to idle.
+	 */
+	z8530_write_a(WR0, WR0_TX_IP_RST);
+
+	z8530_write_a(WR1, WR1_IARCSC);		/* interrupt on all characters */
 
 	/* 8 bits per character and enable receiver */
 	z8530_write_a(WR3, WR3_RX8BITSCH | WR3_RX_ENABLE);
 	
-	z8530_write_a(WR9, WR9_MIE);	/* Master Interrupt Enable. */
+	z8530_write_a(WR9, WR9_MIE);		/* Master Interrupt Enable. */
 	
 	/*