Index: kernel/arch/ia64/include/arch/asm.h
===================================================================
--- kernel/arch/ia64/include/arch/asm.h	(revision a01f7320d7baed06438e7cde66ccddacc299ba1d)
+++ kernel/arch/ia64/include/arch/asm.h	(revision aaf9789c9a5106f7a4fccf6b7a23f0ca726ab545)
@@ -45,5 +45,5 @@
 
 /** Map the I/O port address to a legacy I/O address. */
-NO_TRACE static inline uintptr_t p2a(volatile void *p)
+_NO_TRACE static inline uintptr_t p2a(volatile void *p)
 {
 	uintptr_t prt = (uintptr_t) p;
@@ -52,5 +52,5 @@
 }
 
-NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
+_NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
 {
 	if (port < (ioport8_t *) IO_SPACE_BOUNDARY)
@@ -66,5 +66,5 @@
 }
 
-NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
+_NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
 {
 	if (port < (ioport16_t *) IO_SPACE_BOUNDARY)
@@ -80,5 +80,5 @@
 }
 
-NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
+_NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
 {
 	if (port < (ioport32_t *) IO_SPACE_BOUNDARY)
@@ -94,5 +94,5 @@
 }
 
-NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
+_NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
 {
 	uint8_t v;
@@ -116,5 +116,5 @@
 }
 
-NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
+_NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
 {
 	uint16_t v;
@@ -138,5 +138,5 @@
 }
 
-NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
+_NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
 {
 	uint32_t v;
@@ -166,5 +166,5 @@
  * The memory stack must start on page boundary.
  */
-NO_TRACE static inline uintptr_t get_stack_base(void)
+_NO_TRACE static inline uintptr_t get_stack_base(void)
 {
 	uint64_t value;
@@ -183,5 +183,5 @@
  *
  */
-NO_TRACE static inline uint64_t psr_read(void)
+_NO_TRACE static inline uint64_t psr_read(void)
 {
 	uint64_t v;
@@ -200,5 +200,5 @@
  *
  */
-NO_TRACE static inline uint64_t iva_read(void)
+_NO_TRACE static inline uint64_t iva_read(void)
 {
 	uint64_t v;
@@ -217,5 +217,5 @@
  *
  */
-NO_TRACE static inline void iva_write(uint64_t v)
+_NO_TRACE static inline void iva_write(uint64_t v)
 {
 	asm volatile (
@@ -231,5 +231,5 @@
  *
  */
-NO_TRACE static inline uint64_t ivr_read(void)
+_NO_TRACE static inline uint64_t ivr_read(void)
 {
 	uint64_t v;
@@ -243,5 +243,5 @@
 }
 
-NO_TRACE static inline uint64_t cr64_read(void)
+_NO_TRACE static inline uint64_t cr64_read(void)
 {
 	uint64_t v;
@@ -260,5 +260,5 @@
  *
  */
-NO_TRACE static inline void itc_write(uint64_t v)
+_NO_TRACE static inline void itc_write(uint64_t v)
 {
 	asm volatile (
@@ -273,5 +273,5 @@
  *
  */
-NO_TRACE static inline uint64_t itc_read(void)
+_NO_TRACE static inline uint64_t itc_read(void)
 {
 	uint64_t v;
@@ -290,5 +290,5 @@
  *
  */
-NO_TRACE static inline void itm_write(uint64_t v)
+_NO_TRACE static inline void itm_write(uint64_t v)
 {
 	asm volatile (
@@ -303,5 +303,5 @@
  *
  */
-NO_TRACE static inline uint64_t itm_read(void)
+_NO_TRACE static inline uint64_t itm_read(void)
 {
 	uint64_t v;
@@ -320,5 +320,5 @@
  *
  */
-NO_TRACE static inline uint64_t itv_read(void)
+_NO_TRACE static inline uint64_t itv_read(void)
 {
 	uint64_t v;
@@ -337,5 +337,5 @@
  *
  */
-NO_TRACE static inline void itv_write(uint64_t v)
+_NO_TRACE static inline void itv_write(uint64_t v)
 {
 	asm volatile (
@@ -350,5 +350,5 @@
  *
  */
-NO_TRACE static inline void eoi_write(uint64_t v)
+_NO_TRACE static inline void eoi_write(uint64_t v)
 {
 	asm volatile (
@@ -363,5 +363,5 @@
  *
  */
-NO_TRACE static inline uint64_t tpr_read(void)
+_NO_TRACE static inline uint64_t tpr_read(void)
 {
 	uint64_t v;
@@ -380,5 +380,5 @@
  *
  */
-NO_TRACE static inline void tpr_write(uint64_t v)
+_NO_TRACE static inline void tpr_write(uint64_t v)
 {
 	asm volatile (
@@ -396,5 +396,5 @@
  *
  */
-NO_TRACE static ipl_t interrupts_disable(void)
+_NO_TRACE static ipl_t interrupts_disable(void)
 {
 	uint64_t v;
@@ -418,5 +418,5 @@
  *
  */
-NO_TRACE static ipl_t interrupts_enable(void)
+_NO_TRACE static ipl_t interrupts_enable(void)
 {
 	uint64_t v;
@@ -441,5 +441,5 @@
  *
  */
-NO_TRACE static inline void interrupts_restore(ipl_t ipl)
+_NO_TRACE static inline void interrupts_restore(ipl_t ipl)
 {
 	if (ipl & PSR_I_MASK)
@@ -454,5 +454,5 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_read(void)
+_NO_TRACE static inline ipl_t interrupts_read(void)
 {
 	return (ipl_t) psr_read();
@@ -464,5 +464,5 @@
  *
  */
-NO_TRACE static inline bool interrupts_disabled(void)
+_NO_TRACE static inline bool interrupts_disabled(void)
 {
 	return !(psr_read() & PSR_I_MASK);
@@ -470,5 +470,5 @@
 
 /** Disable protection key checking. */
-NO_TRACE static inline void pk_disable(void)
+_NO_TRACE static inline void pk_disable(void)
 {
 	asm volatile (
Index: kernel/arch/ia64/include/arch/cpu.h
===================================================================
--- kernel/arch/ia64/include/arch/cpu.h	(revision a01f7320d7baed06438e7cde66ccddacc299ba1d)
+++ kernel/arch/ia64/include/arch/cpu.h	(revision aaf9789c9a5106f7a4fccf6b7a23f0ca726ab545)
@@ -64,5 +64,5 @@
  *
  */
-NO_TRACE static inline uint64_t cpuid_read(int n)
+_NO_TRACE static inline uint64_t cpuid_read(int n)
 {
 	uint64_t v;
@@ -77,5 +77,5 @@
 }
 
-NO_TRACE static inline int ia64_get_cpu_id(void)
+_NO_TRACE static inline int ia64_get_cpu_id(void)
 {
 	uint64_t cr64 = cr64_read();
@@ -83,5 +83,5 @@
 }
 
-NO_TRACE static inline int ia64_get_cpu_eid(void)
+_NO_TRACE static inline int ia64_get_cpu_eid(void)
 {
 	uint64_t cr64 = cr64_read();
@@ -89,5 +89,5 @@
 }
 
-NO_TRACE static inline void ipi_send_ipi(int id, int eid, int intno)
+_NO_TRACE static inline void ipi_send_ipi(int id, int eid, int intno)
 {
 	(bootinfo->sapic)[2 * (id * 256 + eid)] = intno;
Index: kernel/arch/ia64/include/arch/cycle.h
===================================================================
--- kernel/arch/ia64/include/arch/cycle.h	(revision a01f7320d7baed06438e7cde66ccddacc299ba1d)
+++ kernel/arch/ia64/include/arch/cycle.h	(revision aaf9789c9a5106f7a4fccf6b7a23f0ca726ab545)
@@ -38,5 +38,5 @@
 #include <trace.h>
 
-NO_TRACE static inline uint64_t get_cycle(void)
+_NO_TRACE static inline uint64_t get_cycle(void)
 {
 	return 0;
Index: kernel/arch/ia64/include/arch/istate.h
===================================================================
--- kernel/arch/ia64/include/arch/istate.h	(revision a01f7320d7baed06438e7cde66ccddacc299ba1d)
+++ kernel/arch/ia64/include/arch/istate.h	(revision aaf9789c9a5106f7a4fccf6b7a23f0ca726ab545)
@@ -50,5 +50,5 @@
 #endif /* KERNEL */
 
-NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
+_NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     uintptr_t retaddr)
 {
@@ -57,10 +57,10 @@
 }
 
-NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate)
+_NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate)
 {
 	return istate->cr_iip;
 }
 
-NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate)
+_NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate)
 {
 	/* FIXME */
@@ -69,5 +69,5 @@
 }
 
-NO_TRACE static inline int istate_from_uspace(istate_t *istate)
+_NO_TRACE static inline int istate_from_uspace(istate_t *istate)
 {
 	return (istate->cr_iip) < 0xe000000000000000ULL;
Index: kernel/arch/ia64/include/arch/mm/page.h
===================================================================
--- kernel/arch/ia64/include/arch/mm/page.h	(revision a01f7320d7baed06438e7cde66ccddacc299ba1d)
+++ kernel/arch/ia64/include/arch/mm/page.h	(revision aaf9789c9a5106f7a4fccf6b7a23f0ca726ab545)
@@ -191,5 +191,5 @@
  * @return Address of the head of VHPT collision chain.
  */
-NO_TRACE static inline uint64_t thash(uint64_t va)
+_NO_TRACE static inline uint64_t thash(uint64_t va)
 {
 	uint64_t ret;
@@ -213,5 +213,5 @@
  * @return The unique tag for VPN and RID in the collision chain returned by thash().
  */
-NO_TRACE static inline uint64_t ttag(uint64_t va)
+_NO_TRACE static inline uint64_t ttag(uint64_t va)
 {
 	uint64_t ret;
@@ -232,5 +232,5 @@
  * @return Current contents of rr[i].
  */
-NO_TRACE static inline uint64_t rr_read(size_t i)
+_NO_TRACE static inline uint64_t rr_read(size_t i)
 {
 	uint64_t ret;
@@ -252,5 +252,5 @@
  * @param v Value to be written to rr[i].
  */
-NO_TRACE static inline void rr_write(size_t i, uint64_t v)
+_NO_TRACE static inline void rr_write(size_t i, uint64_t v)
 {
 	assert(i < REGION_REGISTERS);
@@ -267,5 +267,5 @@
  * @return Current value stored in PTA.
  */
-NO_TRACE static inline uint64_t pta_read(void)
+_NO_TRACE static inline uint64_t pta_read(void)
 {
 	uint64_t ret;
@@ -283,5 +283,5 @@
  * @param v New value to be stored in PTA.
  */
-NO_TRACE static inline void pta_write(uint64_t v)
+_NO_TRACE static inline void pta_write(uint64_t v)
 {
 	asm volatile (