Index: arch/mips/src/cpu/cpu.c
===================================================================
--- arch/mips/src/cpu/cpu.c	(revision f761f1eb635bfe9a5deaf70a0f0a51aa8d2f5f22)
+++ arch/mips/src/cpu/cpu.c	(revision aa9551d30eaa623e14ad0adb93951d69fccf962a)
@@ -84,6 +84,6 @@
 void cpu_identify(void)
 {
-	the->cpu->arch.rev_num = cp0_prid_read() & 0xff;
-	the->cpu->arch.imp_num = (cp0_prid_read() >> 8) & 0xff;
+	CPU->arch.rev_num = cp0_prid_read() & 0xff;
+	CPU->arch.imp_num = (cp0_prid_read() >> 8) & 0xff;
 }
 
Index: arch/mips/src/exception.c
===================================================================
--- arch/mips/src/exception.c	(revision f761f1eb635bfe9a5deaf70a0f0a51aa8d2f5f22)
+++ arch/mips/src/exception.c	(revision aa9551d30eaa623e14ad0adb93951d69fccf962a)
@@ -43,7 +43,7 @@
 	cp0_status_write(cp0_status_read() & ~ cp0_status_exl_exception_bit);
 
-	if (the->thread) {
-		the->thread->saved_pri = pri;
-		the->thread->saved_epc = epc;
+	if (THREAD) {
+		THREAD->saved_pri = pri;
+		THREAD->saved_epc = epc;
 	}
 	/* decode exception number and process the exception */
@@ -55,7 +55,7 @@
 	}
 	
-	if (the->thread) {
-		pri = the->thread->saved_pri;
-		epc = the->thread->saved_epc;
+	if (THREAD) {
+		pri = THREAD->saved_pri;
+		epc = THREAD->saved_epc;
 	}
 
Index: arch/mips/src/mm/tlb.c
===================================================================
--- arch/mips/src/mm/tlb.c	(revision f761f1eb635bfe9a5deaf70a0f0a51aa8d2f5f22)
+++ arch/mips/src/mm/tlb.c	(revision aa9551d30eaa623e14ad0adb93951d69fccf962a)
@@ -47,5 +47,5 @@
 void tlb_invalid(void)
 {
-	panic(PANIC "%X: TLB exception at %X", cp0_badvaddr_read(), the->thread ? the->thread->saved_epc : 0);
+	panic(PANIC "%X: TLB exception at %X", cp0_badvaddr_read(), THREAD ? THREAD->saved_epc : 0);
 }