Changeset aa85487 in mainline for kernel/arch/sparc64/include


Ignore:
Timestamp:
2010-03-07T15:11:56Z (16 years ago)
Author:
Lukas Mejdrech <lukasmejdrech@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/fix-logger-deadlock, topic/msim-upgrade, topic/simplify-dev-export
Children:
aadf01e
Parents:
2e99277 (diff), 137691a (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes, revision 308

Location:
kernel/arch/sparc64/include
Files:
5 added
20 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/include/atomic.h

    r2e99277 raa85487  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */
    … …  
    4545 *
    4646 * @param val Atomic variable.
    47  * @param i Signed value to be added.
     47 * @param i   Signed value to be added.
    4848 *
    4949 * @return Value of the atomic variable as it existed before addition.
     50 *
    5051 */
    51 static inline long atomic_add(atomic_t *val, int i)
     52static inline atomic_count_t atomic_add(atomic_t *val, atomic_count_t i)
    5253{
    53         uint64_t a, b;
    54 
     54        atomic_count_t a;
     55        atomic_count_t b;
     56       
    5557        do {
    56                 volatile uintptr_t x = (uint64_t) &val->count;
    57 
    58                 a = *((uint64_t *) x);
     58                volatile uintptr_t ptr = (uintptr_t) &val->count;
     59               
     60                a = *((atomic_count_t *) ptr);
    5961                b = a + i;
    60                 asm volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *)x)),
    61                     "+r" (b) : "r" (a));
     62               
     63                asm volatile (
     64                        "casx %0, %2, %1\n"
     65                        : "+m" (*((atomic_count_t *) ptr)),
     66                      "+r" (b)
     67                    : "r" (a)
     68                );
    6269        } while (a != b);
    63 
     70       
    6471        return a;
    6572}
    6673
    67 static inline long atomic_preinc(atomic_t *val)
     74static inline atomic_count_t atomic_preinc(atomic_t *val)
    6875{
    6976        return atomic_add(val, 1) + 1;
    7077}
    7178
    72 static inline long atomic_postinc(atomic_t *val)
     79static inline atomic_count_t atomic_postinc(atomic_t *val)
    7380{
    7481        return atomic_add(val, 1);
    7582}
    7683
    77 static inline long atomic_predec(atomic_t *val)
     84static inline atomic_count_t atomic_predec(atomic_t *val)
    7885{
    7986        return atomic_add(val, -1) - 1;
    8087}
    8188
    82 static inline long atomic_postdec(atomic_t *val)
     89static inline atomic_count_t atomic_postdec(atomic_t *val)
    8390{
    8491        return atomic_add(val, -1);
    … …  
    95102}
    96103
    97 static inline long test_and_set(atomic_t *val)
     104static inline atomic_count_t test_and_set(atomic_t *val)
    98105{
    99         uint64_t v = 1;
    100         volatile uintptr_t x = (uint64_t) &val->count;
    101 
    102         asm volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *) x)),
    103             "+r" (v) : "r" (0));
    104 
     106        atomic_count_t v = 1;
     107        volatile uintptr_t ptr = (uintptr_t) &val->count;
     108       
     109        asm volatile (
     110                "casx %0, %2, %1\n"
     111                : "+m" (*((atomic_count_t *) ptr)),
     112              "+r" (v)
     113            : "r" (0)
     114        );
     115       
    105116        return v;
    106117}
    … …  
    108119static inline void atomic_lock_arch(atomic_t *val)
    109120{
    110         uint64_t tmp1 = 1;
    111         uint64_t tmp2 = 0;
    112 
    113         volatile uintptr_t x = (uint64_t) &val->count;
    114 
     121        atomic_count_t tmp1 = 1;
     122        atomic_count_t tmp2 = 0;
     123       
     124        volatile uintptr_t ptr = (uintptr_t) &val->count;
     125       
    115126        preemption_disable();
    116 
     127       
    117128        asm volatile (
    118         "0:\n"
    119                 "casx %0, %3, %1\n"
    120                 "brz %1, 2f\n"
    121                 "nop\n"
    122         "1:\n"
    123                 "ldx %0, %2\n"
    124                 "brz %2, 0b\n"
    125                 "nop\n"
    126                 "ba %%xcc, 1b\n"
    127                 "nop\n"
    128         "2:\n"
    129                 : "+m" (*((uint64_t *) x)), "+r" (tmp1), "+r" (tmp2) : "r" (0)
     129                "0:\n"
     130                        "casx %0, %3, %1\n"
     131                        "brz %1, 2f\n"
     132                        "nop\n"
     133                "1:\n"
     134                        "ldx %0, %2\n"
     135                        "brz %2, 0b\n"
     136                        "nop\n"
     137                        "ba %%xcc, 1b\n"
     138                        "nop\n"
     139                "2:\n"
     140                : "+m" (*((atomic_count_t *) ptr)),
     141                  "+r" (tmp1),
     142                  "+r" (tmp2)
     143                : "r" (0)
    130144        );
    131145       

  • kernel/arch/sparc64/include/mm/as.h

    r2e99277 raa85487  
    3636#define KERN_sparc64_AS_H_
    3737
    38 #include <arch/mm/tte.h>
    39 
    40 #define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH      1
    41 
    42 #define KERNEL_ADDRESS_SPACE_START_ARCH         (unsigned long) 0x0000000000000000
    43 #define KERNEL_ADDRESS_SPACE_END_ARCH           (unsigned long) 0xffffffffffffffff
    44 #define USER_ADDRESS_SPACE_START_ARCH           (unsigned long) 0x0000000000000000
    45 #define USER_ADDRESS_SPACE_END_ARCH             (unsigned long) 0xffffffffffffffff
    46 
    47 #define USTACK_ADDRESS_ARCH     (0xffffffffffffffffULL - (PAGE_SIZE - 1))
    48 
    49 #ifdef CONFIG_TSB
    50 
    51 /** TSB Tag Target register. */
    52 typedef union tsb_tag_target {
    53         uint64_t value;
    54         struct {
    55                 unsigned invalid : 1;   /**< Invalidated by software. */
    56                 unsigned : 2;
    57                 unsigned context : 13;  /**< Software ASID. */
    58                 unsigned : 6;
    59                 uint64_t va_tag : 42;   /**< Virtual address bits <63:22>. */
    60         } __attribute__ ((packed));
    61 } tsb_tag_target_t;
    62 
    63 /** TSB entry. */
    64 typedef struct tsb_entry {
    65         tsb_tag_target_t tag;
    66         tte_data_t data;
    67 } __attribute__ ((packed)) tsb_entry_t;
    68 
    69 typedef struct {
    70         tsb_entry_t *itsb;
    71         tsb_entry_t *dtsb;
    72 } as_arch_t;
    73 
    74 #else
    75 
    76 typedef struct {
    77 } as_arch_t;
    78 
    79 #endif /* CONFIG_TSB */
    80 
    81 #include <genarch/mm/as_ht.h>
    82 
    83 #ifdef CONFIG_TSB
    84 #include <arch/mm/tsb.h>
    85 #define as_invalidate_translation_cache(as, page, cnt) \
    86         tsb_invalidate((as), (page), (cnt))
    87 #else
    88 #define as_invalidate_translation_cache(as, page, cnt)
     38#if defined (SUN4U)
     39#include <arch/mm/sun4u/as.h>
     40#elif defined (SUN4V)
     41#include <arch/mm/sun4v/as.h>
    8942#endif
    90 
    91 extern void as_arch_init(void);
    9243
    9344#endif

  • kernel/arch/sparc64/include/mm/sun4u/tlb.h

    r2e99277 raa85487  
    684684
    685685extern void dump_sfsr_and_sfar(void);
     686extern void describe_dmmu_fault(void);
    686687
    687688#endif /* !def __ASM__ */

  • kernel/arch/sparc64/include/mm/sun4v/frame.h

    r2e99277 raa85487  
    3333 */
    3434
    35 #ifndef KERN_sparc64_SUN4V_FRAME_H_
    36 #define KERN_sparc64_SUN4V_FRAME_H_
     35#ifndef KERN_sparc64_sun4v_FRAME_H_
     36#define KERN_sparc64_sun4v_FRAME_H_
    3737
    38 /*
    39  * Page size supported by the MMU.
    40  * For 8K there is the nasty illegal virtual aliasing problem.
    41  * Therefore, the kernel uses 8K only internally on the TLB and TSB levels.
    42  */
    4338#define MMU_FRAME_WIDTH         13      /* 8K */
    4439#define MMU_FRAME_SIZE          (1 << MMU_FRAME_WIDTH)
    … …  
    5247#include <arch/types.h>
    5348
    54 union frame_address {
    55         uintptr_t address;
    56         struct {
    57 #if defined (US)
    58                 unsigned : 23;
    59                 uint64_t pfn : 28;              /**< Physical Frame Number. */
    60 #elif defined (US3)
    61                 unsigned : 21;
    62                 uint64_t pfn : 30;              /**< Physical Frame Number. */
    63 #endif
    64                 unsigned offset : 13;           /**< Offset. */
    65         } __attribute__ ((packed));
    66 };
    67 
    68 typedef union frame_address frame_address_t;
    69 
    7049extern uintptr_t last_frame;
    71 //MH
    72 //extern uintptr_t end_of_identity;
    73 
    7450extern void frame_arch_init(void);
    7551#define physmem_print()

  • kernel/arch/sparc64/include/mm/sun4v/mmu.h

    r2e99277 raa85487  
    2828 */
    2929
    30 /** @addtogroup sparc64mm       
     30/** @addtogroup sparc64mm
    3131 * @{
    3232 */
    … …  
    4545#define ASI_SECONDARY_CONTEXT_REG       0x21    /**< secondary context register ASI. */
    4646
    47 
    48 
    49 
    50 
    51 
    52 
    53 
    54 
    55 
    56 
    57 /* I-MMU ASIs. */
    58 #define ASI_IMMU                        0x50
    59 #define ASI_IMMU_TSB_8KB_PTR_REG        0x51   
    60 #define ASI_IMMU_TSB_64KB_PTR_REG       0x52
    61 #define ASI_ITLB_DATA_IN_REG            0x54
    62 #define ASI_ITLB_DATA_ACCESS_REG        0x55
    63 #define ASI_ITLB_TAG_READ_REG           0x56
    64 #define ASI_IMMU_DEMAP                  0x57
    65 
    66 /* Virtual Addresses within ASI_IMMU. */
    67 #define VA_IMMU_TSB_TAG_TARGET          0x0     /**< IMMU TSB tag target register. */
    68 #define VA_IMMU_SFSR                    0x18    /**< IMMU sync fault status register. */
    69 #define VA_IMMU_TSB_BASE                0x28    /**< IMMU TSB base register. */
    70 #define VA_IMMU_TAG_ACCESS              0x30    /**< IMMU TLB tag access register. */
    71 #if defined (US3)
    72 #define VA_IMMU_PRIMARY_EXTENSION       0x48    /**< IMMU TSB primary extension register */
    73 #define VA_IMMU_NUCLEUS_EXTENSION       0x58    /**< IMMU TSB nucleus extension register */
    74 #endif
    75 
    76 
    77 /* D-MMU ASIs. */
    78 #define ASI_DMMU                        0x58
    79 #define ASI_DMMU_TSB_8KB_PTR_REG        0x59   
    80 #define ASI_DMMU_TSB_64KB_PTR_REG       0x5a
    81 #define ASI_DMMU_TSB_DIRECT_PTR_REG     0x5b
    82 #define ASI_DTLB_DATA_IN_REG            0x5c
    83 #define ASI_DTLB_DATA_ACCESS_REG        0x5d
    84 #define ASI_DTLB_TAG_READ_REG           0x5e
    85 #define ASI_DMMU_DEMAP                  0x5f
    86 
    87 /* Virtual Addresses within ASI_DMMU. */
    88 #define VA_DMMU_TSB_TAG_TARGET          0x0     /**< DMMU TSB tag target register. */
    89 #define VA_PRIMARY_CONTEXT_REG          0x8     /**< DMMU primary context register. */
    90 #define VA_SECONDARY_CONTEXT_REG        0x10    /**< DMMU secondary context register. */
    91 #define VA_DMMU_SFSR                    0x18    /**< DMMU sync fault status register. */
    92 #define VA_DMMU_SFAR                    0x20    /**< DMMU sync fault address register. */
    93 #define VA_DMMU_TSB_BASE                0x28    /**< DMMU TSB base register. */
    94 #define VA_DMMU_TAG_ACCESS              0x30    /**< DMMU TLB tag access register. */
    95 #define VA_DMMU_VA_WATCHPOINT_REG       0x38    /**< DMMU VA data watchpoint register. */
    96 #define VA_DMMU_PA_WATCHPOINT_REG       0x40    /**< DMMU PA data watchpoint register. */
    97 #if defined (US3)
    98 #define VA_DMMU_PRIMARY_EXTENSION       0x48    /**< DMMU TSB primary extension register */
    99 #define VA_DMMU_SECONDARY_EXTENSION     0x50    /**< DMMU TSB secondary extension register */
    100 #define VA_DMMU_NUCLEUS_EXTENSION       0x58    /**< DMMU TSB nucleus extension register */
    101 #endif
    102 
    103 #ifndef __ASM__
    104 
    105 #include <arch/asm.h>
    106 #include <arch/barrier.h>
    107 #include <arch/types.h>
    108 
    109 #if defined(US)
    110 /** LSU Control Register. */
    111 typedef union {
    112         uint64_t value;
    113         struct {
    114                 unsigned : 23;
    115                 unsigned pm : 8;
    116                 unsigned vm : 8;
    117                 unsigned pr : 1;
    118                 unsigned pw : 1;
    119                 unsigned vr : 1;
    120                 unsigned vw : 1;
    121                 unsigned : 1;
    122                 unsigned fm : 16;       
    123                 unsigned dm : 1;        /**< D-MMU enable. */
    124                 unsigned im : 1;        /**< I-MMU enable. */
    125                 unsigned dc : 1;        /**< D-Cache enable. */
    126                 unsigned ic : 1;        /**< I-Cache enable. */
    127                
    128         } __attribute__ ((packed));
    129 } lsu_cr_reg_t;
    130 #endif /* US */
    131 
    132 #endif /* !def __ASM__ */
    133 
    134 
    135 
    136 
    137 
    138 
    139 
    140 
    141 
    142 
    143 
    144 
    145 
    146 
    147 
    148 
    14947#endif
    15048

  • kernel/arch/sparc64/include/mm/sun4v/tlb.h

    r2e99277 raa85487  
    2828 */
    2929
    30 /** @addtogroup sparc64mm       
     30/** @addtogroup sparc64mm
    3131 * @{
    3232 */

  • kernel/arch/sparc64/include/mm/sun4v/tsb.h

    r2e99277 raa85487  
    2828 */
    2929
    30 /** @addtogroup sparc64mm       
     30/** @addtogroup sparc64mm
    3131 * @{
    3232 */
    … …  
    7171struct pte;
    7272
    73 extern void tsb_invalidate(struct as *as, uintptr_t page, count_t pages);
     73extern void tsb_invalidate(struct as *as, uintptr_t page, uint64_t pages);
    7474extern void itsb_pte_copy(struct pte *t);
    7575extern void dtsb_pte_copy(struct pte *t, bool ro);

  • kernel/arch/sparc64/include/mm/sun4v/tte.h

    r2e99277 raa85487  
    2727 */
    2828
    29 /** @addtogroup sparc64mm       
     29/** @addtogroup sparc64mm
    3030 * @{
    3131 */

  • kernel/arch/sparc64/include/mm/tlb.h

    r2e99277 raa85487  
    3636#define KERN_sparc64_TLB_H_
    3737
     38
    3839#if defined (SUN4U)
    3940#include <arch/mm/sun4u/tlb.h>

  • kernel/arch/sparc64/include/mm/tsb.h

    r2e99277 raa85487  
    3636#define KERN_sparc64_TSB_H_
    3737
    38 /*
    39  * ITSB abd DTSB will claim 64K of memory, which
    40  * is a nice number considered that it is one of
    41  * the page sizes supported by hardware, which,
    42  * again, is nice because TSBs need to be locked
    43  * in TLBs - only one TLB entry will do.
    44  */
    45 #define TSB_SIZE                        2       /* when changing this, change
    46                                                  * as.c as well */
    47 #define ITSB_ENTRY_COUNT                (512 * (1 << TSB_SIZE))
    48 #define DTSB_ENTRY_COUNT                (512 * (1 << TSB_SIZE))
    49 
    50 #define TSB_TAG_TARGET_CONTEXT_SHIFT    48
    51 
    52 #ifndef __ASM__
    53 
    54 #include <arch/mm/tte.h>
    55 #include <arch/mm/mmu.h>
    56 #include <arch/types.h>
    57 
    58 /** TSB Base register. */
    59 typedef union tsb_base_reg {
    60         uint64_t value;
    61         struct {
    62                 uint64_t base : 51;     /**< TSB base address, bits 63:13. */
    63                 unsigned split : 1;     /**< Split vs. common TSB for 8K and 64K
    64                                          * pages. HelenOS uses only 8K pages
    65                                          * for user mappings, so we always set
    66                                          * this to 0.
    67                                          */
    68                 unsigned : 9;
    69                 unsigned size : 3;      /**< TSB size. Number of entries is
    70                                          * 512 * 2^size. */
    71         } __attribute__ ((packed));
    72 } tsb_base_reg_t;
    73 
    74 /** Read ITSB Base register.
    75  *
    76  * @return Content of the ITSB Base register.
    77  */
    78 static inline uint64_t itsb_base_read(void)
    79 {
    80         return asi_u64_read(ASI_IMMU, VA_IMMU_TSB_BASE);
    81 }
    82 
    83 /** Read DTSB Base register.
    84  *
    85  * @return Content of the DTSB Base register.
    86  */
    87 static inline uint64_t dtsb_base_read(void)
    88 {
    89         return asi_u64_read(ASI_DMMU, VA_DMMU_TSB_BASE);
    90 }
    91 
    92 /** Write ITSB Base register.
    93  *
    94  * @param v New content of the ITSB Base register.
    95  */
    96 static inline void itsb_base_write(uint64_t v)
    97 {
    98         asi_u64_write(ASI_IMMU, VA_IMMU_TSB_BASE, v);
    99 }
    100 
    101 /** Write DTSB Base register.
    102  *
    103  * @param v New content of the DTSB Base register.
    104  */
    105 static inline void dtsb_base_write(uint64_t v)
    106 {
    107         asi_u64_write(ASI_DMMU, VA_DMMU_TSB_BASE, v);
    108 }
    109 
    110 #if defined (US3)
    111 
    112 /** Write DTSB Primary Extension register.
    113  *
    114  * @param v New content of the DTSB Primary Extension register.
    115  */
    116 static inline void dtsb_primary_extension_write(uint64_t v)
    117 {
    118         asi_u64_write(ASI_DMMU, VA_DMMU_PRIMARY_EXTENSION, v);
    119 }
    120 
    121 /** Write DTSB Secondary Extension register.
    122  *
    123  * @param v New content of the DTSB Secondary Extension register.
    124  */
    125 static inline void dtsb_secondary_extension_write(uint64_t v)
    126 {
    127         asi_u64_write(ASI_DMMU, VA_DMMU_SECONDARY_EXTENSION, v);
    128 }
    129 
    130 /** Write DTSB Nucleus Extension register.
    131  *
    132  * @param v New content of the DTSB Nucleus Extension register.
    133  */
    134 static inline void dtsb_nucleus_extension_write(uint64_t v)
    135 {
    136         asi_u64_write(ASI_DMMU, VA_DMMU_NUCLEUS_EXTENSION, v);
    137 }
    138 
    139 /** Write ITSB Primary Extension register.
    140  *
    141  * @param v New content of the ITSB Primary Extension register.
    142  */
    143 static inline void itsb_primary_extension_write(uint64_t v)
    144 {
    145         asi_u64_write(ASI_IMMU, VA_IMMU_PRIMARY_EXTENSION, v);
    146 }
    147 
    148 /** Write ITSB Nucleus Extension register.
    149  *
    150  * @param v New content of the ITSB Nucleus Extension register.
    151  */
    152 static inline void itsb_nucleus_extension_write(uint64_t v)
    153 {
    154         asi_u64_write(ASI_IMMU, VA_IMMU_NUCLEUS_EXTENSION, v);
    155 }
    156 
     38#if defined (SUN4U)
     39#include <arch/mm/sun4u/tsb.h>
     40#elif defined (SUN4V)
     41#include <arch/mm/sun4v/tsb.h>
    15742#endif
    158 
    159 /* Forward declarations. */
    160 struct as;
    161 struct pte;
    162 
    163 extern void tsb_invalidate(struct as *as, uintptr_t page, size_t pages);
    164 extern void itsb_pte_copy(struct pte *t, size_t index);
    165 extern void dtsb_pte_copy(struct pte *t, size_t index, bool ro);
    166 
    167 #endif /* !def __ASM__ */
    16843
    16944#endif

  • kernel/arch/sparc64/include/sun4v/arch.h

    r2e99277 raa85487  
    5858#define SCRATCHPAD_WBUF         0x18
    5959
    60 //MH - remove when cpu.h is forked
    61 #define ASI_NUCLEUS_QUAD_LDD    0x24    /** ASI for 16-byte atomic loads. */
    62 #define ASI_DCACHE_TAG          0x47    /** ASI D-Cache Tag. */
    63 #define ASI_ICBUS_CONFIG        0x4a    /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */
    64 
    6560#endif
    6661

  • kernel/arch/sparc64/include/sun4v/cpu.h

    r2e99277 raa85487  
    4444#ifndef __ASM__
    4545
     46#include <atomic.h>
     47#include <synch/spinlock.h>
     48
    4649struct cpu;
    4750
    48 /*
    4951typedef struct {
    5052        uint64_t exec_unit_id;
    … …  
    5557        SPINLOCK_DECLARE(proposed_nrdy_lock);
    5658} exec_unit_t;
    57 */
    5859
    5960typedef struct cpu_arch {
    … …  
    6364                                             generated when the TICK register
    6465                                             matches this value. */
    65         //exec_unit_t *exec_unit;               /**< Physical core. */
    66         //unsigned long proposed_nrdy;  /**< Proposed No. of ready threads
    67         //                                   so that cores are equally balanced. */
     66        exec_unit_t *exec_unit;         /**< Physical core. */
     67        unsigned long proposed_nrdy;    /**< Proposed No. of ready threads
     68                                             so that cores are equally balanced. */
    6869} cpu_arch_t;
    6970

  • kernel/arch/sparc64/include/sun4v/hypercall.h

    r2e99277 raa85487  
    7575
    7676/* return codes */
    77 #define EOK             0       /**< Successful return */
    78 #define ENOCPU          1       /**< Invalid CPU id */
    79 #define ENORADDR        2       /**< Invalid real address */
    80 #define ENOINTR         3       /**< Invalid interrupt id */
    81 #define EBADPGSZ        4       /**< Invalid pagesize encoding */
    82 #define EBADTSB         5       /**< Invalid TSB description */
    83 #define EINVAL          6       /**< Invalid argument */
    84 #define EBADTRAP        7       /**< Invalid function number */
    85 #define EBADALIGN       8       /**< Invalid address alignment */
    86 #define EWOULDBLOCK     9       /**< Cannot complete operation without blocking */
    87 #define ENOACCESS       10      /**< No access to specified resource */
    88 #define EIO             11      /**< I/O Error */
    89 #define ECPUERROR       12      /**< CPU is in error state */
    90 #define ENOTSUPPORTED   13      /**< Function not supported */
    91 #define ENOMAP          14      /**< No mapping found */
    92 #define ETOOMANY        15      /**< Too many items specified / limit reached */
    93 #define ECHANNEL        16      /**< Invalid LDC channel */
    94 #define EBUSY           17      /**< Operation failed as resource is otherwise busy */
     77#define HV_EOK                  0       /**< Successful return */
     78#define HV_ENOCPU               1       /**< Invalid CPU id */
     79#define HV_ENORADDR             2       /**< Invalid real address */
     80#define HV_ENOINTR              3       /**< Invalid interrupt id */
     81#define HV_EBADPGSZ             4       /**< Invalid pagesize encoding */
     82#define HV_EBADTSB              5       /**< Invalid TSB description */
     83#define HV_EINVAL               6       /**< Invalid argument */
     84#define HV_EBADTRAP             7       /**< Invalid function number */
     85#define HV_EBADALIGN            8       /**< Invalid address alignment */
     86#define HV_EWOULDBLOCK          9       /**< Cannot complete operation without blocking */
     87#define HV_ENOACCESS            10      /**< No access to specified resource */
     88#define HV_EIO                  11      /**< I/O Error */
     89#define HV_ECPUERROR            12      /**< CPU is in error state */
     90#define HV_ENOTSUPPORTED        13      /**< Function not supported */
     91#define HV_ENOMAP               14      /**< No mapping found */
     92#define HV_ETOOMANY             15      /**< Too many items specified / limit reached */
     93#define HV_ECHANNEL             16      /**< Invalid LDC channel */
     94#define HV_EBUSY                17      /**< Operation failed as resource is otherwise busy */
    9595
    9696
    … …  
    190190__hypercall_fast_ret1(const uint64_t p1, const uint64_t p2, const uint64_t p3,
    191191    const uint64_t p4, const uint64_t p5, const uint64_t function_number,
    192     uint64_t * const ret1)
     192    uint64_t *ret1)
    193193{
    194         uint64_t errno = __hypercall_fast(p1, p2, p3, p4, p5, function_number);
    195         if (ret1 != NULL) {
    196                 asm volatile ("mov %%o1, %0\n" : "=r" (*ret1));
    197         }
    198         return errno;
     194        register uint64_t a6 asm("o5") = function_number;
     195        register uint64_t a1 asm("o0") = p1;
     196        register uint64_t a2 asm("o1") = p2;
     197        register uint64_t a3 asm("o2") = p3;
     198        register uint64_t a4 asm("o3") = p4;
     199        register uint64_t a5 asm("o4") = p5;
     200       
     201        asm volatile (
     202                "ta %8\n"
     203                : "=r" (a1), "=r" (a2)
     204                : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6),
     205                  "i" (FAST_TRAP)
     206                : "memory"
     207        );
     208
     209        if (ret1)
     210                *ret1 = a2;
     211
     212        return a1;
    199213}
    200214

  • kernel/arch/sparc64/include/sun4v/ipi.h

    r2e99277 raa85487  
    3838#define KERN_sparc64_sun4v_IPI_H_
    3939
    40 uint64_t ipi_brodcast_to(void (*func)(void), uint16_t cpu_list[MAX_NUM_STRANDS],
    41                 uint64_t list_size);
    42 uint64_t ipi_unicast_to(void (*func)(void), uint16_t cpu_id);
     40#include <arch/types.h>
     41
     42extern uint64_t ipi_brodcast_to(void (*)(void), uint16_t cpu_list[], uint64_t);
     43extern uint64_t ipi_unicast_to(void (*)(void), uint16_t);
    4344
    4445#endif

  • kernel/arch/sparc64/include/trap/exception.h

    r2e99277 raa85487  
    3838
    3939#define TT_INSTRUCTION_ACCESS_EXCEPTION         0x08
     40#define TT_INSTRUCTION_ACCESS_MMU_MISS          0x09
    4041#define TT_INSTRUCTION_ACCESS_ERROR             0x0a
     42#define TT_IAE_UNAUTH_ACCESS                    0x0b
     43#define TT_IAE_NFO_PAGE                         0x0c
    4144#define TT_ILLEGAL_INSTRUCTION                  0x10
    4245#define TT_PRIVILEGED_OPCODE                    0x11
    4346#define TT_UNIMPLEMENTED_LDD                    0x12
    4447#define TT_UNIMPLEMENTED_STD                    0x13
     48#define TT_DAE_INVALID_ASI                      0x14
     49#define TT_DAE_PRIVILEGE_VIOLATION              0x15
     50#define TT_DAE_NC_PAGE                          0x16
     51#define TT_DAE_NFO_PAGE                         0x17
    4552#define TT_FP_DISABLED                          0x20
    4653#define TT_FP_EXCEPTION_IEEE_754                0x21
    … …  
    4956#define TT_DIVISION_BY_ZERO                     0x28
    5057#define TT_DATA_ACCESS_EXCEPTION                0x30
     58#define TT_DATA_ACCESS_MMU_MISS                 0x31
    5159#define TT_DATA_ACCESS_ERROR                    0x32
    5260#define TT_MEM_ADDRESS_NOT_ALIGNED              0x34

  • kernel/arch/sparc64/include/trap/interrupt.h

    r2e99277 raa85487  
    3232/**
    3333 * @file
    34  * @brief This file contains interrupt vector trap handler.
     34 * @brief This file contains level N interrupt and inter-processor interrupt
     35 * trap handler.
    3536 */
    36 
    37 #ifndef KERN_sparc64_TRAP_INTERRUPT_H_
    38 #define KERN_sparc64_TRAP_INTERRUPT_H_
    39 
    40 #include <arch/trap/trap_table.h>
    41 #include <arch/stack.h>
    42 
    43 /* IMAP register bits */
    44 #define IGN_MASK        0x7c0
    45 #define INO_MASK        0x1f
    46 #define IMAP_V_MASK     (1ULL << 31)
    47 
    48 #define IGN_SHIFT       6
    49 
    50 
    51 /* Interrupt ASI registers. */
    52 #define ASI_INTR_W                      0x77
    53 #define ASI_INTR_DISPATCH_STATUS        0x48
    54 #define ASI_INTR_R                      0x7f
    55 #define ASI_INTR_RECEIVE                0x49
    56 
    57 /* VA's used with ASI_INTR_W register. */
    58 #if defined (US)
    59 #define ASI_UDB_INTR_W_DATA_0   0x40
    60 #define ASI_UDB_INTR_W_DATA_1   0x50
    61 #define ASI_UDB_INTR_W_DATA_2   0x60
    62 #elif defined (US3)
    63 #define VA_INTR_W_DATA_0        0x40
    64 #define VA_INTR_W_DATA_1        0x48
    65 #define VA_INTR_W_DATA_2        0x50
    66 #define VA_INTR_W_DATA_3        0x58
    67 #define VA_INTR_W_DATA_4        0x60
    68 #define VA_INTR_W_DATA_5        0x68
    69 #define VA_INTR_W_DATA_6        0x80
    70 #define VA_INTR_W_DATA_7        0x88
    71 #endif
    72 #define VA_INTR_W_DISPATCH      0x70
    73 
    74 /* VA's used with ASI_INTR_R register. */
    75 #if defined(US)
    76 #define ASI_UDB_INTR_R_DATA_0   0x40
    77 #define ASI_UDB_INTR_R_DATA_1   0x50
    78 #define ASI_UDB_INTR_R_DATA_2   0x60
    79 #elif defined (US3)
    80 #define VA_INTR_R_DATA_0        0x40
    81 #define VA_INTR_R_DATA_1        0x48
    82 #define VA_INTR_R_DATA_2        0x50
    83 #define VA_INTR_R_DATA_3        0x58
    84 #define VA_INTR_R_DATA_4        0x60
    85 #define VA_INTR_R_DATA_5        0x68
    86 #define VA_INTR_R_DATA_6        0x80
    87 #define VA_INTR_R_DATA_7        0x88
    88 #endif
    89 
    90 /* Shifts in the Interrupt Vector Dispatch virtual address. */
    91 #define INTR_VEC_DISPATCH_MID_SHIFT     14
    92 
    93 /* Bits in the Interrupt Dispatch Status register. */
    94 #define INTR_DISPATCH_STATUS_NACK       0x2
    95 #define INTR_DISPATCH_STATUS_BUSY       0x1
     37#ifndef KERN_sparc64_INTERRUPT_TRAP_H_
     38#define KERN_sparc64_INTERRUPT_TRAP_H_
    9639
    9740#define TT_INTERRUPT_LEVEL_1                    0x41
    … …  
    11154#define TT_INTERRUPT_LEVEL_15                   0x4f
    11255
    113 #define TT_INTERRUPT_VECTOR_TRAP                0x60
     56#define INTERRUPT_LEVEL_N_HANDLER_SIZE          TRAP_TABLE_ENTRY_SIZE
    11457
    115 #define INTERRUPT_LEVEL_N_HANDLER_SIZE          TRAP_TABLE_ENTRY_SIZE
    116 #define INTERRUPT_VECTOR_TRAP_HANDLER_SIZE      TRAP_TABLE_ENTRY_SIZE
     58/* IMAP register bits */
     59#define IGN_MASK        0x7c0
     60#define INO_MASK        0x1f
     61#define IMAP_V_MASK     (1ULL << 31)
     62
     63#define IGN_SHIFT       6
     64
    11765
    11866#ifdef __ASM__
    … …  
    12169        PREEMPTIBLE_HANDLER exc_dispatch
    12270.endm
    123 
    124 .macro INTERRUPT_VECTOR_TRAP_HANDLER
    125         PREEMPTIBLE_HANDLER interrupt
    126 .endm
    127 #endif /* __ASM__ */
     71#endif
    12872
    12973#ifndef __ASM__
    … …  
    13478#endif /* !def __ASM__ */
    13579
     80
     81#if defined (SUN4U)
     82#include <arch/trap/sun4u/interrupt.h>
     83#elif defined (SUN4V)
     84#include <arch/trap/sun4v/interrupt.h>
     85#endif
     86
    13687#endif
    13788

  • kernel/arch/sparc64/include/trap/regwin.h

    r2e99277 raa85487  
    183183        add %l0, 1, %l0
    184184        wrpr %l0, 0, %cleanwin
     185#if defined(SUN4U)
    185186        mov %r0, %l0
    186187        mov %r0, %l1
    … …  
    199200        mov %r0, %o6
    200201        mov %r0, %o7
     202#endif
    201203        retry
    202204.endm
    203205#endif /* __ASM__ */
    204206
    205 #if defined (SUN4U)
     207#if defined(SUN4U)
    206208#include <arch/trap/sun4u/regwin.h>
    207 #elif defined (SUN4V)
     209#elif defined(SUN4V)
    208210#include <arch/trap/sun4v/regwin.h>
    209211#endif

  • kernel/arch/sparc64/include/trap/sun4v/mmu.h

    r2e99277 raa85487  
    3636 */
    3737
    38 #ifndef KERN_sparc64_SUN4V_MMU_TRAP_H_
    39 #define KERN_sparc64_SUN4V_MMU_TRAP_H_
     38#ifndef KERN_sparc64_sun4v_MMU_TRAP_H_
     39#define KERN_sparc64_sun4v_MMU_TRAP_H_
    4040
    4141#include <arch/stack.h>
    … …  
    121121         * but this time its handler accesse memory which IS mapped.
    122122         */
    123 0:
    124 .if (\tl > 0)
    125         wrpr %g0, 1, %tl
    126 .endif
     123        .if (\tl > 0)
     124                wrpr %g0, 1, %tl
     125        .endif
    127126
    128127        /*

  • kernel/arch/sparc64/include/trap/trap_table.h

    r2e99277 raa85487  
    101101.macro PREEMPTIBLE_HANDLER f
    102102        sethi %hi(\f), %g1
    103         ba %xcc, preemptible_handler
     103        b preemptible_handler
    104104        or %g1, %lo(\f), %g1
    105105.endm

  • kernel/arch/sparc64/include/types.h

    r2e99277 raa85487  
    2727 */
    2828
    29 /** @addtogroup sparc64 
     29/** @addtogroup sparc64
    3030 * @{
    3131 */
    … …  
    5555typedef uint64_t unative_t;
    5656typedef int64_t native_t;
     57typedef uint64_t atomic_count_t;
    5758
    5859typedef struct {
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