Index: arch/mips32/src/mm/tlb.c
===================================================================
--- arch/mips32/src/mm/tlb.c	(revision 7910cffd4851e0ac56b045bf13deddbae09ae9ee)
+++ arch/mips32/src/mm/tlb.c	(revision a98d2ecd2f9c6faa76d404cc92cbe2f4e82f6279)
@@ -56,19 +56,8 @@
 void tlb_arch_init(void)
 {
-	int i;
-
 	cp0_pagemask_write(TLB_PAGE_MASK_16K);
-	cp0_entry_hi_write(0);
-	cp0_entry_lo0_write(0);
-	cp0_entry_lo1_write(0);
-
-	/*
-	 * Invalidate all entries.
-	 */
-	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
-		cp0_index_write(i);
-		tlbwi();
-	}
-	
+
+	tlb_invalidate_all();
+		
 	/*
 	 * The kernel is going to make use of some wired
@@ -410,5 +399,4 @@
 	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
 		cp0_index_write(i);
-
 		tlbr();
 		
@@ -423,2 +411,64 @@
 	}
 }
+
+/** Invalidate all TLB entries. */
+void tlb_invalidate_all(void)
+{
+	int i;
+
+	cp0_entry_hi_write(0);
+	cp0_entry_lo0_write(0);
+	cp0_entry_lo1_write(0);
+
+	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
+		cp0_index_write(i);
+		tlbwi();
+	}
+}
+
+/** Invalidate all TLB entries belonging to specified address space.
+ *
+ * @param asid Address space identifier.
+ */
+void tlb_invalidate_asid(asid_t asid)
+{
+	entry_hi_t hi;
+	int i;
+
+	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
+		cp0_index_write(i);
+		tlbr();
+		
+		if (hi.asid == asid) {
+			cp0_entry_lo0_write(0);
+			cp0_entry_lo1_write(0);
+			tlbwi();
+		}
+	}
+
+}
+
+/** Invalidate TLB entry for specified page belonging to specified address space.
+ *
+ * @param asid Address space identifier.
+ * @param page Page whose TLB entry is to be invalidated.
+ */
+void tlb_invalidate_page(asid_t asid, __address page)
+{
+	entry_hi_t hi;
+	tlb_index_t index;
+	int i;
+
+	hi.value = 0;
+	prepare_entry_hi(&hi, asid, page);
+	
+	tlbp();
+	index.value = cp0_index_read();
+
+	if (!index.p) {
+		/* Entry was found, index register contains valid index. */
+		cp0_entry_lo0_write(0);
+		cp0_entry_lo1_write(0);
+		tlbwi();
+	}
+}