Index: uspace/drv/ehci-hcd/pci.c
===================================================================
--- uspace/drv/ehci-hcd/pci.c	(revision d394e57ac30ff4616bf4b935c8ec68654a2f3192)
+++ uspace/drv/ehci-hcd/pci.c	(revision a948c2387cc16e9d919a3893aa3ec79ea6683c58)
@@ -54,5 +54,6 @@
 
 #define CMD_OFFSET 0x0
-#define CONFIGFLAG_OFFSET 0x40
+#define STS_OFFSET 0x4
+#define CFG_OFFSET 0x40
 
 #define USBCMD_RUN 1
@@ -264,7 +265,7 @@
 	 * It would prevent pre-OS code from interfering. */
 	ret = async_req_3_0(parent_phone, DEV_IFACE_ID(PCI_DEV_IFACE),
-	   IPC_M_CONFIG_SPACE_WRITE_32, eecp + USBLEGCTLSTS_OFFSET, 0);
+	   IPC_M_CONFIG_SPACE_WRITE_32, eecp + USBLEGCTLSTS_OFFSET,
+	   0xe0000000);
 	CHECK_RET_HANGUP_RETURN(ret, "Failed(%d) zero USBLEGCTLSTS.\n", ret);
-	usb_log_debug("Zeroed USBLEGCTLSTS register.\n");
 
 	/* Read again Legacy Support and Control register */
@@ -291,15 +292,20 @@
 	volatile uint32_t *usbcmd =
 	    (uint32_t*)((uint8_t*)registers + operation_offset + CMD_OFFSET);
+	volatile uint32_t *usbsts =
+	    (uint32_t*)((uint8_t*)registers + operation_offset + STS_OFFSET);
 	volatile uint32_t *usbconfigured =
-	    (uint32_t*)((uint8_t*)registers + operation_offset
-	    + CONFIGFLAG_OFFSET);
+	    (uint32_t*)((uint8_t*)registers + operation_offset + CFG_OFFSET);
 	usb_log_debug("USBCMD value: %x.\n", *usbcmd);
 	if (*usbcmd & USBCMD_RUN) {
 		*usbcmd = 0;
-		*usbconfigured = 0;
+		while (!(*usbsts & (1 << 12))); /*wait until hc is halted */
+		*usbcmd = 0x2; /* reset */
+		while (*usbcmd & 0x2); /* wait for reset to complete */
 		usb_log_info("EHCI turned off.\n");
 	} else {
 		usb_log_info("EHCI was not running.\n");
 	}
+	usb_log_debug("Registers: %x(0x00080000):%x(0x00001000):%x(0x0).\n",
+	    *usbcmd, *usbsts, *usbconfigured);
 
 	async_hangup(parent_phone);