Changes in / [f3386d7:a940f1d] in mainline


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Files:
2 deleted
8 edited

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  • boot/arch/arm32/src/asm.S

    rf3386d7 ra940f1d  
    7171        mrc     p15, 0, r4, c1, c0, 0
    7272        bic     r4, r4, #(1 << CP15_C1_DC)
    73 #ifndef PROCESSOR_ARCH_armv7_a
    7473        bic     r4, r4, #(1 << CP15_C1_IC)
    7574        bic     r4, r4, #(1 << CP15_C1_BP)
    76 #endif
    7775        mcr     p15, 0, r4, c1, c0, 0
    7876

  • boot/arch/arm32/src/main.c

    rf3386d7 ra940f1d  
    6363{
    6464        const uintptr_t addr = (uintptr_t)address;
     65        /* DCIMVAC - invalidate by address to the point of coherence */
    6566        for (uintptr_t a = addr; a < addr + size; a += 4) {
    66                 /* DCIMVAC - invalidate by address to the point of coherence */
    6767                asm volatile ("mcr p15, 0, %[a], c7, c6, 1\n" :: [a]"r"(a) : );
    6868        }
    … …  
    7272{
    7373        const uintptr_t addr = (uintptr_t)address;
     74        /* DCCMVAC - clean by address to the point of coherence */
    7475        for (uintptr_t a = addr; a < addr + size; a += 4) {
    75                 /* DCCMVAC - clean by address to the point of coherence */
    7676                asm volatile ("mcr p15, 0, %[a], c7, c10, 1\n" :: [a]"r"(a) : );
    7777        }
    … …  
    8282void bootstrap(void)
    8383{
    84         /* Make sure we run in memory code when caches are enabled,
     84        /* Make sure  we run in memory code when caches are enabled,
    8585         * make sure we read memory data too. This part is ARMv7 specific as
    8686         * ARMv7 no longer invalidates caches on restart.
    … …  
    105105                    components[i].start, components[i].name, components[i].inflated,
    106106                    components[i].size);
    107                 /* Make sure there is no cache garbage in read locations */
    108107                invalidate_dcache(components[i].start, components[i].size);
    109108        }
    … …  
    149148                        halt();
    150149                }
    151                 /* Make sure data are in the memory, ICache will need them */
    152150                clean_dcache_poc(dest[i - 1], components[i - 1].inflated);
    153151        }

  • kernel/arch/arm32/include/arch/asm.h

    rf3386d7 ra940f1d  
    3838
    3939#include <typedefs.h>
    40 #include <arch/cp15.h>
    4140#include <arch/stack.h>
    4241#include <config.h>
    … …  
    5251 * chapter 2.3.8 p.2-22 (52 in the PDF)
    5352 *
    54  * @note Although CP15WFI (mcr p15, 0, R0, c7, c0, 4) is defined in ARM
    55  * Architecture reference manual for armv4/5, CP15 implementation is mandatory
    56  * only for armv6+.
     53 * @note Although mcr p15, 0, R0, c7, c0, 4 is defined in ARM Architecture
     54 * reference manual for armv4/5 CP15 implementation is mandatory only for
     55 * armv6+.
    5756 */
    5857NO_TRACE static inline void cpu_sleep(void)
    … …  
    6160        asm volatile ( "wfe" );
    6261#elif defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_arm926ej_s) | defined(PROCESSOR_arm920t)
    63         WFI_write(0);
     62        asm volatile ( "mcr p15, 0, R0, c7, c0, 4" );
    6463#endif
    6564}

  • kernel/arch/arm32/include/arch/mm/page_armv4.h

    rf3386d7 ra940f1d  
    4141#error "Do not include arch specific page.h directly use generic page.h instead"
    4242#endif
    43 
    44 #include <arch/cp15.h>
    4543
    4644/* Macros for querying the last-level PTE entries. */
    … …  
    130128NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
    131129{
    132         TTBR0_write((uint32_t)pt);
     130        asm volatile (
     131                "mcr p15, 0, %[pt], c2, c0, 0\n"
     132                :: [pt] "r" (pt)
     133        );
    133134}
    134135
    … …  
    222223       
    223224        /* default access permission */
    224         p->access_permission_0 = p->access_permission_1 =
     225        p->access_permission_0 = p->access_permission_1 = 
    225226            p->access_permission_2 = p->access_permission_3 =
    226227            PTE_AP_USER_NO_KERNEL_RW;
    … …  
    228229        if (flags & PAGE_USER)  {
    229230                if (flags & PAGE_READ) {
    230                         p->access_permission_0 = p->access_permission_1 =
    231                             p->access_permission_2 = p->access_permission_3 =
     231                        p->access_permission_0 = p->access_permission_1 = 
     232                            p->access_permission_2 = p->access_permission_3 = 
    232233                            PTE_AP_USER_RO_KERNEL_RW;
    233234                }
    234235                if (flags & PAGE_WRITE) {
    235                         p->access_permission_0 = p->access_permission_1 =
    236                             p->access_permission_2 = p->access_permission_3 =
    237                             PTE_AP_USER_RW_KERNEL_RW;
     236                        p->access_permission_0 = p->access_permission_1 = 
     237                            p->access_permission_2 = p->access_permission_3 = 
     238                            PTE_AP_USER_RW_KERNEL_RW; 
    238239                }
    239240        }

  • kernel/arch/arm32/include/arch/mm/page_armv6.h

    rf3386d7 ra940f1d  
    4040#error "Do not include arch specific page.h directly use generic page.h instead"
    4141#endif
    42 
    43 #include <arch/cp15.h>
    4442
    4543/* Macros for querying the last-level PTE entries. */
    … …  
    134132NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
    135133{
    136         TTBR0_write((uint32_t)pt);
     134        asm volatile (
     135                "mcr p15, 0, %[pt], c2, c0, 0\n"
     136                :: [pt] "r" (pt)
     137        );
    137138}
    138139

  • kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c

    rf3386d7 ra940f1d  
    8585static void bb_timer_irq_handler(irq_t *irq)
    8686{
    87         amdm37x_gpt_irq_ack(&beagleboard.timer);
    88 
    8987        /*
    9088         * We are holding a lock which prevents preemption.
    9189         * Release the lock, call clock() and reacquire the lock again.
    9290         */
     91        amdm37x_gpt_irq_ack(&beagleboard.timer);
    9392        spinlock_unlock(&irq->lock);
    9493        clock();
    … …  
    148147{
    149148        const unsigned inum = amdm37x_irc_inum_get(beagleboard.irc_addr);
     149        amdm37x_irc_irq_ack(beagleboard.irc_addr);
    150150
    151151        irq_t *irq = irq_dispatch_and_lock(inum);
    … …  
    159159                    CPU->id, inum);
    160160        }
    161         /** amdm37x manual ch. 12.5.2 (p. 2428) places irc ack at the end
    162          * of ISR. DO this to avoid strange behavior. */
    163         amdm37x_irc_irq_ack(beagleboard.irc_addr);
    164161}
    165162

  • kernel/arch/arm32/src/mm/tlb.c

    rf3386d7 ra940f1d  
    3737#include <arch/mm/asid.h>
    3838#include <arch/asm.h>
    39 #include <arch/cp15.h>
    4039#include <typedefs.h>
    4140#include <arch/mm/page.h>
    … …  
    4746void tlb_invalidate_all(void)
    4847{
    49         TLBIALL_write(0);
     48        asm volatile (
     49                "eor r1, r1\n"
     50                "mcr p15, 0, r1, c8, c7, 0\n"
     51                ::: "r1"
     52        );
    5053}
    5154
    … …  
    5760{
    5861        tlb_invalidate_all();
    59         // TODO: why not TLBIASID_write(asid) ?
    6062}
    6163
    … …  
    6365 *
    6466 * @param page Virtual adress of the page
    65  */
     67 */ 
    6668static inline void invalidate_page(uintptr_t page)
    6769{
    68         TLBIMVA_write(page);
    69         //TODO: What about TLBIMVAA?
     70        asm volatile (
     71                "mcr p15, 0, %[page], c8, c7, 1\n"
     72                :: [page] "r" (page)
     73        );
    7074}
    7175

  • kernel/genarch/include/genarch/drivers/amdm37x/gpt.h

    rf3386d7 ra940f1d  
    3939#include <typedefs.h>
    4040#include <mm/km.h>
    41 #include <time/clock.h>
    4241
    4342/* AMDM37x TRM p. 2740 */
    … …  
    129128#define AMDM37x_GPT_TCLR_CE_FLAG  (1 << 6)
    130129#define AMDM37x_GPT_TCLR_SCPWM  (1 << 7)
    131 #define AMDM37x_GPT_TCLR_TCM_MASK  (0x3 << 8)
    132 #define AMDM37x_GPT_TCLR_TCM_NO_CAPTURE   (0x0 << 8)
    133 #define AMDM37x_GPT_TCLR_TCM_RAISE_CAPTURE   (0x1 << 8)
    134 #define AMDM37x_GPT_TCLR_TCM_FALL_CAPTURE   (0x2 << 8)
    135 #define AMDM37x_GPT_TCLR_TCM_BOTH_CAPTURE   (0x3 << 8)
    136 #define AMDM37x_GPT_TCLR_TRG_MASK  (0x3 << 10)
    137 #define AMDM37x_GPT_TCLR_TRG_NO  (0x0 << 10)
    138 #define AMDM37x_GPT_TCLR_TRG_OVERFLOW  (0x1 << 10)
    139 #define AMDM37x_GPT_TCLR_TRG_OVERMATCH  (0x2 << 10)
     130#define AMDM37x_GPT_TCLR_TCM_MASK  (0x3)
     131#define AMDM37x_GPT_TCLR_TCM_SHIFT  (8)
     132#define AMDM37x_GPT_TCLR_TRG_MASK  (0x3)
     133#define AMDM37x_GPT_TCLR_TRG_SHIFT (10)
    140134#define AMDM37x_GPT_TCLR_PT_FLAG  (1 << 12)
    141135#define AMDM37x_GPT_TCLR_CAPT_MODE_FLAG  (1 << 13)
    … …  
    215209        timer->regs = (void*) km_map(ioregs, iosize, PAGE_NOT_CACHEABLE);
    216210
    217         /* Reset the timer */
    218         timer->regs->tiocp_cfg |= AMDM37x_GPT_TIOCP_CFG_SOFTRESET_FLAG;
    219 
    220         while (timer->regs->tistat & AMDM37x_GPT_TISTAT_RESET_DONE_FLAG);
    221 
    222211        /* Set autoreload */
    223         timer->regs->tclr |= AMDM37x_GPT_TCLR_AR_FLAG;
     212        timer->regs->tclr = AMDM37x_GPT_TCLR_AR_FLAG;
    224213
    225214        timer->special_available = (
    … …  
    227216            (ioregs == AMDM37x_GPT2_BASE_ADDRESS) ||
    228217            (ioregs == AMDM37x_GPT10_BASE_ADDRESS));
    229         /* Select reload value */
    230218        timer->regs->tldr = 0xffffffff - (32768 / hz) + 1;
    231         /* Set current counter value */
    232219        timer->regs->tccr = 0xffffffff - (32768 / hz) + 1;
    233 
    234220        if (timer->special_available) {
    235                 /* Set values according to formula (manual p. 2733) */
     221                /* Set values for according to formula (manual p. 2733) */
    236222                /* Use temporary variables for easier debugging */
    237223                const uint32_t tpir =
    238224                    ((32768 / hz + 1) * 1000000) - (32768000L * (1000 / hz));
    239225                const uint32_t tnir =
    240                     ((32768 / hz) * 1000000) - (32768000L * (1000 / hz));
     226                    ((32768 / hz) * 1000000) - (32768000 * (1000 / hz));
    241227                timer->regs->tpir = tpir;
    242228                timer->regs->tnir = tnir;
    … …  
    255241}
    256242
    257 static inline bool amdm37x_gpt_irq_ack(amdm37x_gpt_t* timer)
     243static inline void amdm37x_gpt_irq_ack(amdm37x_gpt_t* timer)
    258244{
    259245        ASSERT(timer);
    260246        ASSERT(timer->regs);
    261247        /* Clear all pending interrupts */
    262         const uint32_t tisr = timer->regs->tisr;
    263         timer->regs->tisr = tisr;
    264         return tisr != 0;
     248        timer->regs->tisr = timer->regs->tisr;
    265249}
    266250
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