Index: kernel/arch/arm32/include/arch/mm/page.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/page.h	(revision 3e6bca8e30f09268060ae3e4db1f0a3d721f5730)
+++ kernel/arch/arm32/include/arch/mm/page.h	(revision a7f7b9c3744bb1a355f84327e6b489c2a79f47c5)
@@ -159,4 +159,7 @@
 #endif
 	TTBR0_write(val);
+#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
+	BPIALL_write(0);
+#endif
 }
 
Index: kernel/arch/arm32/src/cpu/cpu.c
===================================================================
--- kernel/arch/arm32/src/cpu/cpu.c	(revision 3e6bca8e30f09268060ae3e4db1f0a3d721f5730)
+++ kernel/arch/arm32/src/cpu/cpu.c	(revision a7f7b9c3744bb1a355f84327e6b489c2a79f47c5)
@@ -170,6 +170,4 @@
 	 */
 	control_reg |= SCTLR_CACHE_EN_FLAG;
-#endif
-#ifdef PROCESSOR_ARCH_armv7_a
 	/*
 	 * ICache coherency is elaborated on in barrier.h.