Index: uspace/drv/audio/sb16/dsp_commands.h =================================================================== --- uspace/drv/audio/sb16/dsp_commands.h (revision 4f8772d4d5ecb28999d787aebab937222f9f97d8) +++ uspace/drv/audio/sb16/dsp_commands.h (revision a4eb3ba2b6a831a2a639dfe74c4deb2ca435b91c) @@ -38,127 +38,236 @@ /** See Sound Blaster Series HW programming Guide Chapter 6. */ typedef enum dsp_command { - DIRECT_8B_OUTPUT = 0x10, /* Followed by unsigned byte of digital data, - * software controls sampling rate */ - DIRECT_8B_INPUT = 0x20, /* Same as DIRECT_8B_OUTPUT but for input */ - - TRANSFER_TIME_CONSTANT = 0x40, /* Followed by time constant. - * TC = 65536 - (256 000 000 / - * (channels * sampling rate)) - * Send only high byte */ - - SINGLE_DMA_8B_OUTPUT = 0x14, /* Followed by length.high and length.low - * starts single-cycle DMA, length is -1 */ - SINGLE_DMA_8B_INPUT = 0x24, /* Same as SINGLE_DMA_8B_OUTPUT, but for - * input */ - SINGLE_DMA_8B_ADPCM_2B_OUT = 0x16, /* Starts single-cycle DMA using - * Creative ADPSM 8->2 bit compressed - * data, Followed by length.low - * and length.high. Length is -1 */ - SINGLE_DMA_8B_ADPCM_2B_OUT_REF = 0x17, /* Starts single-cycle DMA using - * DPSM 8->2 bit compressed data - * with reference byte. - * Followed by length.low and - * length.high. Length is -1 */ - SINGLE_DMA_8B_ADPCM_4B_OUT = 0x74, /* Same as - * SINGLE_DMA_8B_ADPCM_2B_OUT */ - SINGLE_DMA_8B_ADPCM_4B_OUT_REF = 0x75, /* Same as - * SINGLE_DMA_8B_ADPCM_2B_OUT_REF - */ - SINGLE_DMA_8B_ADPCM_3B_OUT = 0x76, /* Same as - * SINGLE_DMA_8B_ADPCM_2B_OUT */ - SINGLE_DMA_8B_ADPCM_3B_OUT_REF = 0x77, /* Same as - * SINGLE_DMA_8B_ADPCM_2B_OUT_REF - */ - - DMA_8B_PAUSE = 0xd0, /* Stop sending DMA request, - * works for SINGLE and AUTO */ - DMA_8B_CONTINUE = 0xd4, /* Resume transfers paused by DMA_8B_PAUSE */ - - SPEAKER_ON = 0xd1, /* Connect speaker via internal amplifier, - * has no effect on 4.xx */ - SPEAKER_OFF = 0xd3, /* Disconnect output from the amplifier, - * has no effect on 4.xx */ - - MIDI_POLLING = 0x30, /* Read DSP for MIDI data */ - MIDI_INTERRUPT = 0x31, /* Start interrupt mode, interrupt will be - * generated when there is in-bound data. - * To exit send again */ - MIDI_OUTPUT = 0x38, /* Followed by midi_data */ - - PAUSE = 0x80, /* Followed by duration.low, duration.high. Duration is -1 - * In the units of sampling period. Generates interrupt - * at the end of period */ - DSP_VERSION = 0xe1, /* Read 2 bytes, major and minor number */ - - AUTO_DMA_8B_OUTPUT = 0x1c, /* Starts auto-init DMA mode using 8-bit - * Interrupt after every block. - * To terminate, switch to single or use - * EXIT command*/ - AUTO_DMA_8B_INPUT = 0x2c, /* Same as AUTO_DMA_8B_OUTPUT, but for input*/ - AUTO_DMA_8B_ADPCM_2B_REF = 0x1f, /* Same as AUTO_DMA_8B_OUTPUT, but use - * 8->2bit ADPCM audio format */ - AUTO_DMA_8B_ADPCM_4B_REF = 0x7d, /* Same as AUTO_DMA_8B_ADPCM_2B_REF */ - AUTO_DMA_8B_ADPCM_3B_REF = 0x7f, /* Same as AUTO_DMA_8B_ADPCM_2B_REF */ - - DMA_8B_EXIT = 0xda, /* Ends DMA transfer and terminates I/O process */ - - BLOCK_TRANSFER_SIZE = 0x48, /* Followed by size.low, size.high - * Used with HIGH_SPEED AUTO_DMA */ - - UART_MIDI_POLLING = 0x34, /* Start UART MIDI polling mode, read and - * write from/to DSP is interpreted as - * read/write from/to MIDI. - * To exit use reset signal. Note that reset - * will restore previous state and won't do - * complete reset */ - UART_MIDI_INTERRUPT = 0x35, /* Same as UART_MIDI_POLLING, but use - * interrupts instead of polling. */ - UART_MIDI_POLLING_TS = 0x36, /* Add time stamp to inbound data, the - * order is time.low time.mid time.high - * data */ - UART_MIDI_INTERRUPT_TS = 0x37, /* Same as UART_MIDI_POLLING_TS, but use - * interrupts instead of polling */ - - SPEAKER_STATUS = 0xd8, /* 0xff means amp is on, 0x00 means it's off */ - - AUTO_DMA_8B_HIGH_OUTPUT = 0x90, /* DSP will generate interrupt after - * every block. No other commands are - * accepted in this mode. To exit - * the mode send RESET command. - * Note that reset will restore - * previous state. */ - AUTO_DMA_8B_HIGH_INPUT = 0x98, /* Same as AUTO_DMA_8B_HIGH_OUTPUT */ - SINGLE_DMA_8B_HIGH_OUTPUT = 0x91, /* Transfer one block and exit, - * generates interrupt */ - SINGLE_DMA_8B_HIGH_INPUT = 0x99, /* Same as SINGLE_DMA_8B_HIGH_OUTPUT */ - - SET_MONO_INPUT = 0xa0, /* Mono mode is the default, only on 3.xx */ - SET_STEREO_INPUT = 0xa8, /* Switch to stereo recording, only on 3.xx */ - - SET_SAMPLING_RATE_OUTPUT = 0x41, /* Followed by sapling rate - * 5000 to 45000 Hz, inclusive */ - SET_SAMPLING_RATE_INPUT = 0x42, /* Same as SET_SAMPLING_RATE_OUTPUT */ - - SINGLE_DMA_16B_DA = 0xb0, /* Followed by mode, size.low, size.high*/ - SINGLE_DMA_16B_DA_FIFO = 0xb2,/* mode format is: */ - AUTO_DMA_16B_DA = 0xb4, /* 0x00 - unsigned mono */ - AUTO_DMA_16B_DA_FIFO = 0xb6, /* 0x10 - signed mono */ - SINGLE_DMA_16B_AD = 0xb8, /* 0x20 - unsigned stereo */ - SINGLE_DMA_16B_AD_FIFO = 0xba,/* 0x30 - signed stereo */ - AUTO_DMA_16B_AD = 0xbc, /* Size is -1. Terminate by EXIT */ - AUTO_DMA_16B_AD_FIFO = 0xbe, /* or switch to SINGLE_DMA */ - - SINGLE_DMA_8B_DA = 0xc0, /* Followed by mode, size.low, size.high */ - SINGLE_DMA_8B_DA_FIFO = 0xc2,/* mode format is: */ - AUTO_DMA_8B_DA = 0xc4, /* 0x00 - unsigned mono */ - AUTO_DMA_8B_DA_FIFO = 0xc6, /* 0x10 - signed mono */ - SINGLE_DMA_8B_AD = 0xc8, /* 0x20 - unsigned stereo */ - SINGLE_DMA_8B_AD_FIFO = 0xca,/* 0x30 - signed stereo */ - AUTO_DMA_8B_AD = 0xcc, /* Size is -1. Terminate by EXIT */ - AUTO_DMA_8B_AD_FIFO = 0xce, /* or switch to SINGLE_DMA */ - - DMA_16B_PAUSE = 0xd5,/* Stop sending DMA request, both SINGLE and AUTO*/ - DMA_16B_CONTINUE = 0xd6, /* Resume requests paused by DMA_16B_PAUSE */ - DMA_16B_EXIT = 0xd9, /* Ends DMA transfer and terminates I/O process */ + /* + * Followed by unsigned byte of digital data, + * software controls sampling rate + */ + DIRECT_8B_OUTPUT = 0x10, + /* Same as DIRECT_8B_OUTPUT but for input */ + DIRECT_8B_INPUT = 0x20, + + /* + * Followed by time constant. + * TC = 65536 - (256 000 000 / + * (channels * sampling rate)) + * Send only high byte + */ + TRANSFER_TIME_CONSTANT = 0x40, + + /* + * Followed by length.high and length.low + * starts single-cycle DMA, length is -1 + */ + SINGLE_DMA_8B_OUTPUT = 0x14, + /* + * Same as SINGLE_DMA_8B_OUTPUT, but for + * input + */ + SINGLE_DMA_8B_INPUT = 0x24, + /* + * Starts single-cycle DMA using + * Creative ADPSM 8->2 bit compressed + * data, Followed by length.low + * and length.high. Length is -1 + */ + SINGLE_DMA_8B_ADPCM_2B_OUT = 0x16, + /* + * Starts single-cycle DMA using + * DPSM 8->2 bit compressed data + * with reference byte. + * Followed by length.low and + * length.high. Length is -1 + */ + SINGLE_DMA_8B_ADPCM_2B_OUT_REF = 0x17, + /* + * Same as + * SINGLE_DMA_8B_ADPCM_2B_OUT + */ + SINGLE_DMA_8B_ADPCM_4B_OUT = 0x74, + /* + * Same as + * SINGLE_DMA_8B_ADPCM_2B_OUT_REF + */ + SINGLE_DMA_8B_ADPCM_4B_OUT_REF = 0x75, + /* + * Same as + * SINGLE_DMA_8B_ADPCM_2B_OUT + */ + SINGLE_DMA_8B_ADPCM_3B_OUT = 0x76, + /* + * Same as + * SINGLE_DMA_8B_ADPCM_2B_OUT_REF + */ + SINGLE_DMA_8B_ADPCM_3B_OUT_REF = 0x77, + /* + * Stop sending DMA request, + * works for SINGLE and AUTO + */ + DMA_8B_PAUSE = 0xd0, + /* Resume transfers paused by DMA_8B_PAUSE */ + DMA_8B_CONTINUE = 0xd4, + + /* + * Connect speaker via internal amplifier, + * has no effect on 4.xx + */ + SPEAKER_ON = 0xd1, + /* + * Disconnect output from the amplifier, + * has no effect on 4.xx + */ + SPEAKER_OFF = 0xd3, + + /* Read DSP for MIDI data */ + MIDI_POLLING = 0x30, + /* + * Start interrupt mode, interrupt will be + * generated when there is in-bound data. + * To exit send again + */ + MIDI_INTERRUPT = 0x31, + /* Followed by midi_data */ + MIDI_OUTPUT = 0x38, + + /* + * Followed by duration.low, duration.high. Duration is -1 + * In the units of sampling period. Generates interrupt + * at the end of period + */ + PAUSE = 0x80, + /* Read 2 bytes, major and minor number */ + DSP_VERSION = 0xe1, + + /* + * Starts auto-init DMA mode using 8-bit + * Interrupt after every block. + * To terminate, switch to single or use + * EXIT command + */ + AUTO_DMA_8B_OUTPUT = 0x1c, + /* Same as AUTO_DMA_8B_OUTPUT, but for input */ + AUTO_DMA_8B_INPUT = 0x2c, + /* + * Same as AUTO_DMA_8B_OUTPUT, but use + * 8->2bit ADPCM audio format + */ + AUTO_DMA_8B_ADPCM_2B_REF = 0x1f, + /* Same as AUTO_DMA_8B_ADPCM_2B_REF */ + AUTO_DMA_8B_ADPCM_4B_REF = 0x7d, + /* Same as AUTO_DMA_8B_ADPCM_2B_REF */ + AUTO_DMA_8B_ADPCM_3B_REF = 0x7f, + + /* Ends DMA transfer and terminates I/O process */ + DMA_8B_EXIT = 0xda, + + /* + * Followed by size.low, size.high + * Used with HIGH_SPEED AUTO_DMA + */ + BLOCK_TRANSFER_SIZE = 0x48, + /* + * Start UART MIDI polling mode, read and + * write from/to DSP is interpreted as + * read/write from/to MIDI. + * To exit use reset signal. Note that reset + * will restore previous state and won't do + * complete reset + */ + UART_MIDI_POLLING = 0x34, + /* + * Same as UART_MIDI_POLLING, but use + * interrupts instead of polling. + */ + UART_MIDI_INTERRUPT = 0x35, + /* + * Add time stamp to inbound data, the + * order is time.low time.mid time.high + * data + */ + UART_MIDI_POLLING_TS = 0x36, + /* + * Same as UART_MIDI_POLLING_TS, but use + * interrupts instead of polling + */ + UART_MIDI_INTERRUPT_TS = 0x37, + + /* 0xff means amp is on, 0x00 means it's off */ + SPEAKER_STATUS = 0xd8, + + /* + * DSP will generate interrupt after + * every block. No other commands are + * accepted in this mode. To exit + * the mode send RESET command. + * Note that reset will restore + * previous state. + */ + AUTO_DMA_8B_HIGH_OUTPUT = 0x90, + /* Same as AUTO_DMA_8B_HIGH_OUTPUT */ + AUTO_DMA_8B_HIGH_INPUT = 0x98, + /* + * Transfer one block and exit, + * generates interrupt + */ + SINGLE_DMA_8B_HIGH_OUTPUT = 0x91, + /* Same as SINGLE_DMA_8B_HIGH_OUTPUT */ + SINGLE_DMA_8B_HIGH_INPUT = 0x99, + + /* Mono mode is the default, only on 3.xx */ + SET_MONO_INPUT = 0xa0, + /* Switch to stereo recording, only on 3.xx */ + SET_STEREO_INPUT = 0xa8, + + /* + * Followed by sapling rate + * 5000 to 45000 Hz, inclusive + */ + SET_SAMPLING_RATE_OUTPUT = 0x41, + /* Same as SET_SAMPLING_RATE_OUTPUT */ + SET_SAMPLING_RATE_INPUT = 0x42, + + /* + * Followed by mode, size.low, size.high + * mode format is: + * 0x00 - unsigned mono + * 0x10 - signed mono + * 0x20 - unsigned stereo + * 0x30 - signed stereo + * Size is -1. Terminate AUTO_DMA by EXIT + * or switch to SINGLE_DMA + */ + SINGLE_DMA_16B_DA = 0xb0, + SINGLE_DMA_16B_DA_FIFO = 0xb2, + AUTO_DMA_16B_DA = 0xb4, + AUTO_DMA_16B_DA_FIFO = 0xb6, + SINGLE_DMA_16B_AD = 0xb8, + SINGLE_DMA_16B_AD_FIFO = 0xba, + AUTO_DMA_16B_AD = 0xbc, + AUTO_DMA_16B_AD_FIFO = 0xbe, + + /* + * Followed by mode, size.low, size.high + * mode format is: + * 0x00 - unsigned mono + * 0x10 - signed mono + * 0x20 - unsigned stereo + * 0x30 - signed stereo + * Size is -1. Terminate AUTO_DMA by EXIT + * or switch to SINGLE_DMA + */ + SINGLE_DMA_8B_DA = 0xc0, + SINGLE_DMA_8B_DA_FIFO = 0xc2, + AUTO_DMA_8B_DA = 0xc4, + AUTO_DMA_8B_DA_FIFO = 0xc6, + SINGLE_DMA_8B_AD = 0xc8, + SINGLE_DMA_8B_AD_FIFO = 0xca, + AUTO_DMA_8B_AD = 0xcc, + AUTO_DMA_8B_AD_FIFO = 0xce, + + /* Stop sending DMA request, both SINGLE and AUTO */ + DMA_16B_PAUSE = 0xd5, + /* Resume requests paused by DMA_16B_PAUSE */ + DMA_16B_CONTINUE = 0xd6, + /* Ends DMA transfer and terminates I/O process */ + DMA_16B_EXIT = 0xd9, } dsp_command_t; Index: uspace/drv/bus/usb/ehci/hw_struct/iso_transfer_descriptor.h =================================================================== --- uspace/drv/bus/usb/ehci/hw_struct/iso_transfer_descriptor.h (revision 4f8772d4d5ecb28999d787aebab937222f9f97d8) +++ uspace/drv/bus/usb/ehci/hw_struct/iso_transfer_descriptor.h (revision a4eb3ba2b6a831a2a639dfe74c4deb2ca435b91c) @@ -43,4 +43,13 @@ volatile uint32_t transaction[8]; + volatile uint32_t buffer_pointer[7]; + + /* 64 bit struct only */ + volatile uint32_t extended_bp[7]; +} __attribute__((packed, aligned(32))) itd_t; + +/* + * itd_t.transaction + */ #define ITD_TRANSACTION_STATUS_ACTIVE_FLAG (1 << 31) #define ITD_TRANSACTION_STATUS_BUFFER_ERROR_FLAG (1 << 30) @@ -55,5 +64,7 @@ #define ITD_TRANSACTION_OFFSET_SHIFT 0 - volatile uint32_t buffer_pointer[7]; +/* + * itd_t.buffer_pointer + */ #define ITD_BUFFER_POINTER_MASK 0xfffff000 /* First buffer pointer */ @@ -70,8 +81,6 @@ #define ITD_BUFFER_POINTER_MULTI_SHIFT 0 - /* 64 bit struct only */ - volatile uint32_t extended_bp[7]; -} __attribute__((packed, aligned(32))) itd_t; #endif + /** * @} Index: uspace/drv/bus/usb/ehci/hw_struct/queue_head.h =================================================================== --- uspace/drv/bus/usb/ehci/hw_struct/queue_head.h (revision 4f8772d4d5ecb28999d787aebab937222f9f97d8) +++ uspace/drv/bus/usb/ehci/hw_struct/queue_head.h (revision a4eb3ba2b6a831a2a639dfe74c4deb2ca435b91c) @@ -49,4 +49,20 @@ volatile uint32_t ep_char; + volatile uint32_t ep_cap; + + link_pointer_t current; + /* Transfer overlay starts here */ + link_pointer_t next; + link_pointer_t alternate; + volatile uint32_t status; + volatile uint32_t buffer_pointer[5]; + + /* 64 bit struct only */ + volatile uint32_t extended_bp[5]; +} __attribute__((packed, aligned(32))) qh_t; + +/* + * qh_t.ep_char + */ #define QH_EP_CHAR_RL_MASK 0xf #define QH_EP_CHAR_RL_SHIFT 28 @@ -78,5 +94,7 @@ (((val) >> QH_EP_CHAR_ADDR_SHIFT) & QH_EP_CHAR_ADDR_MASK) - volatile uint32_t ep_cap; +/* + * qh_t.ep_cap + */ #define QH_EP_CAP_MULTI_MASK 0x3 #define QH_EP_CAP_MULTI_SHIFT 30 @@ -100,12 +118,13 @@ (((val) & QH_EP_CAP_S_MASK_MASK) << QH_EP_CAP_S_MASK_SHIFT) - link_pointer_t current; -/* Transfer overlay starts here */ - link_pointer_t next; - link_pointer_t alternate; +/* + * qh_t.alternate + */ #define QH_ALTERNATE_NACK_CNT_MASK 0x7 #define QH_ALTERNATE_NACK_CNT_SHIFT 1 - volatile uint32_t status; +/* + * qh_t.status + */ #define QH_STATUS_TOGGLE_FLAG (1 << 31) #define QH_STATUS_TOTAL_MASK 0x7fff @@ -127,5 +146,7 @@ #define QH_STATUS_PING_FLAG (1 << 0) - volatile uint32_t buffer_pointer[5]; +/* + * qh_t.buffer_pointer + */ #define QH_BUFFER_POINTER_MASK 0xfffff000 /* Only the first buffer pointer */ @@ -141,7 +162,4 @@ #define QH_BUFFER_POINTER_FTAG_SHIFT 0 - /* 64 bit struct only */ - volatile uint32_t extended_bp[5]; -} __attribute__((packed, aligned(32))) qh_t; static inline void qh_append_qh(qh_t *qh, const qh_t *next) @@ -212,6 +230,6 @@ } - -void qh_init(qh_t *instance, const endpoint_t *ep); +extern void qh_init(qh_t *instance, const endpoint_t *ep); + #endif /** Index: uspace/drv/bus/usb/ehci/hw_struct/split_iso_transfer_descriptor.h =================================================================== --- uspace/drv/bus/usb/ehci/hw_struct/split_iso_transfer_descriptor.h (revision 4f8772d4d5ecb28999d787aebab937222f9f97d8) +++ uspace/drv/bus/usb/ehci/hw_struct/split_iso_transfer_descriptor.h (revision a4eb3ba2b6a831a2a639dfe74c4deb2ca435b91c) @@ -43,4 +43,16 @@ volatile uint32_t ep; + volatile uint32_t uframe; + volatile uint32_t status; + volatile uint32_t buffer_pointer[2]; + link_pointer_t back; + + /* 64 bit struct only */ + volatile uint32_t extended_bp[2]; +} __attribute__((packed, aligned(32))) sitd_t; + +/* + * sitd_t.ep + */ #define SITD_EP_IN_FLAG (1 << 31) #define SITD_EP_PORT_MASK 0x3f @@ -53,5 +65,7 @@ #define SITD_EP_ADDR_SHIFT 0 - volatile uint32_t uframe; +/* + * sitd_t.uframe + */ #define SITD_uFRAME_CMASK_MASK 0xff #define SITD_uFRAME_CMASK_SHIFT 8 @@ -59,5 +73,7 @@ #define SITD_uFRAME_SMASK_SHIFT 0 - volatile uint32_t status; +/* + * sitd_t.status + */ #define SITD_STATUS_IOC_FLAG (1 << 31) #define SITD_STATUS_PAGE_FLAG (1 << 30) @@ -74,5 +90,7 @@ #define SITD_STATUS_SPLIT_COMPLETE_FLAG (1 << 1) - volatile uint32_t buffer_pointer[2]; +/* + * sitd_t.buffer_pointer + */ #define SITD_BUFFER_POINTER_MASK 0xfffff000 /* Only the first page pointer */ @@ -85,10 +103,6 @@ #define SITD_BUFFER_POINTER_COUNT_SHIFT 0 - link_pointer_t back; +#endif - /* 64 bit struct only */ - volatile uint32_t extended_bp[2]; -} __attribute__((packed, aligned(32))) sitd_t; -#endif /** * @} Index: uspace/drv/bus/usb/ehci/hw_struct/transfer_descriptor.h =================================================================== --- uspace/drv/bus/usb/ehci/hw_struct/transfer_descriptor.h (revision 4f8772d4d5ecb28999d787aebab937222f9f97d8) +++ uspace/drv/bus/usb/ehci/hw_struct/transfer_descriptor.h (revision a4eb3ba2b6a831a2a639dfe74c4deb2ca435b91c) @@ -47,4 +47,15 @@ volatile uint32_t status; + + volatile uint32_t buffer_pointer[5]; + + /* 64 bit struct only */ + volatile uint32_t extended_bp[5]; + +} __attribute__((packed, aligned(32))) td_t; + +/* + * td_t.status + */ #define TD_STATUS_TOGGLE_FLAG (1 << 31) #define TD_STATUS_TOTAL_MASK 0x7fff @@ -69,13 +80,11 @@ #define TD_STATUS_PING_FLAG (1 << 0) - volatile uint32_t buffer_pointer[5]; +/* + * td_t.buffer_pointer + */ + #define TD_BUFFER_POINTER_MASK 0xfffff000 /* Only the first page pointer */ #define TD_BUFFER_POINTER_OFFSET_MASK 0xfff - - /* 64 bit struct only */ - volatile uint32_t extended_bp[5]; - -} __attribute__((packed, aligned(32))) td_t; static_assert(sizeof(td_t) % 32 == 0); Index: uspace/drv/bus/usb/ohci/ohci_regs.h =================================================================== --- uspace/drv/bus/usb/ohci/ohci_regs.h (revision 4f8772d4d5ecb28999d787aebab937222f9f97d8) +++ uspace/drv/bus/usb/ohci/ohci_regs.h (revision a4eb3ba2b6a831a2a639dfe74c4deb2ca435b91c) @@ -50,69 +50,20 @@ typedef struct ohci_regs { const ioport32_t revision; -#define R_REVISION_MASK (0x3f) -#define R_LEGACY_FLAG (0x80) ioport32_t control; -/* Control-bulk service ratio */ -#define C_CBSR_1_1 (0x0) -#define C_CBSR_1_2 (0x1) -#define C_CBSR_1_3 (0x2) -#define C_CBSR_1_4 (0x3) -#define C_CBSR_MASK (0x3) -#define C_CBSR_SHIFT 0 - -#define C_PLE (1 << 2) /* Periodic list enable */ -#define C_IE (1 << 3) /* Isochronous enable */ -#define C_CLE (1 << 4) /* Control list enable */ -#define C_BLE (1 << 5) /* Bulk list enable */ - -/* Host controller functional state */ -#define C_HCFS_RESET (0x0) -#define C_HCFS_RESUME (0x1) -#define C_HCFS_OPERATIONAL (0x2) -#define C_HCFS_SUSPEND (0x3) -#define C_HCFS_GET(reg) ((OHCI_RD(reg) >> 6) & 0x3) -#define C_HCFS_SET(reg, value) \ -do { \ - uint32_t r = OHCI_RD(reg); \ - r &= ~(0x3 << 6); \ - r |= (value & 0x3) << 6; \ - OHCI_WR(reg, r); \ -} while (0) - -#define C_IR (1 << 8) /* Interrupt routing, make sure it's 0 */ -#define C_RWC (1 << 9) /* Remote wakeup connected, host specific */ -#define C_RWE (1 << 10) /* Remote wakeup enable */ ioport32_t command_status; -#define CS_HCR (1 << 0) /* Host controller reset */ -#define CS_CLF (1 << 1) /* Control list filled */ -#define CS_BLF (1 << 2) /* Bulk list filled */ -#define CS_OCR (1 << 3) /* Ownership change request */ -#if 0 -#define CS_SOC_MASK (0x3) /* Scheduling overrun count */ -#define CS_SOC_SHIFT (16) -#endif /** Interupt enable/disable/status, * reads give the same value, * writing causes enable/disable, - * status is write-clean (writing 1 clears the bit*/ + * status is write-clean (writing 1 clears the bit + */ ioport32_t interrupt_status; ioport32_t interrupt_enable; ioport32_t interrupt_disable; -#define I_SO (1 << 0) /* Scheduling overrun */ -#define I_WDH (1 << 1) /* Done head write-back */ -#define I_SF (1 << 2) /* Start of frame */ -#define I_RD (1 << 3) /* Resume detect */ -#define I_UE (1 << 4) /* Unrecoverable error */ -#define I_FNO (1 << 5) /* Frame number overflow */ -#define I_RHSC (1 << 6) /* Root hub status change */ -#define I_OC (1 << 30) /* Ownership change */ -#define I_MI (1 << 31) /* Master interrupt (any/all) */ /** HCCA pointer (see hw_struct hcca.h) */ ioport32_t hcca; -#define HCCA_PTR_MASK 0xffffff00 /* HCCA is 256B aligned */ /** Currently executed periodic endpoint */ @@ -136,82 +87,25 @@ /** Frame time and max packet size for all transfers */ ioport32_t fm_interval; -#define FMI_FI_MASK (0x3fff) /* Frame interval in bit times (should be 11999)*/ -#define FMI_FI_SHIFT (0) -#define FMI_FSMPS_MASK (0x7fff) /* Full speed max packet size */ -#define FMI_FSMPS_SHIFT (16) -#define FMI_TOGGLE_FLAG (1 << 31) /** Bit times remaining in current frame */ const ioport32_t fm_remaining; -#define FMR_FR_MASK FMI_FI_MASK -#define FMR_FR_SHIFT FMI_FI_SHIFT -#define FMR_TOGGLE_FLAG FMI_TOGGLE_FLAG /** Frame number */ const ioport32_t fm_number; -#define FMN_NUMBER_MASK (0xffff) /** Remaining bit time in frame to start periodic transfers */ ioport32_t periodic_start; -#define PS_MASK 0x3fff -#define PS_SHIFT 0 /** Threshold for starting LS transaction */ ioport32_t ls_threshold; -#define LST_LST_MASK (0x7fff) /** The first root hub control register */ ioport32_t rh_desc_a; -/** Number of downstream ports, max 15 */ -#define RHDA_NDS_MASK (0xff) -/** Power switching mode: 0-global, 1-per port*/ -#define RHDA_PSM_FLAG (1 << 8) -/** No power switch: 1-power on, 0-use PSM*/ -#define RHDA_NPS_FLAG (1 << 9) -/** 1-Compound device, must be 0 */ -#define RHDA_DT_FLAG (1 << 10) -/** Over-current mode: 0-global, 1-per port */ -#define RHDA_OCPM_FLAG (1 << 11) -/** OC control: 0-use OCPM, 1-OC off */ -#define RHDA_NOCP_FLAG (1 << 12) -/** Power on to power good time */ -#define RHDA_POTPGT_SHIFT 24 /** The other root hub control register */ ioport32_t rh_desc_b; -/** Device removable mask */ -#define RHDB_DR_SHIFT 0 -#define RHDB_DR_MASK 0xffffU -/** Power control mask */ -#define RHDB_PCC_MASK 0xffffU -#define RHDB_PCC_SHIFT 16 /** Root hub status register */ ioport32_t rh_status; -/* read: 0, - * write: 0-no effect, - * 1-turn off port power for ports - * specified in PPCM(RHDB), or all ports, - * if power is set globally */ -#define RHS_LPS_FLAG (1 << 0) -#define RHS_CLEAR_GLOBAL_POWER RHS_LPS_FLAG /* synonym for the above */ -/** Over-current indicator, if per-port: 0 */ -#define RHS_OCI_FLAG (1 << 1) - -/* read: 0-connect status change does not wake HC - * 1-connect status change wakes HC - * write: 1-set DRWE, 0-no effect */ -#define RHS_DRWE_FLAG (1 << 15) -#define RHS_SET_DRWE RHS_DRWE_FLAG -/* read: 0, - * write: 0-no effect - * 1-turn on port power for ports - * specified in PPCM(RHDB), or all ports, - * if power is set globally */ -#define RHS_LPSC_FLAG (1 << 16) -#define RHS_SET_GLOBAL_POWER RHS_LPSC_FLAG /* synonym for the above */ -/** Over-current change indicator*/ -#define RHS_OCIC_FLAG (1 << 17) -#define RHS_CLEAR_DRWE (1 << 31) /** Root hub per port status */ @@ -249,5 +143,223 @@ } ohci_regs_t; +/* + * ohci_regs_t.revision + */ + +#define R_REVISION_MASK (0x3f) +#define R_LEGACY_FLAG (0x80) + +/* + * ohci_regs_t.control + */ + +/* Control-bulk service ratio */ +#define C_CBSR_1_1 (0x0) +#define C_CBSR_1_2 (0x1) +#define C_CBSR_1_3 (0x2) +#define C_CBSR_1_4 (0x3) +#define C_CBSR_MASK (0x3) +#define C_CBSR_SHIFT 0 + +#define C_PLE (1 << 2) /* Periodic list enable */ +#define C_IE (1 << 3) /* Isochronous enable */ +#define C_CLE (1 << 4) /* Control list enable */ +#define C_BLE (1 << 5) /* Bulk list enable */ + +/* Host controller functional state */ +#define C_HCFS_RESET (0x0) +#define C_HCFS_RESUME (0x1) +#define C_HCFS_OPERATIONAL (0x2) +#define C_HCFS_SUSPEND (0x3) +#define C_HCFS_GET(reg) ((OHCI_RD(reg) >> 6) & 0x3) +#define C_HCFS_SET(reg, value) \ +do { \ + uint32_t r = OHCI_RD(reg); \ + r &= ~(0x3 << 6); \ + r |= (value & 0x3) << 6; \ + OHCI_WR(reg, r); \ +} while (0) + +#define C_IR (1 << 8) /* Interrupt routing, make sure it's 0 */ +#define C_RWC (1 << 9) /* Remote wakeup connected, host specific */ +#define C_RWE (1 << 10) /* Remote wakeup enable */ + +/* + * ohci_regs_t.command_status + */ + +#define CS_HCR (1 << 0) /* Host controller reset */ +#define CS_CLF (1 << 1) /* Control list filled */ +#define CS_BLF (1 << 2) /* Bulk list filled */ +#define CS_OCR (1 << 3) /* Ownership change request */ +#if 0 +#define CS_SOC_MASK (0x3) /* Scheduling overrun count */ +#define CS_SOC_SHIFT (16) #endif + +/* + * ohci_regs_t.interrupt_xxx + */ + +#define I_SO (1 << 0) /* Scheduling overrun */ +#define I_WDH (1 << 1) /* Done head write-back */ +#define I_SF (1 << 2) /* Start of frame */ +#define I_RD (1 << 3) /* Resume detect */ +#define I_UE (1 << 4) /* Unrecoverable error */ +#define I_FNO (1 << 5) /* Frame number overflow */ +#define I_RHSC (1 << 6) /* Root hub status change */ +#define I_OC (1 << 30) /* Ownership change */ +#define I_MI (1 << 31) /* Master interrupt (any/all) */ + + +/* + * ohci_regs_t.hcca + */ + +#define HCCA_PTR_MASK 0xffffff00 /* HCCA is 256B aligned */ + +/* + * ohci_regs_t.fm_interval + */ + +#define FMI_FI_MASK (0x3fff) /* Frame interval in bit times (should be 11999)*/ +#define FMI_FI_SHIFT (0) +#define FMI_FSMPS_MASK (0x7fff) /* Full speed max packet size */ +#define FMI_FSMPS_SHIFT (16) +#define FMI_TOGGLE_FLAG (1 << 31) + +/* + * ohci_regs_t.fm_remaining + */ + +#define FMR_FR_MASK FMI_FI_MASK +#define FMR_FR_SHIFT FMI_FI_SHIFT +#define FMR_TOGGLE_FLAG FMI_TOGGLE_FLAG + +/* + * ohci_regs_t.fm_number + */ + +#define FMN_NUMBER_MASK (0xffff) + +/* + * ohci_regs_t.periodic_start + */ + +#define PS_MASK 0x3fff +#define PS_SHIFT 0 + +/* + * ohci_regs_t.ls_threshold + */ + +#define LST_LST_MASK (0x7fff) + +/* + * ohci_regs_t.rh_desc_a + */ + +/** Number of downstream ports, max 15 */ +#define RHDA_NDS_MASK (0xff) +/** Power switching mode: 0-global, 1-per port*/ +#define RHDA_PSM_FLAG (1 << 8) +/** No power switch: 1-power on, 0-use PSM*/ +#define RHDA_NPS_FLAG (1 << 9) +/** 1-Compound device, must be 0 */ +#define RHDA_DT_FLAG (1 << 10) +/** Over-current mode: 0-global, 1-per port */ +#define RHDA_OCPM_FLAG (1 << 11) +/** OC control: 0-use OCPM, 1-OC off */ +#define RHDA_NOCP_FLAG (1 << 12) +/** Power on to power good time */ +#define RHDA_POTPGT_SHIFT 24 + +/* + * ohci_regs_t.rh_desc_b + */ + +/** Device removable mask */ +#define RHDB_DR_SHIFT 0 +#define RHDB_DR_MASK 0xffffU + +/** Power control mask */ +#define RHDB_PCC_MASK 0xffffU +#define RHDB_PCC_SHIFT 16 + +/* + * ohci_regs_t.rh_status + */ + +/* + * read: 0, + * write: 0-no effect, + * 1-turn off port power for ports + * specified in PPCM(RHDB), or all ports, + * if power is set globally + */ +#define RHS_LPS_FLAG (1 << 0) +#define RHS_CLEAR_GLOBAL_POWER RHS_LPS_FLAG /* synonym for the above */ +/** Over-current indicator, if per-port: 0 */ +#define RHS_OCI_FLAG (1 << 1) +/* + * read: 0-connect status change does not wake HC + * 1-connect status change wakes HC + * write: 1-set DRWE, 0-no effect + */ +#define RHS_DRWE_FLAG (1 << 15) +#define RHS_SET_DRWE RHS_DRWE_FLAG +/* + * read: 0, + * write: 0-no effect + * 1-turn on port power for ports + * specified in PPCM(RHDB), or all ports, + * if power is set globally + */ +#define RHS_LPSC_FLAG (1 << 16) +#define RHS_SET_GLOBAL_POWER RHS_LPSC_FLAG /* synonym for the above */ +/** Over-current change indicator*/ +#define RHS_OCIC_FLAG (1 << 17) +#define RHS_CLEAR_DRWE (1 << 31) + +#endif + +/* + * ohci_regs_t.rh_port_status[x] + */ + +/** r: current connect status, w: 1-clear port enable, 0-N/S*/ +#define RHPS_CCS_FLAG (1 << 0) +#define RHPS_CLEAR_PORT_ENABLE RHPS_CCS_FLAG +/** r: port enable status, w: 1-set port enable, 0-N/S */ +#define RHPS_PES_FLAG (1 << 1) +#define RHPS_SET_PORT_ENABLE RHPS_PES_FLAG +/** r: port suspend status, w: 1-set port suspend, 0-N/S */ +#define RHPS_PSS_FLAG (1 << 2) +#define RHPS_SET_PORT_SUSPEND RHPS_PSS_FLAG +/** r: port over-current (if reports are per-port + * w: 1-clear port suspend (start resume if suspened), 0-nothing + */ +#define RHPS_POCI_FLAG (1 << 3) +#define RHPS_CLEAR_PORT_SUSPEND RHPS_POCI_FLAG +/** r: port reset status, w: 1-set port reset, 0-N/S */ +#define RHPS_PRS_FLAG (1 << 4) +#define RHPS_SET_PORT_RESET RHPS_PRS_FLAG +/** r: port power status, w: 1-set port power, 0-N/S */ +#define RHPS_PPS_FLAG (1 << 8) +#define RHPS_SET_PORT_POWER RHPS_PPS_FLAG +/** r: low speed device attached, w: 1-clear port power, 0-N/S */ +#define RHPS_LSDA_FLAG (1 << 9) +#define RHPS_CLEAR_PORT_POWER RHPS_LSDA_FLAG +/** connect status change WC */ +#define RHPS_CSC_FLAG (1 << 16) +/** port enable status change WC */ +#define RHPS_PESC_FLAG (1 << 17) +/** port suspend status change WC */ +#define RHPS_PSSC_FLAG (1 << 18) +/** port over-current change WC */ +#define RHPS_OCIC_FLAG (1 << 19) +/** port reset status change WC */ +#define RHPS_PRSC_FLAG (1 << 20) +#define RHPS_CHANGE_WC_MASK (0x1f0000) /** Index: uspace/drv/bus/usb/uhci/hc.c =================================================================== --- uspace/drv/bus/usb/uhci/hc.c (revision 4f8772d4d5ecb28999d787aebab937222f9f97d8) +++ uspace/drv/bus/usb/uhci/hc.c (revision a4eb3ba2b6a831a2a639dfe74c4deb2ca435b91c) @@ -531,6 +531,8 @@ &instance->transfers_control_slow); - /*FSBR, This feature is not needed (adds no benefit) and is supposedly - * buggy on certain hw, enable at your own risk. */ + /* + * FSBR, This feature is not needed (adds no benefit) and is supposedly + * buggy on certain hw, enable at your own risk. + */ #ifdef FSBR transfer_list_set_next(&instance->transfers_bulk_full, Index: uspace/drv/bus/usb/xhci/commands.h =================================================================== --- uspace/drv/bus/usb/xhci/commands.h (revision 4f8772d4d5ecb28999d787aebab937222f9f97d8) +++ uspace/drv/bus/usb/xhci/commands.h (revision a4eb3ba2b6a831a2a639dfe74c4deb2ca435b91c) @@ -79,12 +79,15 @@ xhci_trb_ring_t trb_ring; - fibril_mutex_t guard; /**< Guard access to this structure. */ + /** Guard access to this structure. */ + fibril_mutex_t guard; list_t cmd_list; - xhci_cr_state_t state; /**< Whether commands are allowed to be - added. */ - fibril_condvar_t state_cv; /**< For waiting on CR state change. */ + /** Whether commands are allowed to be added. */ + xhci_cr_state_t state; + /** For waiting on CR state change. */ + fibril_condvar_t state_cv; - fibril_condvar_t stopped_cv; /**< For waiting on CR stopped event. */ + /** For waiting on CR stopped event. */ + fibril_condvar_t stopped_cv; } xhci_cmd_ring_t; @@ -108,5 +111,6 @@ /** Below are arguments of all commands mixed together. - * Be sure to know which command accepts what arguments. */ + * Be sure to know which command accepts what arguments. + */ uint32_t slot_id; Index: uspace/drv/nic/ne2k/dp8390.c =================================================================== --- uspace/drv/nic/ne2k/dp8390.c (revision 4f8772d4d5ecb28999d787aebab937222f9f97d8) +++ uspace/drv/nic/ne2k/dp8390.c (revision a4eb3ba2b6a831a2a639dfe74c4deb2ca435b91c) @@ -475,7 +475,9 @@ size_t frames_count = 0; - /* We may block sending in this loop - after so many received frames there + /* + * We may block sending in this loop - after so many received frames there * must be some interrupt pending (for the frames not yet downloaded) and - * we will continue in its handler. */ + * we will continue in its handler. + */ while (frames_count < 16) { //TODO: isn't some locking necessary here? Index: uspace/drv/nic/rtl8139/defs.h =================================================================== --- uspace/drv/nic/rtl8139/defs.h (revision 4f8772d4d5ecb28999d787aebab937222f9f97d8) +++ uspace/drv/nic/rtl8139/defs.h (revision a4eb3ba2b6a831a2a639dfe74c4deb2ca435b91c) @@ -280,38 +280,57 @@ /** Receiver control register values */ enum rtl8139_rcr { - RCR_ERTH_SHIFT = 24, /**< Early Rx treshold part shift */ - RCR_ERTH_SIZE = 4, /**< Early Rx treshold part size */ - - RCR_MulERINT = 1 << 17, /**< Multiple early interrupt select */ - - /** Minimal error frame length (1 = 8B, 0 = 64B). If AER/AR is set, RER8 - * is "Don't care" + /** Early Rx treshold part shift */ + RCR_ERTH_SHIFT = 24, + /** Early Rx treshold part size */ + RCR_ERTH_SIZE = 4, + + /** Multiple early interrupt select */ + RCR_MulERINT = 1 << 17, + + /** Minimal error frame length (1 = 8B, 0 = 64B). + * If AER/AR is set, RER8 is "Don't care" */ RCR_RER8 = 1 << 16, - RCR_RXFTH_SHIFT = 13, /**< Rx FIFO treshold part shitf */ - RCR_RXFTH_SIZE = 3, /**< Rx FIFO treshold part size */ - - RCR_RBLEN_SHIFT = 11, /**< Rx buffer length part shift */ - RCR_RBLEN_SIZE = 2, /**< Rx buffer length part size */ - - RCR_RBLEN_8k = 0x00 << RCR_RBLEN_SHIFT, /**< 8K + 16 byte rx buffer */ - RCR_RBLEN_16k = 0x01 << RCR_RBLEN_SHIFT, /**< 16K + 16 byte rx buffer */ - RCR_RBLEN_32k = 0x02 << RCR_RBLEN_SHIFT, /**< 32K + 16 byte rx buffer */ - RCR_RBLEN_64k = 0x03 << RCR_RBLEN_SHIFT, /**< 64K + 16 byte rx buffer */ - - RCR_MXDMA_SHIFT = 8, /**< Max DMA Burst Size part shift */ - RCR_MXDMA_SIZE = 3, /**< Max DMA Burst Size part size */ - - RCR_WRAP = 1 << 7, /**< Rx buffer wrapped */ - RCR_ACCEPT_ERROR = 1 << 5, /**< Accept error frame */ - RCR_ACCEPT_RUNT = 1 << 4, /**< Accept Runt (8-64 bytes) frames */ - RCR_ACCEPT_BROADCAST = 1 << 3, /**< Accept broadcast */ - RCR_ACCEPT_MULTICAST = 1 << 2, /**< Accept multicast */ - RCR_ACCEPT_PHYS_MATCH = 1 << 1, /**< Accept device MAC address match */ - RCR_ACCEPT_ALL_PHYS = 1 << 0, /**< Accept all frames with - * phys. desticnation - */ - RCR_ACCEPT_MASK = (1 << 6) - 1 /**< Mask of accept part */ + /** Rx FIFO treshold part shift */ + RCR_RXFTH_SHIFT = 13, + /** Rx FIFO treshold part size */ + RCR_RXFTH_SIZE = 3, + + /** Rx buffer length part shift */ + RCR_RBLEN_SHIFT = 11, + /** Rx buffer length part size */ + RCR_RBLEN_SIZE = 2, + + /** 8K + 16 byte rx buffer */ + RCR_RBLEN_8k = 0x00 << RCR_RBLEN_SHIFT, + /** 16K + 16 byte rx buffer */ + RCR_RBLEN_16k = 0x01 << RCR_RBLEN_SHIFT, + /** 32K + 16 byte rx buffer */ + RCR_RBLEN_32k = 0x02 << RCR_RBLEN_SHIFT, + /** 64K + 16 byte rx buffer */ + RCR_RBLEN_64k = 0x03 << RCR_RBLEN_SHIFT, + + /** Max DMA Burst Size part shift */ + RCR_MXDMA_SHIFT = 8, + /** Max DMA Burst Size part size */ + RCR_MXDMA_SIZE = 3, + + /** Rx buffer wrapped */ + RCR_WRAP = 1 << 7, + /** Accept error frame */ + RCR_ACCEPT_ERROR = 1 << 5, + /** Accept Runt (8-64 bytes) frames */ + RCR_ACCEPT_RUNT = 1 << 4, + /** Accept broadcast */ + RCR_ACCEPT_BROADCAST = 1 << 3, + /** Accept multicast */ + RCR_ACCEPT_MULTICAST = 1 << 2, + /** Accept device MAC address match */ + RCR_ACCEPT_PHYS_MATCH = 1 << 1, + /** Accept all frames with phys. destination */ + RCR_ACCEPT_ALL_PHYS = 1 << 0, + /** Mask of accept part */ + RCR_ACCEPT_MASK = (1 << 6) - 1 }; @@ -320,14 +339,18 @@ enum rtl8139_cscr { CS_Testfun = (1 << 15), - CS_LD = (1 << 9), /**< Low TPI link disable signal */ - CS_HEART_BEAT = (1 << 8), /**< Heart beat enable; 10Mbit mode only */ - CS_JABBER_ENABLE = (1 << 7), /**< Enable jabber function */ + /** Low TPI link disable signal */ + CS_LD = (1 << 9), + /** Heart beat enable; 10Mbit mode only */ + CS_HEART_BEAT = (1 << 8), + /** Enable jabber function */ + CS_JABBER_ENABLE = (1 << 7), CS_F_LINK100 = (1 << 6), CS_F_CONNECT = (1 << 5), - CS_CON_STATUS = (1 << 3), /**< connection status: - * 1 = valid, 0 = disconnected - */ - CS_CON_STATUS_EN = (1 << 2), /**< LED1 pin connection status indication */ - CS_PASS_SCR = (1 << 0) /**< Bypass Scramble */ + /** connection status: 1 = valid, 0 = disconnected */ + CS_CON_STATUS = (1 << 3), + /** LED1 pin connection status indication */ + CS_CON_STATUS_EN = (1 << 2), + /** Bypass Scramble */ + CS_PASS_SCR = (1 << 0) }; @@ -360,18 +383,24 @@ /** Auto-negotiation advertisement register */ enum rtl8139_anar { - ANAR_NEXT_PAGE = (1 << 15), /**< Next page bit, 0 - primary capability - * 1 - protocol specific - */ - ANAR_ACK = (1 << 14), /**< Capability reception acknowledge */ - ANAR_REMOTE_FAULT = (1 << 13), /**< Remote fault detection capability */ - ANAR_PAUSE = (1 << 10), /**< Symetric pause frame capability */ - ANAR_100T4 = (1 << 9), /**< T4, not supported by the device */ - ANAR_100TX_FD = (1 << 8), /**< 100BASE_TX full duplex */ - ANAR_100TX_HD = (1 << 7), /**< 100BASE_TX half duplex */ - ANAR_10_FD = (1 << 6), /**< 10BASE_T full duplex */ - ANAR_10_HD = (1 << 5), /**< 10BASE_T half duplex */ - ANAR_SELECTOR = 0x1 /**< Selector, - * CSMA/CD (0x1) supported only - */ + /** Next page bit, 0 - primary capability, 1 - protocol specific */ + ANAR_NEXT_PAGE = (1 << 15), + /** Capability reception acknowledge */ + ANAR_ACK = (1 << 14), + /** Remote fault detection capability */ + ANAR_REMOTE_FAULT = (1 << 13), + /** Symetric pause frame capability */ + ANAR_PAUSE = (1 << 10), + /** T4, not supported by the device */ + ANAR_100T4 = (1 << 9), + /** 100BASE_TX full duplex */ + ANAR_100TX_FD = (1 << 8), + /** 100BASE_TX half duplex */ + ANAR_100TX_HD = (1 << 7), + /** 10BASE_T full duplex */ + ANAR_10_FD = (1 << 6), + /** 10BASE_T half duplex */ + ANAR_10_HD = (1 << 5), + /** Selector, CSMA/CD (0x1) supported only */ + ANAR_SELECTOR = 0x1 }; @@ -409,12 +438,16 @@ enum rtl8139_config4 { - CONFIG4_RxFIFOAutoClr = (1 << 7), /**< Automatic RxFIFO owerflow clear */ - CONFIG4_AnaOff = (1 << 6), /**< Analog poweroff */ - CONFIG4_LongWF = (1 << 5), /**< Long wakeup frame - * (2xCRC8 + 3xCRC16) - */ - CONFIG4_LWPME = (1 << 4), /**< LWAKE and PMEB assertion */ - CONFIG4_LWPTN = (1 << 2), /**< LWake pattern */ - CONFIG4_PBWakeup = (1 << 0) /**< Preboot wakeup */ + /** Automatic RxFIFO owerflow clear */ + CONFIG4_RxFIFOAutoClr = (1 << 7), + /** Analog poweroff */ + CONFIG4_AnaOff = (1 << 6), + /** Long wakeup frame (2xCRC8 + 3xCRC16) */ + CONFIG4_LongWF = (1 << 5), + /** LWAKE and PMEB assertion */ + CONFIG4_LWPME = (1 << 4), + /** LWake pattern */ + CONFIG4_LWPTN = (1 << 2), + /** Preboot wakeup */ + CONFIG4_PBWakeup = (1 << 0) }; @@ -438,31 +471,43 @@ enum rtl8139_tcr_bits { - HWVERID_A_SHIFT = 26, /**< HW version id, part A shift */ - HWVERID_A_SIZE = 5, /**< HW version id, part A bit size */ - HWVERID_A_MASK = (1 << 5) - 1, /**< HW version id, part A mask */ - - IFG_SHIFT = 24, /**< The interframe gap time setting shift */ - IFG_SIZE = 2, /**< The interframe gap time setting bit size */ - - HWVERID_B_SHIFT = 22, /**< HW version id, part B shift */ - HWVERID_B_SIZE = 2, /**< HW version id, part B bit size */ - HWVERID_B_MASK = (1 << 2) - 1, /**< HW version id, part B mask */ - - LOOPBACK_SHIFT = 17, /**< Loopback mode shift */ - LOOPBACK_SIZE = 2, /**< Loopback mode size - * 00 = normal, 11 = loopback - */ - - APPEND_CRC = 1 << 16, /**< Append CRC at the end of a frame */ - - MXTxDMA_SHIFT = 8, /**< Max. DMA Burst per TxDMA shift, burst = 16^value */ - MXTxDMA_SIZE = 3, /**< Max. DMA Burst per TxDMA bit size */ - - TX_RETRY_COUNT_SHIFT = 4, /**< Retries before aborting shift */ - TX_RETRY_COUNT_SIZE = 4, /**< Retries before aborting size */ - - CLEAR_ABORT = 1 << 0 /**< Retransmit aborted frame at the last - * transmitted descriptor - */ + /** HW version id, part A shift */ + HWVERID_A_SHIFT = 26, + /** HW version id, part A bit size */ + HWVERID_A_SIZE = 5, + /** HW version id, part A mask */ + HWVERID_A_MASK = (1 << 5) - 1, + + /** The interframe gap time setting shift */ + IFG_SHIFT = 24, + /** The interframe gap time setting bit size */ + IFG_SIZE = 2, + + /** HW version id, part B shift */ + HWVERID_B_SHIFT = 22, + /** HW version id, part B bit size */ + HWVERID_B_SIZE = 2, + /** HW version id, part B mask */ + HWVERID_B_MASK = (1 << 2) - 1, + + /** Loopback mode shift */ + LOOPBACK_SHIFT = 17, + /** Loopback mode size. 00 = normal, 11 = loopback */ + LOOPBACK_SIZE = 2, + + /** Append CRC at the end of a frame */ + APPEND_CRC = 1 << 16, + + /** Max. DMA Burst per TxDMA shift, burst = 16^value */ + MXTxDMA_SHIFT = 8, + /** Max. DMA Burst per TxDMA bit size */ + MXTxDMA_SIZE = 3, + + /** Retries before aborting shift */ + TX_RETRY_COUNT_SHIFT = 4, + /** Retries before aborting size */ + TX_RETRY_COUNT_SIZE = 4, + + /** Retransmit aborted frame at the last transmitted descriptor */ + CLEAR_ABORT = 1 << 0 };