Index: kernel/arch/arm32/include/arch/cp15.h
===================================================================
--- kernel/arch/arm32/include/arch/cp15.h	(revision 6ff23ff32c8aa9d6ad8d06f1743ca1b0d68c14bc)
+++ kernel/arch/arm32/include/arch/cp15.h	(revision a4eb3ba2b6a831a2a639dfe74c4deb2ca435b91c)
@@ -40,5 +40,6 @@
 
 /** See ARM Architecture reference manual ch. B3.17.1 page B3-1456
- * for the list */
+ * for the list
+ */
 
 #define CONTROL_REG_GEN_READ(name, crn, opc1, crm, opc2) \
@@ -183,4 +184,6 @@
 	CCSIDR_LINESIZE_MASK = 0x7,
 	CCSIDR_LINESIZE_SHIFT = 0,
+};
+
 #define CCSIDR_SETS(val) \
 	(((val >> CCSIDR_NUMSETS_SHIFT) & CCSIDR_NUMSETS_MASK) + 1)
@@ -190,5 +193,5 @@
 #define CCSIDR_LINESIZE_LOG(val) \
 	(((val >> CCSIDR_LINESIZE_SHIFT) & CCSIDR_LINESIZE_MASK) + 2 + 2)
-};
+
 CONTROL_REG_GEN_READ(CCSIDR, c0, 1, c0, 0);
 
@@ -206,7 +209,9 @@
 	CLIDR_UNI_CACHE = 0x4,
 	CLIDR_CACHE_MASK = 0x7,
+};
+
 /** levels counted from 0 */
 #define CLIDR_CACHE(level, val)   ((val >> (level * 3)) & CLIDR_CACHE_MASK)
-};
+
 CONTROL_REG_GEN_READ(CLIDR, c0, 1, c0, 1);
 CONTROL_REG_GEN_READ(AIDR, c0, 1, c0, 7); /* Implementation defined or MIDR */
@@ -225,6 +230,8 @@
 
 /* System control registers */
-/* COntrol register bit values see ch. B4.1.130 of ARM Architecture Reference
- * Manual ARMv7-A and ARMv7-R edition, page 1687 */
+/*
+ * Control register bit values see ch. B4.1.130 of ARM Architecture Reference
+ * Manual ARMv7-A and ARMv7-R edition, page 1687
+ */
 enum {
 	SCTLR_MMU_EN_FLAG            = 1 << 0,
Index: kernel/arch/sparc64/include/arch/mm/sun4u/tsb.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4u/tsb.h	(revision 6ff23ff32c8aa9d6ad8d06f1743ca1b0d68c14bc)
+++ kernel/arch/sparc64/include/arch/mm/sun4u/tsb.h	(revision a4eb3ba2b6a831a2a639dfe74c4deb2ca435b91c)
@@ -66,13 +66,13 @@
 	uint64_t value;
 	struct {
-		uint64_t base : 51;	/**< TSB base address, bits 63:13. */
-		unsigned split : 1;	/**< Split vs. common TSB for 8K and 64K
-					 * pages. HelenOS uses only 8K pages
-					 * for user mappings, so we always set
-					 * this to 0.
-					 */
+		/** TSB base address, bits 63:13. */
+		uint64_t base : 51;
+		/** Split vs. common TSB for 8K and 64K pages. HelenOS uses
+		 * only 8K pages for user mappings, so we always set this to 0.
+		 */
+		unsigned split : 1;
 		unsigned : 9;
-		unsigned size : 3;	/**< TSB size. Number of entries is
-					 * 512 * 2^size. */
+		/** TSB size. Number of entries is 512 * 2^size. */
+		unsigned size : 3;
 	} __attribute__((packed));
 } tsb_base_reg_t;
Index: kernel/arch/sparc64/include/arch/sun4u/cpu.h
===================================================================
--- kernel/arch/sparc64/include/arch/sun4u/cpu.h	(revision 6ff23ff32c8aa9d6ad8d06f1743ca1b0d68c14bc)
+++ kernel/arch/sparc64/include/arch/sun4u/cpu.h	(revision a4eb3ba2b6a831a2a639dfe74c4deb2ca435b91c)
@@ -62,11 +62,13 @@
 
 typedef struct {
-	uint32_t mid;              /**< Processor ID as read from
-	                                UPA_CONFIG/FIREPLANE_CONFIG. */
+	/** Processor ID as read from UPA_CONFIG/FIREPLANE_CONFIG. */
+	uint32_t mid;
 	ver_reg_t ver;
-	uint32_t clock_frequency;  /**< Processor frequency in Hz. */
-	uint64_t next_tick_cmpr;   /**< Next clock interrupt should be
-	                                generated when the TICK register
-	                                matches this value. */
+	/** Processor frequency in Hz. */
+	uint32_t clock_frequency;
+	/** Next clock interrupt should be generated when the TICK register
+	 * matches this value.
+	 */
+	uint64_t next_tick_cmpr;
 } cpu_arch_t;
 
Index: kernel/arch/sparc64/include/arch/sun4v/cpu.h
===================================================================
--- kernel/arch/sparc64/include/arch/sun4v/cpu.h	(revision 6ff23ff32c8aa9d6ad8d06f1743ca1b0d68c14bc)
+++ kernel/arch/sparc64/include/arch/sun4v/cpu.h	(revision a4eb3ba2b6a831a2a639dfe74c4deb2ca435b91c)
@@ -59,12 +59,16 @@
 
 typedef struct cpu_arch {
-	uint64_t id;                  /**< virtual processor ID */
-	uint32_t clock_frequency;     /**< Processor frequency in Hz. */
-	uint64_t next_tick_cmpr;      /**< Next clock interrupt should be
-	                                   generated when the TICK register
-	                                   matches this value. */
-	exec_unit_t *exec_unit;       /**< Physical core. */
-	unsigned long proposed_nrdy;  /**< Proposed No. of ready threads
-	                                   so that cores are equally balanced. */
+	/** Virtual processor ID */
+	uint64_t id;
+	/** Processor frequency in Hz */
+	uint32_t clock_frequency;
+	/** Next clock interrupt should be generated when the TICK register
+	 * matches this value.
+	 */
+	uint64_t next_tick_cmpr;
+	/** Physical core. */
+	exec_unit_t *exec_unit;
+	/** Proposed No. of ready threads so that cores are equally balanced. */
+	unsigned long proposed_nrdy;
 } cpu_arch_t;
 
Index: kernel/arch/sparc64/src/mm/sun4u/tsb.c
===================================================================
--- kernel/arch/sparc64/src/mm/sun4u/tsb.c	(revision 6ff23ff32c8aa9d6ad8d06f1743ca1b0d68c14bc)
+++ kernel/arch/sparc64/src/mm/sun4u/tsb.c	(revision a4eb3ba2b6a831a2a639dfe74c4deb2ca435b91c)
@@ -97,7 +97,6 @@
 	 */
 
-	tte->tag.invalid = true;	/* invalidate the entry
-					 * (tag target has this
-					 * set to 0) */
+	/* Invalidate the entry (tag target has this set to 0) */
+	tte->tag.invalid = true;
 
 	write_barrier();
@@ -142,7 +141,6 @@
 	 */
 
-	tte->tag.invalid = true;	/* invalidate the entry
-					 * (tag target has this
-					 * set to 0) */
+	/* Invalidate the entry (tag target has this set to 0) */
+	tte->tag.invalid = true;
 
 	write_barrier();
Index: kernel/arch/sparc64/src/sun4v/md.c
===================================================================
--- kernel/arch/sparc64/src/sun4v/md.c	(revision 6ff23ff32c8aa9d6ad8d06f1743ca1b0d68c14bc)
+++ kernel/arch/sparc64/src/sun4v/md.c	(revision a4eb3ba2b6a831a2a639dfe74c4deb2ca435b91c)
@@ -66,10 +66,15 @@
 /** machine description element (in the node block) */
 typedef struct {
-	uint8_t tag;			/**< Type of element */
-	uint8_t name_len;		/**< Length in bytes of element name */
-	uint16_t _reserved_field;	/**< reserved field (zeros) */
-	uint32_t name_offset;		/**< Location offset of name associated
-					     with this element relative to
-					     start of name block */
+	/** Type of element */
+	uint8_t tag;
+	/** Length in bytes of element name */
+	uint8_t name_len;
+	/** Reserved field (zeros) */
+	uint16_t _reserved_field;
+	/** Location offset of name associated with this element relative to
+	 * start of name block
+	 */
+	uint32_t name_offset;
+
 	union {
 		/** for elements of type “PROP_STR” and of type “PROP_DATA” */