Index: boot/arch/arm32/include/arch/mm.h
===================================================================
--- boot/arch/arm32/include/arch/mm.h	(revision e897527842650001c9fb751fa6a1792a272858d7)
+++ boot/arch/arm32/include/arch/mm.h	(revision a4eb3ba2b6a831a2a639dfe74c4deb2ca435b91c)
@@ -71,6 +71,8 @@
 #define BCM2835_RAM_END     0x20000000
 
-/* Page table level 0 entry - "section" format is used
- * (one-level paging, 1 MB sized pages). Used only while booting the kernel.
+/** Page table level 0 entry
+ *
+ * "section" format is used (one-level paging, 1 MB sized pages).
+ * Used only while booting the kernel.
  */
 typedef struct {
Index: boot/arch/arm32/src/mm.c
===================================================================
--- boot/arch/arm32/src/mm.c	(revision e897527842650001c9fb751fa6a1792a272858d7)
+++ boot/arch/arm32/src/mm.c	(revision a4eb3ba2b6a831a2a639dfe74c4deb2ca435b91c)
@@ -210,5 +210,6 @@
 	    "mrc p15, 0, r0, c1, c0, 0\n"
 
-	    /* Enable ICache, DCache, BPredictors and MMU,
+	    /*
+	     * Enable ICache, DCache, BPredictors and MMU,
 	     * we disable caches before jumping to kernel
 	     * so this is safe for all archs.
@@ -224,5 +225,6 @@
 	    "orr r0, r0, r1\n"
 
-	    /* Invalidate the TLB content before turning on the MMU.
+	    /*
+	     * Invalidate the TLB content before turning on the MMU.
 	     * ARMv7-A Reference manual, B3.10.3
 	     */
@@ -240,8 +242,10 @@
 	disable_paging();
 #ifdef PROCESSOR_ARCH_armv7_a
-	/* Make sure we run in memory code when caches are enabled,
+	/*
+	 * Make sure we run in memory code when caches are enabled,
 	 * make sure we read memory data too. This part is ARMv7 specific as
 	 * ARMv7 no longer invalidates caches on restart.
-	 * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263*/
+	 * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263
+	 */
 	cache_invalidate();
 #endif