Index: uspace/drv/bus/usb/xhci/hw_struct/common.h
===================================================================
--- uspace/drv/bus/usb/xhci/hw_struct/common.h	(revision d09d1083210e2dc527979a5d36c7748a0d925cdb)
+++ uspace/drv/bus/usb/xhci/hw_struct/common.h	(revision a4c066e05f420fa83d520e5497bbd10bd039c8f9)
@@ -81,4 +81,11 @@
 }
 
+static inline void xhci_qword_set_bits(xhci_qword_t *storage, uint64_t value, unsigned hi, unsigned lo)
+{
+   const uint64_t mask = host2xhci(64, BIT_RANGE(uint64_t, hi, lo));
+   const uint64_t set = host2xhci(64, value << lo);
+   *storage = (*storage & ~mask) | set;
+}
+
 #endif
 
Index: uspace/drv/bus/usb/xhci/hw_struct/context.h
===================================================================
--- uspace/drv/bus/usb/xhci/hw_struct/context.h	(revision d09d1083210e2dc527979a5d36c7748a0d925cdb)
+++ uspace/drv/bus/usb/xhci/hw_struct/context.h	(revision a4c066e05f420fa83d520e5497bbd10bd039c8f9)
@@ -49,5 +49,7 @@
  */
 typedef struct xhci_endpoint_ctx {
-	xhci_dword_t data[5];
+	xhci_dword_t data[2];
+	xhci_qword_t data2;
+	xhci_dword_t data3;
 	xhci_dword_t reserved[3];
 
@@ -69,7 +71,7 @@
     xhci_dword_set_bits(&(ctx).data[1], val, 15, 8)
 #define XHCI_EP_TR_DPTR_SET(ctx, val) \
-    xhci_dword_set_bits(&(ctx).data[2], (val >> 4), 63, 4)
+    xhci_qword_set_bits(&(ctx).data2, (val >> 4), 63, 4)
 #define XHCI_EP_DCS_SET(ctx, val) \
-    xhci_dword_set_bits(&(ctx).data[2], val, 0, 0)
+    xhci_qword_set_bits(&(ctx).data2, val, 0, 0)
 #define XHCI_EP_INTERVAL_SET(ctx, val) \
     xhci_dword_set_bits(&(ctx).data[0], val, 23, 16)
@@ -93,6 +95,6 @@
 #define XHCI_EP_MAX_PACKET_SIZE(ctx)    XHCI_DWORD_EXTRACT((ctx).data[1], 31, 16)
 
-#define XHCI_EP_DCS(ctx)                XHCI_DWORD_EXTRACT((ctx).data[2],  0,  0)
-#define XHCI_EP_TR_DPTR(ctx)            XHCI_DWORD_EXTRACT((ctx).data[2], 63,  4)
+#define XHCI_EP_DCS(ctx)                XHCI_QWORD_EXTRACT((ctx).data2,  0,  0)
+#define XHCI_EP_TR_DPTR(ctx)            XHCI_QWORD_EXTRACT((ctx).data2, 63,  4)
 
 } __attribute__((packed)) xhci_ep_ctx_t;
Index: uspace/drv/bus/usb/xhci/hw_struct/trb.h
===================================================================
--- uspace/drv/bus/usb/xhci/hw_struct/trb.h	(revision d09d1083210e2dc527979a5d36c7748a0d925cdb)
+++ uspace/drv/bus/usb/xhci/hw_struct/trb.h	(revision a4c066e05f420fa83d520e5497bbd10bd039c8f9)
@@ -100,4 +100,40 @@
 #define TRB_CYCLE(trb)          XHCI_DWORD_EXTRACT((trb).control, 0, 0)
 #define TRB_LINK_TC(trb)        XHCI_DWORD_EXTRACT((trb).control, 1, 1)
+
+#define TRB_CTRL_SET_SETUP_WLENGTH(trb, val) \
+	xhci_qword_set_bits(&(trb).parameter, val, 63, 48)
+#define TRB_CTRL_SET_SETUP_WINDEX(trb, val) \
+	xhci_qword_set_bits(&(trb).parameter, val, 47, 32)
+#define TRB_CTRL_SET_SETUP_WVALUE(trb, val) \
+	xhci_qword_set_bits(&(trb).parameter, val, 31, 16)
+#define TRB_CTRL_SET_SETUP_BREQ(trb, val) \
+	xhci_qword_set_bits(&(trb).parameter, val, 15, 8)
+#define TRB_CTRL_SET_SETUP_BMREQTYPE(trb, val) \
+	xhci_qword_set_bits(&(trb).parameter, val, 7, 0)
+
+#define TRB_CTRL_SET_TD_SIZE(trb, val) \
+	xhci_dword_set_bits(&(trb).status, val, 21, 17)
+#define TRB_CTRL_SET_XFER_LEN(trb, val) \
+	xhci_dword_set_bits(&(trb).status, val, 16, 0)
+
+#define TRB_CTRL_SET_ENT(trb, val) \
+	xhci_dword_set_bits(&(trb).control, val, 1, 1)
+#define TRB_CTRL_SET_ISP(trb, val) \
+	xhci_dword_set_bits(&(trb).control, val, 2, 2)
+#define TRB_CTRL_SET_NS(trb, val) \
+	xhci_dword_set_bits(&(trb).control, val, 3, 3)
+#define TRB_CTRL_SET_CHAIN(trb, val) \
+	xhci_dword_set_bits(&(trb).control, val, 4, 4)
+#define TRB_CTRL_SET_IOC(trb, val) \
+	xhci_dword_set_bits(&(trb).control, val, 5, 5)
+#define TRB_CTRL_SET_IDT(trb, val) \
+	xhci_dword_set_bits(&(trb).control, val, 6, 6)
+
+#define TRB_CTRL_SET_TRB_TYPE(trb, val) \
+	xhci_dword_set_bits(&(trb).control, val, 15, 10)
+#define TRB_CTRL_SET_DIR(trb, val) \
+	xhci_dword_set_bits(&(trb).control, val, 16, 16)
+#define TRB_CTRL_SET_TRT(trb, val) \
+	xhci_dword_set_bits(&(trb).control, val, 17, 16)
 
 /**