Index: arch/ia32/include/atomic.h
===================================================================
--- arch/ia32/include/atomic.h	(revision 30187ebf258f432c2c4e53c8b41852e6ea4ec6b0)
+++ arch/ia32/include/atomic.h	(revision a4be38de1285764c697001298f4c806616bd32cb)
@@ -36,7 +36,7 @@
 static inline void atomic_inc(atomic_t *val) {
 #ifdef CONFIG_SMP
-	__asm__ volatile ("lock incl %0\n" : "+m" (*val));
+	__asm__ volatile ("lock incl %0\n" : "=m" (*val));
 #else
-	__asm__ volatile ("incl %0\n" : "+m" (*val));
+	__asm__ volatile ("incl %0\n" : "=m" (*val));
 #endif /* CONFIG_SMP */
 }
@@ -44,7 +44,7 @@
 static inline void atomic_dec(atomic_t *val) {
 #ifdef CONFIG_SMP
-	__asm__ volatile ("lock decl %0\n" : "+m" (*val));
+	__asm__ volatile ("lock decl %0\n" : "=m" (*val));
 #else
-	__asm__ volatile ("decl %0\n" : "+m" (*val));
+	__asm__ volatile ("decl %0\n" : "=m" (*val));
 #endif /* CONFIG_SMP */
 }
@@ -56,5 +56,5 @@
 		"movl $1,%0;"
 		"lock xaddl %0,%1;"
-		: "=r"(r), "+m" (*val)
+		: "=r"(r), "=m" (*val)
 	);
 	return r;
@@ -69,5 +69,5 @@
 		"movl $-1,%0;"
 		"lock xaddl %0,%1;"
-		: "=r"(r), "+m" (*val)
+		: "=r"(r), "=m" (*val)
 	);
 	return r;
@@ -85,5 +85,5 @@
 		"movl $1, %0\n"
 		"xchgl %0, %1\n"
-		: "=r" (v),"+m" (*val)
+		: "=r" (v),"=m" (*val)
 	);