Changeset a4afc8d in mainline

Timestamp:

2012-12-30T21:18:57Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

029e3cc

Parents:

46a6a5d

Message:

arm32: Sync boot and kernel cache handling.

File:

• boot/arch/arm32/src/mm.c (modified) (1 diff)

boot/arch/arm32/src/mm.c

@@ -125 +125 @@
                  * See Cortex-A8 TRM ch. 7.2.6 p. 7-4 (PDF 245) */
                 "ldr r1, =0x00001805\n"
+#elif defined(PROCESSOR_ARCH_armv7_a) | defined(PROCESSOR_ARCH_armv6)
+                /* Enable paging, data cache and branch prediction
+                 * see arch/arm32/src/cpu/cpu.c for reasoning */
+                "ldr r1, =0x00000805\n"
 #else
                 /* Mask to enable paging and branch prediction */