Index: arch/amd64/src/fpu_context.c
===================================================================
--- arch/amd64/src/fpu_context.c	(revision bfb87dfa5a2db236f9520a16f8ba1d59d1d9c11c)
+++ arch/amd64/src/fpu_context.c	(revision a3eeceb63abe66d5ad2d3892d18a91ad79b185fc)
@@ -57,5 +57,5 @@
 }
 
-void fpu_init(void)
+void fpu_init(fpu_context_t *fctx)
 {
 	/* TODO: Zero all SSE, MMX etc. registers */
Index: arch/ia32/src/fpu_context.c
===================================================================
--- arch/ia32/src/fpu_context.c	(revision bfb87dfa5a2db236f9520a16f8ba1d59d1d9c11c)
+++ arch/ia32/src/fpu_context.c	(revision a3eeceb63abe66d5ad2d3892d18a91ad79b185fc)
@@ -49,5 +49,5 @@
 }
 
-void fpu_init(void)
+void fpu_init(fpu_context_t *fctx)
 {
 	__asm__ volatile (
Index: arch/mips32/src/fpu_context.c
===================================================================
--- arch/mips32/src/fpu_context.c	(revision bfb87dfa5a2db236f9520a16f8ba1d59d1d9c11c)
+++ arch/mips32/src/fpu_context.c	(revision a3eeceb63abe66d5ad2d3892d18a91ad79b185fc)
@@ -51,5 +51,5 @@
 }
 
-void fpu_init(void)
+void fpu_init(fpu_context_t *fctx)
 {
 	/* TODO: Zero all registers */