Index: uspace/drv/bus/isa/i8237.c =================================================================== --- uspace/drv/bus/isa/i8237.c (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ uspace/drv/bus/isa/i8237.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -99,7 +99,7 @@ uint8_t channel_start3; uint8_t channel_count3; - + uint8_t command_status; - + /** Memory to memory transfers, NOT implemented on PCs */ uint8_t request; @@ -107,5 +107,5 @@ uint8_t mode; uint8_t flip_flop; - + /* * Master reset sets Flip-Flop low, clears status, @@ -136,5 +136,5 @@ uint8_t reserved6; uint8_t channel_count7; - + uint8_t command_status; uint8_t reserved8; @@ -230,5 +230,5 @@ .flip_flop_address = (uint8_t *) 0x0c, }, - + /* The second chip 16-bit */ { /* Channel 4 - Unusable */ @@ -265,5 +265,5 @@ }, }, - + .page_table = NULL, .first = NULL, @@ -286,21 +286,21 @@ if (ret != EOK) return EIO; - + ret = pio_enable(DMA_CONTROLLER_FIRST_BASE, sizeof(dma_controller_regs_first_t), (void **) &controller->first); if (ret != EOK) return EIO; - + ret = pio_enable(DMA_CONTROLLER_SECOND_BASE, sizeof(dma_controller_regs_second_t), (void **) &controller->second); if (ret != EOK) return EIO; - + controller->initialized = true; - + /* Reset the controller */ pio_write_8(&controller->second->master_reset, 0xff); pio_write_8(&controller->first->master_reset, 0xff); - + return EOK; } @@ -347,9 +347,9 @@ if ((channel == 0) || (channel == 4)) return ENOTSUP; - + /* DMA is limited to 24bit addresses. */ if (pa >= (1 << 24)) return EINVAL; - + /* 8 bit channels use only 4 bits from the page register. */ if (is_dma8(channel) && (pa >= (1 << 20))) @@ -359,15 +359,15 @@ if ((pa & 0xffff0000) != ((pa + size - 1) & 0xffff0000)) return EINVAL; - + fibril_mutex_lock(&guard); - + if (!controller_8237.initialized) dma_controller_init(&controller_8237); - + if (!controller_8237.initialized) { fibril_mutex_unlock(&guard); return EIO; } - + /* 16 bit transfers are a bit special */ ddf_msg(LVL_DEBUG, "Unspoiled address %#" PRIx32 " (size %" PRIu32 ")", @@ -384,15 +384,15 @@ pa = ((pa & 0xffff) >> 1) | (pa & 0xff0000); } - + const dma_channel_t dma_channel = controller_8237.channels[channel]; - + ddf_msg(LVL_DEBUG, "Setting channel %u to address %#" PRIx32 " " "(size %" PRIu32 "), mode %hhx.", channel, pa, size, mode); - + /* Mask DMA request */ uint8_t value = DMA_SINGLE_MASK_CHAN_TO_REG(channel) | DMA_SINGLE_MASK_MASKED_FLAG; pio_write_8(dma_channel.single_mask_address, value); - + /* Set mode */ value = DMA_MODE_CHAN_TO_REG(channel) | mode; @@ -400,8 +400,8 @@ dma_channel.mode_address, value); pio_write_8(dma_channel.mode_address, value); - + /* Set address - reset flip-flop */ pio_write_8(dma_channel.flip_flop_address, 0); - + /* Low byte */ value = pa & 0xff; @@ -409,5 +409,5 @@ dma_channel.offset_reg_address, value); pio_write_8(dma_channel.offset_reg_address, value); - + /* High byte */ value = (pa >> 8) & 0xff; @@ -415,5 +415,5 @@ dma_channel.offset_reg_address, value); pio_write_8(dma_channel.offset_reg_address, value); - + /* Page address - third byte */ value = (pa >> 16) & 0xff; @@ -421,8 +421,8 @@ dma_channel.page_reg_address, value); pio_write_8(dma_channel.page_reg_address, value); - + /* Set size - reset flip-flop */ pio_write_8(dma_channel.flip_flop_address, 0); - + /* Low byte */ value = (size - 1) & 0xff; @@ -430,5 +430,5 @@ dma_channel.size_reg_address, value); pio_write_8(dma_channel.size_reg_address, value); - + /* High byte */ value = ((size - 1) >> 8) & 0xff; @@ -436,11 +436,11 @@ dma_channel.size_reg_address, value); pio_write_8(dma_channel.size_reg_address, value); - + /* Unmask DMA request */ value = DMA_SINGLE_MASK_CHAN_TO_REG(channel); pio_write_8(dma_channel.single_mask_address, value); - + fibril_mutex_unlock(&guard); - + return EOK; } @@ -459,8 +459,8 @@ if (!is_dma8(channel) && !is_dma16(channel)) return ENOENT; - + if ((channel == 0) || (channel == 4)) return ENOTSUP; - + fibril_mutex_lock(&guard); if (!controller_8237.initialized) { @@ -472,10 +472,10 @@ /* Get size - reset flip-flop */ pio_write_8(dma_channel.flip_flop_address, 0); - + /* Low byte */ const uint8_t value_low = pio_read_8(dma_channel.size_reg_address); ddf_msg(LVL_DEBUG2, "Read size low byte: %p:%x.", dma_channel.size_reg_address, value_low); - + /* High byte */ const uint8_t value_high = pio_read_8(dma_channel.size_reg_address); Index: uspace/drv/bus/isa/isa.c =================================================================== --- uspace/drv/bus/isa/isa.c (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ uspace/drv/bus/isa/isa.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -402,14 +402,14 @@ size_t count = fun->hw_resources.count; hw_resource_t *resources = fun->hw_resources.resources; - + if (count < ISA_MAX_HW_RES) { if ((dma > 0) && (dma < 4)) { resources[count].type = DMA_CHANNEL_8; resources[count].res.dma_channel.dma8 = dma; - + fun->hw_resources.count++; ddf_msg(LVL_NOTE, "Added dma 0x%x to function %s", dma, ddf_fun_get_name(fun->fnode)); - + return; } @@ -418,12 +418,12 @@ resources[count].type = DMA_CHANNEL_16; resources[count].res.dma_channel.dma16 = dma; - + fun->hw_resources.count++; ddf_msg(LVL_NOTE, "Added dma 0x%x to function %s", dma, ddf_fun_get_name(fun->fnode)); - + return; } - + ddf_msg(LVL_WARN, "Skipped dma 0x%x for function %s", dma, ddf_fun_get_name(fun->fnode)); @@ -492,8 +492,8 @@ { char *end = NULL; - + val = skip_spaces(val); const int dma = strtol(val, &end, 10); - + if (val != end) isa_fun_add_dma(fun, dma); @@ -733,5 +733,5 @@ if (rc != EOK) return rc; - + rc = pio_window_get(sess, &isa->pio_win); if (rc != EOK) { Index: uspace/drv/bus/pci/pciintel/pci.c =================================================================== --- uspace/drv/bus/pci/pciintel/pci.c (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ uspace/drv/bus/pci/pciintel/pci.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -93,5 +93,5 @@ { pci_fun_t *fun = pci_fun(fnode); - + if (fun == NULL) return NULL; @@ -103,5 +103,5 @@ size_t i; hw_resource_list_t *res = &fun->hw_resources; - + for (i = 0; i < res->count; i++) { if (res->resources[i].type == INTERRUPT && @@ -110,5 +110,5 @@ } } - + return false; } @@ -117,5 +117,5 @@ { pci_fun_t *fun = pci_fun(fnode); - + if (!pciintel_fun_owns_interrupt(fun, irq)) return EINVAL; @@ -127,5 +127,5 @@ { pci_fun_t *fun = pci_fun(fnode); - + if (!pciintel_fun_owns_interrupt(fun, irq)) return EINVAL; @@ -137,5 +137,5 @@ { pci_fun_t *fun = pci_fun(fnode); - + if (!pciintel_fun_owns_interrupt(fun, irq)) return EINVAL; @@ -147,5 +147,5 @@ { pci_fun_t *fun = pci_fun(fnode); - + if (fun == NULL) return NULL; @@ -256,5 +256,5 @@ pci_bus_t *bus = pci_bus_from_fun(fun); uint32_t val; - + fibril_mutex_lock(&bus->conf_mutex); @@ -285,5 +285,5 @@ break; } - + fibril_mutex_unlock(&bus->conf_mutex); } @@ -294,5 +294,5 @@ pci_bus_t *bus = pci_bus_from_fun(fun); uint32_t val = 0; - + fibril_mutex_lock(&bus->conf_mutex); @@ -317,5 +317,5 @@ } } - + switch (len) { case 1: @@ -340,5 +340,5 @@ host2uint32_t_le(val)); } - + fibril_mutex_unlock(&bus->conf_mutex); } @@ -458,8 +458,8 @@ hw_resource_t *hw_resources = hw_res_list->resources; size_t count = hw_res_list->count; - + assert(hw_resources != NULL); assert(count < PCI_MAX_HW_RES); - + if (io) { hw_resources[count].type = IO_RANGE; @@ -475,5 +475,5 @@ hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN; } - + hw_res_list->count++; } @@ -498,10 +498,10 @@ /* 64-bit wide address */ bool addrw64; - + /* Size of the io or memory range specified by the BAR */ size_t range_size; /* Beginning of the io or memory range specified by the BAR */ uint64_t range_addr; - + /* Get the value of the BAR. */ val = pci_conf_read_32(fun, addr); @@ -509,5 +509,5 @@ #define IO_MASK (~0x3) #define MEM_MASK (~0xf) - + io = (val & 1) != 0; if (io) { @@ -528,5 +528,5 @@ } } - + /* Get the address mask. */ pci_conf_write_32(fun, addr, 0xffffffff); @@ -544,7 +544,7 @@ pci_conf_write_32(fun, addr, val); val = pci_conf_read_32(fun, addr); - + range_size = pci_bar_mask_to_size(mask); - + if (addrw64) { range_addr = ((uint64_t)pci_conf_read_32(fun, addr + 4) << 32) | @@ -553,5 +553,5 @@ range_addr = (val & 0xfffffff0); } - + if (range_addr != 0) { ddf_msg(LVL_DEBUG, "Function %s : address = %" PRIx64 @@ -559,10 +559,10 @@ (unsigned int) range_size); } - + pci_add_range(fun, range_addr, range_size, io); - + if (addrw64) return addr + 8; - + return addr + 4; } @@ -573,13 +573,13 @@ hw_resource_t *hw_resources = hw_res_list->resources; size_t count = hw_res_list->count; - + assert(NULL != hw_resources); assert(count < PCI_MAX_HW_RES); - + hw_resources[count].type = INTERRUPT; hw_resources[count].res.interrupt.irq = irq; - + hw_res_list->count++; - + ddf_msg(LVL_NOTE, "Function %s uses irq %x.", ddf_fun_get_name(fun->fnode), irq); } @@ -603,15 +603,15 @@ pci_fun_t *fun; errno_t rc; - + int child_bus = 0; int dnum, fnum; bool multi; uint8_t header_type; - + for (dnum = 0; dnum < 32; dnum++) { multi = true; for (fnum = 0; multi && fnum < 8; fnum++) { fun = pci_fun_new(bus); - + pci_fun_init(fun, bus_num, dnum, fnum); if (fun->vendor_id == 0xffff) { @@ -626,5 +626,5 @@ continue; } - + header_type = pci_conf_read_8(fun, PCI_HEADER_TYPE); if (fnum == 0) { @@ -634,5 +634,5 @@ /* Clear the multifunction bit. */ header_type = header_type & 0x7F; - + char *fun_name = pci_fun_create_name(fun); if (fun_name == NULL) { @@ -641,5 +641,5 @@ return; } - + rc = ddf_fun_set_name(fun->fnode, fun_name); free(fun_name); @@ -649,5 +649,5 @@ return; } - + pci_alloc_resource_list(fun); pci_read_bars(fun); @@ -656,12 +656,12 @@ /* Propagate the PIO window to the function. */ fun->pio_window = bus->pio_win; - + ddf_fun_set_ops(fun->fnode, &pci_fun_ops); - + ddf_msg(LVL_DEBUG, "Adding new function %s.", ddf_fun_get_name(fun->fnode)); pci_fun_create_match_ids(fun); - + if (ddf_fun_bind(fun->fnode) != EOK) { pci_clean_resource_list(fun); @@ -669,5 +669,5 @@ continue; } - + if (header_type == PCI_HEADER_TYPE_BRIDGE || header_type == PCI_HEADER_TYPE_CARDBUS) { @@ -692,7 +692,7 @@ async_sess_t *sess; errno_t rc; - + ddf_msg(LVL_DEBUG, "pci_dev_add"); - + bus = ddf_dev_data_alloc(dnode, sizeof(pci_bus_t)); if (bus == NULL) { @@ -704,5 +704,5 @@ bus->dnode = dnode; - + sess = ddf_dev_parent_sess_get(dnode); if (sess == NULL) { @@ -719,5 +719,5 @@ goto fail; } - + rc = hw_res_get_resource_list(sess, &hw_resources); if (rc != EOK) { @@ -727,6 +727,6 @@ } got_res = true; - - + + assert(hw_resources.count >= 1); @@ -745,17 +745,17 @@ goto fail; } - + } else { assert(hw_resources.resources[0].type == IO_RANGE); assert(hw_resources.resources[0].res.io_range.size >= 4); - + assert(hw_resources.resources[1].type == IO_RANGE); assert(hw_resources.resources[1].res.io_range.size >= 4); - + ddf_msg(LVL_DEBUG, "conf_addr = %" PRIx64 ".", hw_resources.resources[0].res.io_range.address); ddf_msg(LVL_DEBUG, "data_addr = %" PRIx64 ".", hw_resources.resources[1].res.io_range.address); - + if (pio_enable_resource(&bus->pio_win, &hw_resources.resources[0], @@ -775,8 +775,8 @@ } } - + /* Make the bus device more visible. It has no use yet. */ ddf_msg(LVL_DEBUG, "Adding a 'ctl' function"); - + ctl = ddf_fun_create(bus->dnode, fun_exposed, "ctl"); if (ctl == NULL) { @@ -785,5 +785,5 @@ goto fail; } - + rc = ddf_fun_bind(ctl); if (rc != EOK) { @@ -791,20 +791,20 @@ goto fail; } - + /* Enumerate functions. */ ddf_msg(LVL_DEBUG, "Scanning the bus"); pci_bus_scan(bus, 0); - + hw_res_clean_resource_list(&hw_resources); - + return EOK; - + fail: if (got_res) hw_res_clean_resource_list(&hw_resources); - + if (ctl != NULL) ddf_fun_destroy(ctl); - + return rc; } @@ -831,5 +831,5 @@ pci_fun_t *fun; ddf_fun_t *fnode; - + fnode = ddf_fun_create(bus->dnode, fun_inner, NULL); if (fnode == NULL) @@ -852,10 +852,10 @@ fun->vendor_id = pci_conf_read_16(fun, PCI_VENDOR_ID); fun->device_id = pci_conf_read_16(fun, PCI_DEVICE_ID); - + /* Explicitly enable PCI bus mastering */ fun->command = pci_conf_read_16(fun, PCI_COMMAND) | PCI_COMMAND_MASTER; pci_conf_write_16(fun, PCI_COMMAND, fun->command); - + fun->class_code = pci_conf_read_8(fun, PCI_BASE_CLASS); fun->subclass_code = pci_conf_read_8(fun, PCI_SUB_CLASS); @@ -874,5 +874,5 @@ { char *name = NULL; - + asprintf(&name, "%02x:%02x.%01x", fun->bus, fun->dev, fun->fn); @@ -903,5 +903,5 @@ */ int addr = PCI_BASE_ADDR_0; - + while (addr <= PCI_BASE_ADDR_5) addr = pci_read_bar(fun, addr); Index: uspace/drv/bus/usb/ehci/ehci_bus.h =================================================================== --- uspace/drv/bus/usb/ehci/ehci_bus.h (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ uspace/drv/bus/usb/ehci/ehci_bus.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -51,5 +51,5 @@ /** EHCI endpoint descriptor, backed by dma_buffer */ qh_t *qh; - + dma_buffer_t dma_buffer; Index: uspace/drv/bus/usb/ohci/hc.h =================================================================== --- uspace/drv/bus/usb/ohci/hc.h (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ uspace/drv/bus/usb/ohci/hc.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -64,5 +64,5 @@ /** Memory mapped I/O registers area */ ohci_regs_t *registers; - + /** Host controller communication area structure */ hcca_t *hcca; Index: uspace/drv/bus/usb/ohci/ohci_rh.c =================================================================== --- uspace/drv/bus/usb/ohci/ohci_rh.c (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ uspace/drv/bus/usb/ohci/ohci_rh.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -409,14 +409,14 @@ TEST_SIZE_INIT(0, port, hub); const unsigned feature = uint16_usb2host(setup_packet->value); - + switch (feature) { case USB_HUB_FEATURE_PORT_POWER: /*8*/ { const uint32_t rhda = OHCI_RD(hub->registers->rh_desc_a); - + /* No power switching */ if (rhda & RHDA_NPS_FLAG) return EOK; - + /* Ganged power switching, one port powers all */ if (!(rhda & RHDA_PSM_FLAG)) { Index: uspace/drv/bus/usb/usbhub/port.c =================================================================== --- uspace/drv/bus/usb/usbhub/port.c (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ uspace/drv/bus/usb/usbhub/port.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -87,5 +87,5 @@ return; } - + const errno_t err = usbhc_device_remove(exch, port->port_number); if (err) Index: uspace/drv/bus/usb/usbmid/explore.c =================================================================== --- uspace/drv/bus/usb/usbmid/explore.c (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ uspace/drv/bus/usb/usbmid/explore.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -164,5 +164,5 @@ return rc; } - + /* Create driver soft-state. */ usb_mid_t *usb_mid = usb_device_data_alloc(dev, sizeof(usb_mid_t)); Index: uspace/drv/bus/usb/vhc/conndev.c =================================================================== --- uspace/drv/bus/usb/vhc/conndev.c (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ uspace/drv/bus/usb/vhc/conndev.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -57,5 +57,5 @@ { async_exch_t *exch = async_exchange_begin(sess); - + aid_t opening_request = async_send_0(exch, IPC_M_USBVIRT_GET_NAME, NULL); if (opening_request == 0) { @@ -63,24 +63,24 @@ return; } - + ipc_call_t data_request_call; aid_t data_request = async_data_read(exch, plugged_device_name, PLUGGED_DEVICE_NAME_MAXLEN, &data_request_call); - + async_exchange_end(exch); - + if (data_request == 0) { async_forget(opening_request); return; } - + errno_t data_request_rc; errno_t opening_request_rc; async_wait_for(data_request, &data_request_rc); async_wait_for(opening_request, &opening_request_rc); - + if ((data_request_rc != EOK) || (opening_request_rc != EOK)) return; - + size_t len = IPC_GET_ARG2(data_request_call); plugged_device_name[len] = 0; @@ -97,8 +97,8 @@ { vhc_data_t *vhc = ddf_fun_data_get(fun); - + async_sess_t *callback = async_callback_receive_start(EXCHANGE_SERIALIZE, icall); - + if (callback) { errno_t rc = vhc_virtdev_plug(vhc, callback, &plugged_device_handle); @@ -108,9 +108,9 @@ return; } - + async_answer_0(icallid, EOK); - + receive_device_name(callback); - + usb_log_info("New virtual device `%s' (id: %" PRIxn ").", plugged_device_name, plugged_device_handle); Index: uspace/drv/bus/usb/vhc/hub/virthubops.c =================================================================== --- uspace/drv/bus/usb/vhc/hub/virthubops.c (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ uspace/drv/bus/usb/vhc/hub/virthubops.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -73,5 +73,5 @@ return ESTALL; } - + hub_t *hub = dev->device_data; @@ -94,5 +94,5 @@ *actual_size = 0; } - + hub->signal_changes = false; Index: uspace/drv/bus/usb/vhc/transfer.c =================================================================== --- uspace/drv/bus/usb/vhc/transfer.c (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ uspace/drv/bus/usb/vhc/transfer.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -228,5 +228,5 @@ fibril_mutex_unlock(&vhc->guard); - + if (targets > 1) usb_log_warning("Transfer would be accepted by more devices!"); Index: uspace/drv/bus/usb/xhci/debug.c =================================================================== --- uspace/drv/bus/usb/xhci/debug.c (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ uspace/drv/bus/usb/xhci/debug.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -301,5 +301,5 @@ static const char speed_exp [] = " KMG"; static const char *psi_types [] = { "", " rsvd", " RX", " TX" }; - + usb_log_debug("Speed %u%s: %5u %cb/s, %s", XHCI_REG_RD(psi, XHCI_PSI_PSIV), Index: uspace/drv/bus/usb/xhci/rh.c =================================================================== --- uspace/drv/bus/usb/xhci/rh.c (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ uspace/drv/bus/usb/xhci/rh.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -273,5 +273,5 @@ if (status != 0) usb_log_debug("RH port %u change not handled: 0x%x", port_id, status); - + /* Make sure that PSCEG is 0 before exiting the loop. */ status = XHCI_REG_RD_FIELD(&port->regs->portsc, 32);