Index: uspace/drv/bus/pci/pciintel/pci.c
===================================================================
--- uspace/drv/bus/pci/pciintel/pci.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ uspace/drv/bus/pci/pciintel/pci.c	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -93,5 +93,5 @@
 {
 	pci_fun_t *fun = pci_fun(fnode);
-	
+
 	if (fun == NULL)
 		return NULL;
@@ -103,5 +103,5 @@
 	size_t i;
 	hw_resource_list_t *res = &fun->hw_resources;
-	
+
 	for (i = 0; i < res->count; i++) {
 		if (res->resources[i].type == INTERRUPT &&
@@ -110,5 +110,5 @@
 		}
 	}
-	
+
 	return false;
 }
@@ -117,5 +117,5 @@
 {
 	pci_fun_t *fun = pci_fun(fnode);
-	
+
 	if (!pciintel_fun_owns_interrupt(fun, irq))
 		return EINVAL;
@@ -127,5 +127,5 @@
 {
 	pci_fun_t *fun = pci_fun(fnode);
-	
+
 	if (!pciintel_fun_owns_interrupt(fun, irq))
 		return EINVAL;
@@ -137,5 +137,5 @@
 {
 	pci_fun_t *fun = pci_fun(fnode);
-	
+
 	if (!pciintel_fun_owns_interrupt(fun, irq))
 		return EINVAL;
@@ -147,5 +147,5 @@
 {
 	pci_fun_t *fun = pci_fun(fnode);
-	
+
 	if (fun == NULL)
 		return NULL;
@@ -256,5 +256,5 @@
 	pci_bus_t *bus = pci_bus_from_fun(fun);
 	uint32_t val;
-	
+
 	fibril_mutex_lock(&bus->conf_mutex);
 
@@ -285,5 +285,5 @@
 		break;
 	}
-	
+
 	fibril_mutex_unlock(&bus->conf_mutex);
 }
@@ -294,5 +294,5 @@
 	pci_bus_t *bus = pci_bus_from_fun(fun);
 	uint32_t val = 0;
-	
+
 	fibril_mutex_lock(&bus->conf_mutex);
 
@@ -317,5 +317,5 @@
 		}
 	}
-	
+
 	switch (len) {
 	case 1:
@@ -340,5 +340,5 @@
 		    host2uint32_t_le(val));
 	}
-	
+
 	fibril_mutex_unlock(&bus->conf_mutex);
 }
@@ -458,8 +458,8 @@
 	hw_resource_t *hw_resources =  hw_res_list->resources;
 	size_t count = hw_res_list->count;
-	
+
 	assert(hw_resources != NULL);
 	assert(count < PCI_MAX_HW_RES);
-	
+
 	if (io) {
 		hw_resources[count].type = IO_RANGE;
@@ -475,5 +475,5 @@
 		hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
 	}
-	
+
 	hw_res_list->count++;
 }
@@ -498,10 +498,10 @@
 	/* 64-bit wide address */
 	bool addrw64;
-	
+
 	/* Size of the io or memory range specified by the BAR */
 	size_t range_size;
 	/* Beginning of the io or memory range specified by the BAR */
 	uint64_t range_addr;
-	
+
 	/* Get the value of the BAR. */
 	val = pci_conf_read_32(fun, addr);
@@ -509,5 +509,5 @@
 #define IO_MASK  (~0x3)
 #define MEM_MASK (~0xf)
-	
+
 	io = (val & 1) != 0;
 	if (io) {
@@ -528,5 +528,5 @@
 		}
 	}
-	
+
 	/* Get the address mask. */
 	pci_conf_write_32(fun, addr, 0xffffffff);
@@ -544,7 +544,7 @@
 	pci_conf_write_32(fun, addr, val);
 	val = pci_conf_read_32(fun, addr);
-	
+
 	range_size = pci_bar_mask_to_size(mask);
-	
+
 	if (addrw64) {
 		range_addr = ((uint64_t)pci_conf_read_32(fun, addr + 4) << 32) |
@@ -553,5 +553,5 @@
 		range_addr = (val & 0xfffffff0);
 	}
-	
+
 	if (range_addr != 0) {
 		ddf_msg(LVL_DEBUG, "Function %s : address = %" PRIx64
@@ -559,10 +559,10 @@
 		    (unsigned int) range_size);
 	}
-	
+
 	pci_add_range(fun, range_addr, range_size, io);
-	
+
 	if (addrw64)
 		return addr + 8;
-	
+
 	return addr + 4;
 }
@@ -573,13 +573,13 @@
 	hw_resource_t *hw_resources = hw_res_list->resources;
 	size_t count = hw_res_list->count;
-	
+
 	assert(NULL != hw_resources);
 	assert(count < PCI_MAX_HW_RES);
-	
+
 	hw_resources[count].type = INTERRUPT;
 	hw_resources[count].res.interrupt.irq = irq;
-	
+
 	hw_res_list->count++;
-	
+
 	ddf_msg(LVL_NOTE, "Function %s uses irq %x.", ddf_fun_get_name(fun->fnode), irq);
 }
@@ -603,15 +603,15 @@
 	pci_fun_t *fun;
 	errno_t rc;
-	
+
 	int child_bus = 0;
 	int dnum, fnum;
 	bool multi;
 	uint8_t header_type;
-	
+
 	for (dnum = 0; dnum < 32; dnum++) {
 		multi = true;
 		for (fnum = 0; multi && fnum < 8; fnum++) {
 			fun = pci_fun_new(bus);
-			
+
 			pci_fun_init(fun, bus_num, dnum, fnum);
 			if (fun->vendor_id == 0xffff) {
@@ -626,5 +626,5 @@
 					continue;
 			}
-			
+
 			header_type = pci_conf_read_8(fun, PCI_HEADER_TYPE);
 			if (fnum == 0) {
@@ -634,5 +634,5 @@
 			/* Clear the multifunction bit. */
 			header_type = header_type & 0x7F;
-			
+
 			char *fun_name = pci_fun_create_name(fun);
 			if (fun_name == NULL) {
@@ -641,5 +641,5 @@
 				return;
 			}
-			
+
 			rc = ddf_fun_set_name(fun->fnode, fun_name);
 			free(fun_name);
@@ -649,5 +649,5 @@
 				return;
 			}
-			
+
 			pci_alloc_resource_list(fun);
 			pci_read_bars(fun);
@@ -656,12 +656,12 @@
 			/* Propagate the PIO window to the function. */
 			fun->pio_window = bus->pio_win;
-			
+
 			ddf_fun_set_ops(fun->fnode, &pci_fun_ops);
-			
+
 			ddf_msg(LVL_DEBUG, "Adding new function %s.",
 			    ddf_fun_get_name(fun->fnode));
 
 			pci_fun_create_match_ids(fun);
-			
+
 			if (ddf_fun_bind(fun->fnode) != EOK) {
 				pci_clean_resource_list(fun);
@@ -669,5 +669,5 @@
 				continue;
 			}
-			
+
 			if (header_type == PCI_HEADER_TYPE_BRIDGE ||
 			    header_type == PCI_HEADER_TYPE_CARDBUS) {
@@ -692,7 +692,7 @@
 	async_sess_t *sess;
 	errno_t rc;
-	
+
 	ddf_msg(LVL_DEBUG, "pci_dev_add");
-	
+
 	bus = ddf_dev_data_alloc(dnode, sizeof(pci_bus_t));
 	if (bus == NULL) {
@@ -704,5 +704,5 @@
 
 	bus->dnode = dnode;
-	
+
 	sess = ddf_dev_parent_sess_get(dnode);
 	if (sess == NULL) {
@@ -719,5 +719,5 @@
 		goto fail;
 	}
-	
+
 	rc = hw_res_get_resource_list(sess, &hw_resources);
 	if (rc != EOK) {
@@ -727,6 +727,6 @@
 	}
 	got_res = true;
-	
-	
+
+
 	assert(hw_resources.count >= 1);
 
@@ -745,17 +745,17 @@
 			goto fail;
 		}
-		
+
 	} else {
 		assert(hw_resources.resources[0].type == IO_RANGE);
 		assert(hw_resources.resources[0].res.io_range.size >= 4);
-	
+
 		assert(hw_resources.resources[1].type == IO_RANGE);
 		assert(hw_resources.resources[1].res.io_range.size >= 4);
-	
+
 		ddf_msg(LVL_DEBUG, "conf_addr = %" PRIx64 ".",
 		    hw_resources.resources[0].res.io_range.address);
 		ddf_msg(LVL_DEBUG, "data_addr = %" PRIx64 ".",
 		    hw_resources.resources[1].res.io_range.address);
-	
+
 		if (pio_enable_resource(&bus->pio_win,
 		    &hw_resources.resources[0],
@@ -775,8 +775,8 @@
 		}
 	}
-	
+
 	/* Make the bus device more visible. It has no use yet. */
 	ddf_msg(LVL_DEBUG, "Adding a 'ctl' function");
-	
+
 	ctl = ddf_fun_create(bus->dnode, fun_exposed, "ctl");
 	if (ctl == NULL) {
@@ -785,5 +785,5 @@
 		goto fail;
 	}
-	
+
 	rc = ddf_fun_bind(ctl);
 	if (rc != EOK) {
@@ -791,20 +791,20 @@
 		goto fail;
 	}
-	
+
 	/* Enumerate functions. */
 	ddf_msg(LVL_DEBUG, "Scanning the bus");
 	pci_bus_scan(bus, 0);
-	
+
 	hw_res_clean_resource_list(&hw_resources);
-	
+
 	return EOK;
-	
+
 fail:
 	if (got_res)
 		hw_res_clean_resource_list(&hw_resources);
-	
+
 	if (ctl != NULL)
 		ddf_fun_destroy(ctl);
-	
+
 	return rc;
 }
@@ -831,5 +831,5 @@
 	pci_fun_t *fun;
 	ddf_fun_t *fnode;
-	
+
 	fnode = ddf_fun_create(bus->dnode, fun_inner, NULL);
 	if (fnode == NULL)
@@ -852,10 +852,10 @@
 	fun->vendor_id = pci_conf_read_16(fun, PCI_VENDOR_ID);
 	fun->device_id = pci_conf_read_16(fun, PCI_DEVICE_ID);
-	
+
 	/* Explicitly enable PCI bus mastering */
 	fun->command = pci_conf_read_16(fun, PCI_COMMAND) |
 	    PCI_COMMAND_MASTER;
 	pci_conf_write_16(fun, PCI_COMMAND, fun->command);
-	
+
 	fun->class_code = pci_conf_read_8(fun, PCI_BASE_CLASS);
 	fun->subclass_code = pci_conf_read_8(fun, PCI_SUB_CLASS);
@@ -874,5 +874,5 @@
 {
 	char *name = NULL;
-	
+
 	asprintf(&name, "%02x:%02x.%01x", fun->bus, fun->dev,
 	    fun->fn);
@@ -903,5 +903,5 @@
 	 */
 	int addr = PCI_BASE_ADDR_0;
-	
+
 	while (addr <= PCI_BASE_ADDR_5)
 		addr = pci_read_bar(fun, addr);
