Index: kernel/arch/abs32le/include/arch/asm.h =================================================================== --- kernel/arch/abs32le/include/arch/asm.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/abs32le/include/arch/asm.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -50,5 +50,5 @@ low-power mode) without any possibility of exitting this function. */ - + while (true); } @@ -137,5 +137,5 @@ * The return value stores the previous interrupt level. */ - + return 0; } @@ -151,5 +151,5 @@ * The return value stores the previous interrupt level. */ - + return 0; } @@ -169,5 +169,5 @@ * level. */ - + return 0; } @@ -179,5 +179,5 @@ * disabled. */ - + return false; } @@ -192,5 +192,5 @@ * address space. */ - + return 0; } Index: kernel/arch/abs32le/include/arch/atomic.h =================================================================== --- kernel/arch/abs32le/include/arch/atomic.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/abs32le/include/arch/atomic.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -49,5 +49,5 @@ /* On real hardware the increment has to be done as an atomic action. */ - + val->count++; } @@ -60,5 +60,5 @@ /* On real hardware the decrement has to be done as an atomic action. */ - + val->count--; } @@ -72,7 +72,7 @@ value and the increment have to be done as a single atomic action. */ - + atomic_count_t prev = val->count; - + val->count++; return prev; @@ -87,7 +87,7 @@ value and the decrement have to be done as a single atomic action. */ - + atomic_count_t prev = val->count; - + val->count--; return prev; @@ -104,5 +104,5 @@ value and storing 1 have to be done as a single atomic action. */ - + atomic_count_t prev = val->count; val->count = 1; Index: kernel/arch/abs32le/include/arch/istate.h =================================================================== --- kernel/arch/abs32le/include/arch/istate.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/abs32le/include/arch/istate.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -67,5 +67,5 @@ /* On real hardware this checks whether the interrupted context originated from user space. */ - + return !(istate->ip & UINT32_C(0x80000000)); } @@ -76,5 +76,5 @@ { /* On real hardware this sets the instruction pointer. */ - + istate->ip = retaddr; } @@ -84,5 +84,5 @@ { /* On real hardware this returns the instruction pointer. */ - + return istate->ip; } @@ -92,5 +92,5 @@ { /* On real hardware this returns the frame pointer. */ - + return istate->fp; } Index: kernel/arch/abs32le/include/arch/mm/page.h =================================================================== --- kernel/arch/abs32le/include/arch/mm/page.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/abs32le/include/arch/mm/page.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -140,5 +140,5 @@ unsigned int pat : 1; unsigned int global : 1; - + /** Valid content even if the present bit is not set. */ unsigned int soft_valid : 1; @@ -151,5 +151,5 @@ { pte_t *p = &pt[i]; - + return ( ((unsigned int) (!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT) | @@ -168,5 +168,5 @@ { pte_t *p = &pt[i]; - + p->page_cache_disable = !(flags & PAGE_CACHEABLE); p->present = !(flags & PAGE_NOT_PRESENT); @@ -174,5 +174,5 @@ p->writeable = (flags & PAGE_WRITE) != 0; p->global = (flags & PAGE_GLOBAL) != 0; - + /* * Ensure that there is at least one bit set even if the present bit is Index: kernel/arch/abs32le/src/abs32le.c =================================================================== --- kernel/arch/abs32le/src/abs32le.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/abs32le/src/abs32le.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -65,5 +65,5 @@ /* Initialize IRQ routing */ irq_init(0, 0); - + /* Merge all memory zones to 1 big zone */ zone_merge_all(); Index: kernel/arch/abs32le/src/userspace.c =================================================================== --- kernel/arch/abs32le/src/userspace.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/abs32le/src/userspace.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -43,5 +43,5 @@ /* On real hardware this switches the CPU to user space mode and jumps to kernel_uarg->uspace_entry. */ - + while (true); } Index: kernel/arch/amd64/include/arch/asm.h =================================================================== --- kernel/arch/amd64/include/arch/asm.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/amd64/include/arch/asm.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -53,5 +53,5 @@ { uintptr_t v; - + asm volatile ( "andq %%rsp, %[v]\n" @@ -59,5 +59,5 @@ : "0" (~((uint64_t) STACK_SIZE - 1)) ); - + return v; } @@ -91,5 +91,5 @@ if (port < (ioport8_t *) IO_SPACE_BOUNDARY) { uint8_t val; - + asm volatile ( "inb %w[port], %b[val]\n" @@ -97,5 +97,5 @@ : [port] "d" (port) ); - + return val; } else @@ -115,5 +115,5 @@ if (port < (ioport16_t *) IO_SPACE_BOUNDARY) { uint16_t val; - + asm volatile ( "inw %w[port], %w[val]\n" @@ -121,5 +121,5 @@ : [port] "d" (port) ); - + return val; } else @@ -139,5 +139,5 @@ if (port < (ioport32_t *) IO_SPACE_BOUNDARY) { uint32_t val; - + asm volatile ( "inl %w[port], %[val]\n" @@ -145,5 +145,5 @@ : [port] "d" (port) ); - + return val; } else @@ -252,7 +252,7 @@ { ipl_t ipl = interrupts_read(); - + asm volatile ("sti\n"); - + return ipl; } @@ -268,7 +268,7 @@ { ipl_t ipl = interrupts_read(); - + asm volatile ("cli\n"); - + return ipl; } @@ -310,5 +310,5 @@ { uint32_t ax, dx; - + asm volatile ( "rdmsr\n" @@ -316,5 +316,5 @@ : "c" (msr) ); - + return ((uint64_t) dx << 32) | ax; } Index: kernel/arch/amd64/include/arch/atomic.h =================================================================== --- kernel/arch/amd64/include/arch/atomic.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/amd64/include/arch/atomic.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -74,5 +74,5 @@ { atomic_count_t r = 1; - + asm volatile ( "lock xaddq %[r], %[count]\n" @@ -80,5 +80,5 @@ [r] "+r" (r) ); - + return r; } @@ -87,5 +87,5 @@ { atomic_count_t r = -1; - + asm volatile ( "lock xaddq %[r], %[count]\n" @@ -93,5 +93,5 @@ [r] "+r" (r) ); - + return r; } @@ -103,5 +103,5 @@ { atomic_count_t v = 1; - + asm volatile ( "xchgq %[v], %[count]\n" @@ -109,5 +109,5 @@ [count] "+m" (val->count) ); - + return v; } @@ -117,5 +117,5 @@ { atomic_count_t tmp; - + preemption_disable(); asm volatile ( @@ -125,5 +125,5 @@ " testq %[tmp], %[tmp]\n" " jnz 0b\n" /* lightweight looping on locked spinlock */ - + " incq %[tmp]\n" /* now use the atomic operation */ " xchgq %[count], %[tmp]\n" @@ -133,5 +133,5 @@ [tmp] "=&r" (tmp) ); - + /* * Prevent critical section code from bleeding out this way up. Index: kernel/arch/amd64/include/arch/cpu.h =================================================================== --- kernel/arch/amd64/include/arch/cpu.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/amd64/include/arch/cpu.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -89,7 +89,7 @@ int stepping; tss_t *tss; - + unsigned int id; /** CPU's local, ie physical, APIC ID. */ - + size_t iomapver_copy; /** Copy of TASK's I/O Permission bitmap generation count. */ } cpu_arch_t; Index: kernel/arch/amd64/include/arch/cycle.h =================================================================== --- kernel/arch/amd64/include/arch/cycle.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/amd64/include/arch/cycle.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -42,5 +42,5 @@ uint32_t lower; uint32_t upper; - + asm volatile ( "rdtsc\n" @@ -48,5 +48,5 @@ "=d" (upper) ); - + return ((uint64_t) lower) | (((uint64_t) upper) << 32); } Index: kernel/arch/amd64/include/arch/mm/page.h =================================================================== --- kernel/arch/amd64/include/arch/mm/page.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/amd64/include/arch/mm/page.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -210,5 +210,5 @@ { pte_t *p = &pt[i]; - + return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT | (!p->present) << PAGE_PRESENT_SHIFT | @@ -223,5 +223,5 @@ { pte_t *p = &pt[i]; - + p->addr_12_31 = (a >> 12) & UINT32_C(0xfffff); p->addr_32_51 = a >> 32; @@ -231,5 +231,5 @@ { pte_t *p = &pt[i]; - + p->page_cache_disable = !(flags & PAGE_CACHEABLE); p->present = !(flags & PAGE_NOT_PRESENT); @@ -238,5 +238,5 @@ p->no_execute = (flags & PAGE_EXEC) == 0; p->global = (flags & PAGE_GLOBAL) != 0; - + /* * Ensure that there is at least one bit set even if the present bit is cleared. Index: kernel/arch/amd64/src/amd64.c =================================================================== --- kernel/arch/amd64/src/amd64.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/amd64/src/amd64.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -92,5 +92,5 @@ multiboot_info_parse(signature, (multiboot_info_t *) info); multiboot2_info_parse(signature, (multiboot2_info_t *) info); - + #ifdef CONFIG_SMP /* Copy AP bootstrap routines below 1 MB. */ @@ -106,17 +106,17 @@ /* Enable FPU */ cpu_setup_fpu(); - + /* Initialize segmentation */ pm_init(); - + /* Disable I/O on nonprivileged levels, clear the nested-thread flag */ write_rflags(read_rflags() & ~(RFLAGS_IOPL | RFLAGS_NT)); /* Disable alignment check */ write_cr0(read_cr0() & ~CR0_AM); - + if (config.cpu_active == 1) { interrupt_init(); bios_init(); - + /* PIC */ i8259_init(); @@ -132,16 +132,16 @@ /* Initialize IRQ routing */ irq_init(IRQ_COUNT, IRQ_COUNT); - + /* hard clock */ i8254_init(); - + #if (defined(CONFIG_FB) || defined(CONFIG_EGA)) bool bfb = false; #endif - + #ifdef CONFIG_FB bfb = bfb_init(); #endif - + #ifdef CONFIG_EGA if (!bfb) { @@ -151,9 +151,9 @@ } #endif - + /* Merge all memory zones to 1 big zone */ zone_merge_all(); } - + /* Setup fast SYSCALL/SYSRET */ syscall_setup_cpu(); @@ -235,5 +235,5 @@ } #endif - + if (irqs_info != NULL) sysinfo_set_item_val(irqs_info, NULL, true); Index: kernel/arch/amd64/src/asm.S =================================================================== --- kernel/arch/amd64/src/asm.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/amd64/src/asm.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -60,16 +60,16 @@ FUNCTION_BEGIN(memcpy_to_uspace) movq MEMCPY_DST, %rax - + movq MEMCPY_SIZE, %rcx shrq $3, %rcx /* size / 8 */ - + rep movsq /* copy as much as possible word by word */ - + movq MEMCPY_SIZE, %rcx andq $7, %rcx /* size % 8 */ jz 0f - + rep movsb /* copy the rest byte by byte */ - + 0: ret /* return MEMCPY_SRC, success */ @@ -92,18 +92,18 @@ popq %rax movq %rax, %rdx - + /* Flip the ID bit */ xorl $RFLAGS_ID, %edx - + /* Store RFLAGS */ pushq %rdx popfq pushfq - + /* Get the ID bit again */ popq %rdx andl $RFLAGS_ID, %eax andl $RFLAGS_ID, %edx - + /* 0 if not supported, 1 if supported */ xorl %edx, %eax @@ -114,8 +114,8 @@ /* Preserve %rbx across function calls */ movq %rbx, %r10 - + /* Load the command into %eax */ movl %edi, %eax - + cpuid movl %eax, 0(%rsi) @@ -123,5 +123,5 @@ movl %ecx, 8(%rsi) movl %edx, 12(%rsi) - + movq %r10, %rbx ret @@ -161,5 +161,5 @@ * code. */ - + .iflt \i-32 .if (1 << \i) & ERROR_WORD_INTERRUPT_LIST @@ -180,5 +180,5 @@ subq $(ISTATE_SOFT_SIZE + 8), %rsp .endif - + /* * Save the general purpose registers. @@ -230,5 +230,5 @@ movq $(\i), %rdi /* pass intnum in the first argument */ movq %rsp, %rsi /* pass istate address in the second argument */ - + cld @@ -250,5 +250,5 @@ movq ISTATE_OFFSET_R10(%rsp), %r10 movq ISTATE_OFFSET_R11(%rsp), %r11 - + /* $8 = Skip error word */ addq $(ISTATE_SOFT_SIZE + 8), %rsp @@ -288,5 +288,5 @@ /* Switch to hidden %gs */ swapgs - + movq %rsp, %gs:KSEG_OFFSET_USTACK_RSP /* save this thread's user RSP */ movq %gs:KSEG_OFFSET_KSTACK_RSP, %rsp /* set this thread's kernel RSP */ @@ -346,5 +346,5 @@ swapgs sti - + /* Copy the 4th argument where it is expected */ movq %r10, %rcx @@ -364,5 +364,5 @@ cli - + /* * Restore registers needed for return via the SYSRET instruction and @@ -394,5 +394,5 @@ callq fault_from_uspace /* not reached */ - + bad_rip_msg: .asciz "Invalid instruction pointer." @@ -414,89 +414,89 @@ FUNCTION_BEGIN(early_putchar) #if ((defined(CONFIG_EGA)) && (!defined(CONFIG_FB))) - + /* Prologue, save preserved registers */ pushq %rbp movq %rsp, %rbp pushq %rbx - + movq %rdi, %rsi movq $(PA2KA(0xb8000)), %rdi /* base of EGA text mode memory */ xorl %eax, %eax - + /* Read bits 8 - 15 of the cursor address */ movw $0x3d4, %dx movb $0xe, %al outb %al, %dx - + movw $0x3d5, %dx inb %dx, %al shl $8, %ax - + /* Read bits 0 - 7 of the cursor address */ movw $0x3d4, %dx movb $0xf, %al outb %al, %dx - + movw $0x3d5, %dx inb %dx, %al - + /* Sanity check for the cursor on screen */ cmp $2000, %ax jb early_putchar_cursor_ok - + movw $1998, %ax - + early_putchar_cursor_ok: - + movw %ax, %bx shl $1, %rax addq %rax, %rdi - + movq %rsi, %rax - + cmp $0x0a, %al jne early_putchar_backspace - + /* Interpret newline */ - + movw %bx, %ax /* %bx -> %dx:%ax */ xorw %dx, %dx - + movw $80, %cx idivw %cx, %ax /* %dx = %bx % 80 */ - + /* %bx <- %bx + 80 - (%bx % 80) */ addw %cx, %bx subw %dx, %bx - + jmp early_putchar_skip - + early_putchar_backspace: - + cmp $0x08, %al jne early_putchar_print - + /* Interpret backspace */ - + cmp $0x0000, %bx je early_putchar_skip - + dec %bx jmp early_putchar_skip - + early_putchar_print: - + /* Print character */ - + movb $0x0e, %ah /* black background, yellow foreground */ stosw inc %bx - + early_putchar_skip: - + /* Sanity check for the cursor on the last line */ cmp $2000, %bx jb early_putchar_no_scroll - + /* Scroll the screen (24 rows) */ movq $(PA2KA(0xb80a0)), %rsi @@ -504,39 +504,39 @@ movl $480, %ecx rep movsq - + /* Clear the 24th row */ xorl %eax, %eax movl $20, %ecx rep stosq - + /* Go to row 24 */ movw $1920, %bx - + early_putchar_no_scroll: - + /* Write bits 8 - 15 of the cursor address */ movw $0x3d4, %dx movb $0xe, %al outb %al, %dx - + movw $0x3d5, %dx movb %bh, %al outb %al, %dx - + /* Write bits 0 - 7 of the cursor address */ movw $0x3d4, %dx movb $0xf, %al outb %al, %dx - + movw $0x3d5, %dx movb %bl, %al outb %al, %dx - + /* Epilogue, restore preserved registers */ popq %rbx leave - + #endif - + ret FUNCTION_END(early_putchar) Index: kernel/arch/amd64/src/boot/multiboot.S =================================================================== --- kernel/arch/amd64/src/boot/multiboot.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/amd64/src/boot/multiboot.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -78,8 +78,8 @@ cli cld - + /* Initialize stack pointer */ movl $START_STACK, %esp - + /* * Initialize Global Descriptor Table and @@ -88,5 +88,5 @@ lgdtl bootstrap_gdtr lidtl bootstrap_idtr - + /* Kernel data + stack */ movw $GDT_SELECTOR(KDATA_DES), %cx @@ -94,5 +94,5 @@ movw %cx, %ds movw %cx, %ss - + /* * Simics seems to remove hidden part of GS on entering user mode @@ -102,77 +102,77 @@ movw %cx, %fs movw %cx, %gs - + jmpl $GDT_SELECTOR(KTEXT32_DES), $multiboot_meeting_point multiboot_meeting_point: - + /* * Protected 32-bit. We want to reuse the code-seg descriptor, * the Default operand size must not be 1 when entering long mode. */ - + /* Save multiboot arguments */ movl %eax, multiboot_eax movl %ebx, multiboot_ebx - + pm_status $status_prot - + movl $(INTEL_CPUID_EXTENDED), %eax cpuid cmp $(INTEL_CPUID_EXTENDED), %eax ja extended_cpuid_supported - + pm_error $err_extended_cpuid - + extended_cpuid_supported: - + movl $(AMD_CPUID_EXTENDED), %eax cpuid bt $(AMD_EXT_LONG_MODE), %edx jc long_mode_supported - + pm_error $err_long_mode - + long_mode_supported: - + bt $(AMD_EXT_NOEXECUTE), %edx jc noexecute_supported - + pm_error $err_noexecute - + noexecute_supported: - + movl $(INTEL_CPUID_STANDARD), %eax cpuid bt $(INTEL_FXSAVE), %edx jc fx_supported - + pm_error $err_fx - + fx_supported: - + bt $(INTEL_SSE2), %edx jc sse2_supported - + pm_error $err_sse2 - + sse2_supported: - + #include "vesa_prot.inc" - + pm2_status $status_prot2 - + /* * Enable 64-bit page translation entries - CR4.PAE = 1. * Paging is not enabled until after long mode is enabled. */ - + movl %cr4, %eax orl $CR4_PAE, %eax movl %eax, %cr4 - + /* Set up paging tables */ leal ptl_0, %eax movl %eax, %cr3 - + /* Enable long mode */ movl $AMD_MSR_EFER, %ecx @@ -180,10 +180,10 @@ orl $AMD_LME, %eax /* set LME = 1 */ wrmsr - + /* Enable paging to activate long mode (set CR0.PG = 1) */ movl %cr0, %eax orl $CR0_PG, %eax movl %eax, %cr0 - + /* At this point we are in compatibility mode */ jmpl $GDT_SELECTOR(KTEXT_DES), $start64 @@ -204,48 +204,48 @@ movl $0xb8000, %edi /* base of EGA text mode memory */ xorl %eax, %eax - + /* Read bits 8 - 15 of the cursor address */ movw $0x3d4, %dx movb $0xe, %al outb %al, %dx - + movw $0x3d5, %dx inb %dx, %al shl $8, %ax - + /* Read bits 0 - 7 of the cursor address */ movw $0x3d4, %dx movb $0xf, %al outb %al, %dx - + movw $0x3d5, %dx inb %dx, %al - + /* Sanity check for the cursor on screen */ cmp $2000, %ax jb err_cursor_ok - + movw $1998, %ax - + err_cursor_ok: - + movw %ax, %bx shl $1, %eax addl %eax, %edi - + err_ploop: lodsb - + cmp $0, %al je err_ploop_end - + movb $0x0c, %ah /* black background, light red foreground */ stosw - + /* Sanity check for the cursor on the last line */ inc %bx cmp $2000, %bx jb err_ploop - + /* Scroll the screen (24 rows) */ movl %esi, %edx @@ -254,36 +254,36 @@ movl $960, %ecx rep movsl - + /* Clear the 24th row */ xorl %eax, %eax movl $40, %ecx rep stosl - + /* Go to row 24 */ movl %edx, %esi movl $0xb8f00, %edi movw $1920, %bx - + jmp err_ploop err_ploop_end: - + /* Write bits 8 - 15 of the cursor address */ movw $0x3d4, %dx movb $0xe, %al outb %al, %dx - + movw $0x3d5, %dx movb %bh, %al outb %al, %dx - + /* Write bits 0 - 7 of the cursor address */ movw $0x3d4, %dx movb $0xf, %al outb %al, %dx - + movw $0x3d5, %dx movb %bl, %al outb %al, %dx - + cli hlt1: @@ -311,51 +311,51 @@ pushl %edx pushl %edi - + movl $0xb8000, %edi /* base of EGA text mode memory */ xorl %eax, %eax - + /* Read bits 8 - 15 of the cursor address */ movw $0x3d4, %dx movb $0xe, %al outb %al, %dx - + movw $0x3d5, %dx inb %dx, %al shl $8, %ax - + /* Read bits 0 - 7 of the cursor address */ movw $0x3d4, %dx movb $0xf, %al outb %al, %dx - + movw $0x3d5, %dx inb %dx, %al - + /* Sanity check for the cursor on screen */ cmp $2000, %ax jb pm_puts_cursor_ok - + movw $1998, %ax - + pm_puts_cursor_ok: - + movw %ax, %bx shl $1, %eax addl %eax, %edi - + pm_puts_ploop: lodsb - + cmp $0, %al je pm_puts_ploop_end - + movb $0x0a, %ah /* black background, light green foreground */ stosw - + /* Sanity check for the cursor on the last line */ inc %bx cmp $2000, %bx jb pm_puts_ploop - + /* Scroll the screen (24 rows) */ movl %esi, %edx @@ -364,36 +364,36 @@ movl $960, %ecx rep movsl - + /* Clear the 24th row */ xorl %eax, %eax movl $40, %ecx rep stosl - + /* Go to row 24 */ movl %edx, %esi movl $0xb8f00, %edi movw $1920, %bx - + jmp pm_puts_ploop pm_puts_ploop_end: - + /* Write bits 8 - 15 of the cursor address */ movw $0x3d4, %dx movb $0xe, %al outb %al, %dx - + movw $0x3d5, %dx movb %bh, %al outb %al, %dx - + /* Write bits 0 - 7 of the cursor address */ movw $0x3d4, %dx movb $0xf, %al outb %al, %dx - + movw $0x3d5, %dx movb %bl, %al outb %al, %dx - + popl %edi popl %edx @@ -401,5 +401,5 @@ popl %ebx popl %eax - + ret @@ -414,21 +414,21 @@ start64: - + /* * Long mode. */ - + movq $(PA2KA(START_STACK)), %rsp - + /* Create the first stack frame */ pushq $0 movq %rsp, %rbp - + long_status $status_long - + /* Call amd64_pre_main(multiboot_eax, multiboot_ebx) */ movl multiboot_eax, %edi movl multiboot_ebx, %esi - + #ifdef MEMORY_MODEL_large movabsq $amd64_pre_main, %rax @@ -437,7 +437,7 @@ callq amd64_pre_main #endif - + long_status $status_main - + /* Call main_bsp() */ #ifdef MEMORY_MODEL_large @@ -447,5 +447,5 @@ callq main_bsp #endif - + /* Not reached */ cli @@ -468,59 +468,59 @@ */ early_puts: - + #if ((defined(CONFIG_EGA)) && (!defined(CONFIG_FB))) - + /* Prologue, save preserved registers */ pushq %rbp movq %rsp, %rbp pushq %rbx - + movq %rdi, %rsi movq $(PA2KA(0xb8000)), %rdi /* base of EGA text mode memory */ xorq %rax, %rax - + /* Read bits 8 - 15 of the cursor address */ movw $0x3d4, %dx movb $0xe, %al outb %al, %dx - + movw $0x3d5, %dx inb %dx, %al shl $8, %ax - + /* Read bits 0 - 7 of the cursor address */ movw $0x3d4, %dx movb $0xf, %al outb %al, %dx - + movw $0x3d5, %dx inb %dx, %al - + /* Sanity check for the cursor on screen */ cmp $2000, %ax jb early_puts_cursor_ok - + movw $1998, %ax - + early_puts_cursor_ok: - + movw %ax, %bx shl $1, %rax addq %rax, %rdi - + early_puts_ploop: lodsb - + cmp $0, %al je early_puts_ploop_end - + movb $0x0e, %ah /* black background, yellow foreground */ stosw - + /* Sanity check for the cursor on the last line */ inc %bx cmp $2000, %bx jb early_puts_ploop - + /* Scroll the screen (24 rows) */ movq %rsi, %rdx @@ -529,42 +529,42 @@ movl $480, %ecx rep movsq - + /* Clear the 24th row */ xorl %eax, %eax movl $20, %ecx rep stosq - + /* Go to row 24 */ movq %rdx, %rsi movq $(PA2KA(0xb8f00)), %rdi movw $1920, %bx - + jmp early_puts_ploop early_puts_ploop_end: - + /* Write bits 8 - 15 of the cursor address */ movw $0x3d4, %dx movb $0xe, %al outb %al, %dx - + movw $0x3d5, %dx movb %bh, %al outb %al, %dx - + /* Write bits 0 - 7 of the cursor address */ movw $0x3d4, %dx movb $0xf, %al outb %al, %dx - + movw $0x3d5, %dx movb %bl, %al outb %al, %dx - + /* Epilogue, restore preserved registers */ popq %rbx leave - + #endif - + ret Index: kernel/arch/amd64/src/boot/multiboot2.S =================================================================== --- kernel/arch/amd64/src/boot/multiboot2.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/amd64/src/boot/multiboot2.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -47,5 +47,5 @@ .long multiboot2_header_end - multiboot2_header_start .long -(MULTIBOOT2_HEADER_MAGIC + MULTIBOOT2_HEADER_ARCH_I386 + (multiboot2_header_end - multiboot2_header_start)) - + /* Information request tag */ .align 8 @@ -61,5 +61,5 @@ #endif tag_info_req_end: - + /* Address tag */ .align 8 @@ -73,5 +73,5 @@ .long 0 tag_address_end: - + /* Entry address tag */ .align 8 @@ -82,5 +82,5 @@ .long multiboot2_image_start tag_entry_address_end: - + /* Flags tag */ .align 8 @@ -91,5 +91,5 @@ .long MULTIBOOT2_FLAGS_CONSOLE tag_flags_end: - + #ifdef CONFIG_FB /* Framebuffer tag */ @@ -104,5 +104,5 @@ tag_framebuffer_end: #endif - + /* Module alignment tag */ .align 8 @@ -113,5 +113,5 @@ .long 0 tag_module_align_end: - + /* Tag terminator */ .align 8 @@ -126,8 +126,8 @@ cli cld - + /* Initialize stack pointer */ movl $START_STACK, %esp - + /* * Initialize Global Descriptor Table and @@ -136,5 +136,5 @@ lgdtl bootstrap_gdtr lidtl bootstrap_idtr - + /* Kernel data + stack */ movw $GDT_SELECTOR(KDATA_DES), %cx @@ -142,5 +142,5 @@ movw %cx, %ds movw %cx, %ss - + /* * Simics seems to remove hidden part of GS on entering user mode @@ -150,71 +150,71 @@ movw %cx, %fs movw %cx, %gs - + jmpl $GDT_SELECTOR(KTEXT32_DES), $multiboot2_meeting_point multiboot2_meeting_point: - + /* * Protected 32-bit. We want to reuse the code-seg descriptor, * the Default operand size must not be 1 when entering long mode. */ - + /* Save multiboot arguments */ movl %eax, multiboot_eax movl %ebx, multiboot_ebx - + movl $(INTEL_CPUID_EXTENDED), %eax cpuid cmp $(INTEL_CPUID_EXTENDED), %eax ja extended_cpuid_supported - - jmp pm_error_halt - + + jmp pm_error_halt + extended_cpuid_supported: - + movl $(AMD_CPUID_EXTENDED), %eax cpuid bt $(AMD_EXT_LONG_MODE), %edx jc long_mode_supported - - jmp pm_error_halt - + + jmp pm_error_halt + long_mode_supported: - + bt $(AMD_EXT_NOEXECUTE), %edx jc noexecute_supported - - jmp pm_error_halt - + + jmp pm_error_halt + noexecute_supported: - + movl $(INTEL_CPUID_STANDARD), %eax cpuid bt $(INTEL_FXSAVE), %edx jc fx_supported - - jmp pm_error_halt - + + jmp pm_error_halt + fx_supported: - + bt $(INTEL_SSE2), %edx jc sse2_supported - - jmp pm_error_halt - + + jmp pm_error_halt + sse2_supported: - + /* * Enable 64-bit page translation entries - CR4.PAE = 1. * Paging is not enabled until after long mode is enabled. */ - + movl %cr4, %eax orl $CR4_PAE, %eax movl %eax, %cr4 - + /* Set up paging tables */ leal ptl_0, %eax movl %eax, %cr3 - + /* Enable long mode */ movl $AMD_MSR_EFER, %ecx @@ -222,10 +222,10 @@ orl $AMD_LME, %eax /* set LME = 1 */ wrmsr - + /* Enable paging to activate long mode (set CR0.PG = 1) */ movl %cr0, %eax orl $CR0_PG, %eax movl %eax, %cr0 - + /* At this point we are in compatibility mode */ jmpl $GDT_SELECTOR(KTEXT_DES), $start64 @@ -240,19 +240,19 @@ start64: - + /* * Long mode. */ - + movq $(PA2KA(START_STACK)), %rsp - + /* Create the first stack frame */ pushq $0 movq %rsp, %rbp - + /* Call amd64_pre_main(multiboot_eax, multiboot_ebx) */ movl multiboot_eax, %edi movl multiboot_ebx, %esi - + #ifdef MEMORY_MODEL_large movabsq $amd64_pre_main, %rax @@ -261,5 +261,5 @@ callq amd64_pre_main #endif - + /* Call main_bsp() */ #ifdef MEMORY_MODEL_large @@ -269,5 +269,5 @@ callq main_bsp #endif - + /* Not reached */ cli Index: kernel/arch/amd64/src/context.S =================================================================== --- kernel/arch/amd64/src/context.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/amd64/src/context.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -40,8 +40,8 @@ FUNCTION_BEGIN(context_save_arch) movq (%rsp), %rdx # the caller's return %rip - + movq %rdx, CONTEXT_OFFSET_PC(%rdi) movq %rsp, CONTEXT_OFFSET_SP(%rdi) - + movq %rbx, CONTEXT_OFFSET_RBX(%rdi) movq %rbp, CONTEXT_OFFSET_RBP(%rdi) @@ -50,5 +50,5 @@ movq %r14, CONTEXT_OFFSET_R14(%rdi) movq %r15, CONTEXT_OFFSET_R15(%rdi) - + #ifdef MEMORY_MODEL_large movabsq $vreg_ptr, %rsi @@ -59,5 +59,5 @@ movq %fs:VREG_TP(%rsi), %rsi movq %rsi, CONTEXT_OFFSET_TP(%rdi) - + xorl %eax, %eax # context_save returns 1 incl %eax @@ -78,10 +78,10 @@ movq CONTEXT_OFFSET_RBP(%rdi), %rbp movq CONTEXT_OFFSET_RBX(%rdi), %rbx - + movq CONTEXT_OFFSET_SP(%rdi), %rsp - + movq CONTEXT_OFFSET_PC(%rdi), %rdx movq %rdx, (%rsp) - + movq CONTEXT_OFFSET_TP(%rdi), %rcx #ifdef MEMORY_MODEL_large @@ -92,5 +92,5 @@ #endif movq %rcx, %fs:VREG_TP(%rsi) - + xorl %eax, %eax # context_restore returns 0 ret Index: kernel/arch/amd64/src/cpu/cpu.c =================================================================== --- kernel/arch/amd64/src/cpu/cpu.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/amd64/src/cpu/cpu.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -106,9 +106,9 @@ { cpu_info_t info; - + CPU->arch.vendor = VendorUnknown; if (has_cpuid()) { cpuid(INTEL_CPUID_LEVEL, &info); - + /* * Check for AMD processor. @@ -119,5 +119,5 @@ CPU->arch.vendor = VendorAMD; } - + /* * Check for Intel processor. @@ -128,5 +128,5 @@ CPU->arch.vendor = VendorIntel; } - + cpuid(INTEL_CPUID_STANDARD, &info); CPU->arch.family = (info.cpuid_eax >> 8) & 0xf; Index: kernel/arch/amd64/src/ddi/ddi.c =================================================================== --- kernel/arch/amd64/src/ddi/ddi.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/amd64/src/ddi/ddi.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -59,16 +59,16 @@ /* First, copy the I/O Permission Bitmap. */ irq_spinlock_lock(&TASK->lock, false); - + size_t ver = TASK->arch.iomapver; size_t elements = TASK->arch.iomap.elements; - + if (elements > 0) { assert(TASK->arch.iomap.bits); - + bitmap_t iomap; bitmap_initialize(&iomap, TSS_IOMAP_SIZE * 8, CPU->arch.tss->iomap); bitmap_copy(&iomap, &TASK->arch.iomap, elements); - + /* * Set the trailing bits in the last byte of the map to disable @@ -77,5 +77,5 @@ bitmap_set_range(&iomap, elements, ALIGN_UP(elements, 8) - elements); - + /* * It is safe to set the trailing eight bits because of the @@ -84,7 +84,7 @@ bitmap_set_range(&iomap, ALIGN_UP(elements, 8), 8); } - + irq_spinlock_unlock(&TASK->lock, false); - + /* * Second, adjust TSS segment limit. @@ -93,10 +93,10 @@ ptr_16_64_t cpugdtr; gdtr_store(&cpugdtr); - + descriptor_t *gdt_p = (descriptor_t *) cpugdtr.base; size_t size = bitmap_size(elements); gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + size); gdtr_load(&cpugdtr); - + /* * Before we load new TSS limit, the current TSS descriptor @@ -106,5 +106,5 @@ tss_desc->type = AR_TSS; tr_load(GDT_SELECTOR(TSS_DES)); - + /* * Update the generation count so that faults caused by Index: kernel/arch/amd64/src/debug/stacktrace.c =================================================================== --- kernel/arch/amd64/src/debug/stacktrace.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/amd64/src/debug/stacktrace.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -50,5 +50,5 @@ uint64_t *stack = (void *) ctx->fp; *prev = stack[FRAME_OFFSET_FP_PREV]; - + return true; } @@ -58,5 +58,5 @@ uint64_t *stack = (void *) ctx->fp; *ra = stack[FRAME_OFFSET_RA]; - + return true; } Index: kernel/arch/amd64/src/delay.S =================================================================== --- kernel/arch/amd64/src/delay.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/amd64/src/delay.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -39,5 +39,5 @@ dec %rdi jnz 0b - + ret FUNCTION_END(asm_delay_loop) @@ -47,5 +47,5 @@ dec %rdi jz 0b - + ret FUNCTION_END(asm_fake_loop) Index: kernel/arch/amd64/src/interrupt.c =================================================================== --- kernel/arch/amd64/src/interrupt.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/amd64/src/interrupt.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -70,12 +70,12 @@ "rfl=%0#18" PRIx64 "\terr=%0#18" PRIx64 "\n", istate->cs, istate->rip, istate->rflags, istate->error_word); - + if (istate_from_uspace(istate)) log_printf("ss =%0#18" PRIx64 "\n", istate->ss); - + log_printf("rax=%0#18" PRIx64 "\trbx=%0#18" PRIx64 "\t" "rcx=%0#18" PRIx64 "\trdx=%0#18" PRIx64 "\n", istate->rax, istate->rbx, istate->rcx, istate->rdx); - + log_printf("rsi=%0#18" PRIx64 "\trdi=%0#18" PRIx64 "\t" "rbp=%0#18" PRIx64 "\trsp=%0#18" PRIx64 "\n", @@ -83,9 +83,9 @@ istate_from_uspace(istate) ? istate->rsp : (uintptr_t) &istate->rsp); - + log_printf("r8 =%0#18" PRIx64 "\tr9 =%0#18" PRIx64 "\t" "r10=%0#18" PRIx64 "\tr11=%0#18" PRIx64 "\n", istate->r8, istate->r9, istate->r10, istate->r11); - + log_printf("r12=%0#18" PRIx64 "\tr13=%0#18" PRIx64 "\t" "r14=%0#18" PRIx64 "\tr15=%0#18" PRIx64 "\n", @@ -123,5 +123,5 @@ size_t ver = TASK->arch.iomapver; irq_spinlock_unlock(&TASK->lock, false); - + if (CPU->arch.iomapver_copy != ver) { /* @@ -176,10 +176,10 @@ { assert(n >= IVT_IRQBASE); - + unsigned int inum = n - IVT_IRQBASE; bool ack = false; assert(inum < IRQ_COUNT); assert((inum != IRQ_PIC_SPUR) && (inum != IRQ_PIC1)); - + irq_t *irq = irq_dispatch_and_lock(inum); if (irq) { @@ -187,5 +187,5 @@ * The IRQ handler was found. */ - + if (irq->preack) { /* Send EOI before processing the interrupt */ @@ -204,5 +204,5 @@ #endif } - + if (!ack) trap_virtual_eoi(); @@ -212,8 +212,8 @@ { unsigned int i; - + for (i = 0; i < IVT_ITEMS; i++) exc_register(i, "null", false, (iroutine_t) null_interrupt); - + for (i = 0; i < IRQ_COUNT; i++) { if ((i != IRQ_PIC_SPUR) && (i != IRQ_PIC1)) @@ -221,10 +221,10 @@ (iroutine_t) irq_interrupt); } - + exc_register(VECTOR_DE, "de_fault", true, (iroutine_t) de_fault); exc_register(VECTOR_NM, "nm_fault", true, (iroutine_t) nm_fault); exc_register(VECTOR_SS, "ss_fault", true, (iroutine_t) ss_fault); exc_register(VECTOR_GP, "gp_fault", true, (iroutine_t) gp_fault); - + #ifdef CONFIG_SMP exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", true, Index: kernel/arch/amd64/src/mm/page.c =================================================================== --- kernel/arch/amd64/src/mm/page.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/amd64/src/mm/page.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -57,9 +57,9 @@ unsigned int identity_flags = PAGE_GLOBAL | PAGE_CACHEABLE | PAGE_EXEC | PAGE_WRITE | PAGE_READ; - + page_mapping_operations = &pt_mapping_operations; - + page_table_lock(AS_KERNEL, true); - + /* * PA2KA(identity) mapping for all low-memory frames. @@ -68,7 +68,7 @@ cur += FRAME_SIZE) page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, identity_flags); - + page_table_unlock(AS_KERNEL, true); - + exc_register(VECTOR_PF, "page_fault", true, (iroutine_t) page_fault); write_cr3((uintptr_t) AS_KERNEL->genarch.page_table); @@ -78,10 +78,10 @@ { uintptr_t badvaddr = read_cr2(); - + if (istate->error_word & PFERR_CODE_RSVD) panic("Reserved bit set in page table entry."); - + pf_access_t access; - + if (istate->error_word & PFERR_CODE_RW) access = PF_ACCESS_WRITE; @@ -90,5 +90,5 @@ else access = PF_ACCESS_READ; - + (void) as_page_fault(badvaddr, access, istate); } Index: kernel/arch/amd64/src/pm.c =================================================================== --- kernel/arch/amd64/src/pm.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/amd64/src/pm.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -130,5 +130,5 @@ { tss_descriptor_t *td = (tss_descriptor_t *) d; - + td->base_0_15 = base & 0xffffU; td->base_16_23 = ((base) >> 16) & 0xffU; @@ -140,5 +140,5 @@ { tss_descriptor_t *td = (tss_descriptor_t *) d; - + td->limit_0_15 = limit & 0xffffU; td->limit_16_19 = (limit >> 16) & 0x0fU; @@ -167,15 +167,15 @@ idescriptor_t *d; unsigned int i; - + for (i = 0; i < IDT_ITEMS; i++) { d = &idt[i]; - + d->unused = 0; d->selector = GDT_SELECTOR(KTEXT_DES); - + d->present = 1; d->type = AR_INTERRUPT; /* masking interrupt */ } - + d = &idt[0]; idt_setoffset(d++, (uintptr_t) &int_0); @@ -252,10 +252,10 @@ descriptor_t *gdt_p = (descriptor_t *) gdtr.base; tss_descriptor_t *tss_desc; - + /* * Each CPU has its private GDT and TSS. * All CPUs share one IDT. */ - + if (config.cpu_active == 1) { idt_init(); @@ -270,20 +270,20 @@ * ahead of page_init */ write_cr3((uintptr_t) AS_KERNEL->genarch.page_table); - + tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC); if (!tss_p) panic("Cannot allocate TSS."); } - + tss_initialize(tss_p); - + tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]); tss_desc->present = 1; tss_desc->type = AR_TSS; tss_desc->dpl = PL_KERNEL; - + gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p); gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1); - + gdtr_load(&gdtr); idtr_load(&idtr); Index: kernel/arch/amd64/src/smp/ap.S =================================================================== --- kernel/arch/amd64/src/smp/ap.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/amd64/src/smp/ap.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -55,7 +55,7 @@ xorw %ax, %ax movw %ax, %ds - + lgdtl ap_gdtr # initialize Global Descriptor Table register - + movl %cr0, %eax orl $CR0_PE, %eax @@ -71,15 +71,15 @@ movw $GDT_SELECTOR(UDATA_DES), %ax movw %ax, %gs - + # Enable 64-bit page transaltion entries (CR4.PAE = 1). # Paging is not enabled until after long mode is enabled - + movl %cr4, %eax orl $CR4_PAE, %eax movl %eax, %cr4 - + leal ptl_0, %eax movl %eax, %cr3 - + # Enable long mode movl $AMD_MSR_EFER, %ecx # EFER MSR number @@ -87,10 +87,10 @@ orl $AMD_LME, %eax # Set LME=1 wrmsr # Write EFER - + # Enable paging to activate long mode (set CR0.PG = 1) movl %cr0, %eax orl $CR0_PG, %eax movl %eax, %cr0 - + # At this point we are in compatibility mode jmpl $GDT_SELECTOR(KTEXT_DES), $start64 - BOOT_OFFSET + AP_BOOT_OFFSET @@ -100,8 +100,8 @@ movabsq $ctx, %rsp movq CONTEXT_OFFSET_SP(%rsp), %rsp - + pushq $0 movq %rsp, %rbp - + movabsq $main_ap, %rax callq *%rax # never returns Index: kernel/arch/amd64/src/syscall.c =================================================================== --- kernel/arch/amd64/src/syscall.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/amd64/src/syscall.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -51,5 +51,5 @@ /* Setup syscall entry address */ - + /* This is _mess_ - the 64-bit CS is argument + 16, * the SS is argument + 8. The order is: Index: kernel/arch/amd64/src/userspace.c =================================================================== --- kernel/arch/amd64/src/userspace.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/amd64/src/userspace.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -49,8 +49,8 @@ { uint64_t rflags = read_rflags(); - + rflags &= ~RFLAGS_NT; rflags |= RFLAGS_IF; - + asm volatile ( "pushq %[udata_des]\n" @@ -60,5 +60,5 @@ "pushq %[entry]\n" "movq %[uarg], %%rax\n" - + /* %rdi is defined to hold pcb_ptr - set it to 0 */ "xorq %%rdi, %%rdi\n" @@ -73,5 +73,5 @@ : "rax" ); - + /* Unreachable */ while (1); Index: kernel/arch/arm32/include/arch/asm.h =================================================================== --- kernel/arch/arm32/include/arch/asm.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/arm32/include/arch/asm.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -105,5 +105,5 @@ { uintptr_t v; - + asm volatile ( "and %[v], sp, %[size]\n" @@ -111,5 +111,5 @@ : [size] "r" (~(STACK_SIZE - 1)) ); - + return v; } Index: kernel/arch/arm32/include/arch/atomic.h =================================================================== --- kernel/arch/arm32/include/arch/atomic.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/arm32/include/arch/atomic.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -59,5 +59,5 @@ atomic_count_t ret = val->count; interrupts_restore(ipl); - + return ret; } Index: kernel/arch/arm32/include/arch/mm/page_armv4.h =================================================================== --- kernel/arch/arm32/include/arch/mm/page_armv4.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/arm32/include/arch/mm/page_armv4.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -137,5 +137,5 @@ pte_level0_t *p = &pt[i].l0; int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); - + return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) | (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) | @@ -152,8 +152,8 @@ { pte_level1_t *p = &pt[i].l1; - + int dt = p->descriptor_type; int ap = p->access_permission_0; - + return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) | @@ -177,5 +177,5 @@ { pte_level0_t *p = &pt[i].l0; - + if (flags & PAGE_NOT_PRESENT) { p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; @@ -206,17 +206,17 @@ { pte_level1_t *p = &pt[i].l1; - + if (flags & PAGE_NOT_PRESENT) p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; else p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; - + p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; - + /* default access permission */ p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = PTE_AP_USER_NO_KERNEL_RW; - + if (flags & PAGE_USER) { if (flags & PAGE_READ) { Index: kernel/arch/arm32/include/arch/mm/page_armv6.h =================================================================== --- kernel/arch/arm32/include/arch/mm/page_armv6.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/arm32/include/arch/mm/page_armv6.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -170,5 +170,5 @@ const pte_level0_t *p = &pt[i].l0; const unsigned np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); - + return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) | (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) | @@ -185,9 +185,9 @@ { const pte_level1_t *p = &pt[i].l1; - + const unsigned dt = p->descriptor_type; const unsigned ap0 = p->access_permission_0; const unsigned ap1 = p->access_permission_1; - + return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | ((dt != PTE_DESCRIPTOR_SMALL_PAGE_NX) << PAGE_EXEC_SHIFT) | @@ -211,5 +211,5 @@ { pte_level0_t *p = &pt[i].l0; - + if (flags & PAGE_NOT_PRESENT) { p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; @@ -245,5 +245,5 @@ { pte_level1_t *p = &pt[i].l1; - + if (flags & PAGE_NOT_PRESENT) { p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; @@ -278,14 +278,14 @@ p->bufferable = 1; } - + /* Shareable is ignored for devices (non-cacheable), * turn it off for normal memory. */ p->shareable = 0; - + p->non_global = !(flags & PAGE_GLOBAL); - + /* default access permission: kernel only*/ p->access_permission_0 = PTE_AP0_USER_NO_KERNEL_FULL; - + if (flags & PAGE_USER) { p->access_permission_0 = PTE_AP0_USER_FULL_KERNEL_FULL; Index: kernel/arch/arm32/src/arm32.c =================================================================== --- kernel/arch/arm32/src/arm32.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/arm32/src/arm32.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -69,5 +69,5 @@ { init.cnt = min3(bootinfo->cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS); - + size_t i; for (i = 0; i < init.cnt; i++) { @@ -93,5 +93,5 @@ { machine_init(); - + /* Initialize exception dispatch table */ exception_init(); @@ -100,5 +100,5 @@ /* Initialize Restartable Atomic Sequences support. */ ras_init(); - + machine_output_init(); } @@ -132,5 +132,5 @@ { uint8_t *stck; - + stck = &THREAD->kstack[STACK_SIZE]; supervisor_sp = (uintptr_t) stck; Index: kernel/arch/arm32/src/asm.S =================================================================== --- kernel/arch/arm32/src/asm.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/arm32/src/asm.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -39,10 +39,10 @@ mov r5, r0 /* save dst */ beq 4f - + 1: cmp r2, #0 movne ip, #0 beq 3f - + 2: ldrb r3, [ip, r1] @@ -51,9 +51,9 @@ cmp ip, r2 bne 2b - + 3: mov r0, r5 ldmia sp!, {r4, r5, pc} - + 4: add r3, r0, #3 @@ -66,5 +66,5 @@ mov lr, #0 mov ip, lr - + 5: ldr r3, [ip, r1] @@ -74,5 +74,5 @@ add ip, ip, #4 bne 5b - + 6: ands r4, r2, #3 @@ -82,5 +82,5 @@ add ip, r3, r1 mov r2, #0 - + 7: ldrb r3, [r2, ip] Index: kernel/arch/arm32/src/atomic.c =================================================================== --- kernel/arch/arm32/src/atomic.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/arm32/src/atomic.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -54,13 +54,13 @@ */ irq_spinlock_lock(&cas_lock, true); - + void * cur_val = *ptr; - + if (cur_val == expected) { *ptr = new_val; } - + irq_spinlock_unlock(&cas_lock, true); - + return cur_val; } Index: kernel/arch/arm32/src/context.S =================================================================== --- kernel/arch/arm32/src/context.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/arm32/src/context.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -54,5 +54,5 @@ ldmia r0!, {sp, lr} ldmia r0!, {r4-r11} - + mov r0, #0 mov pc, lr Index: kernel/arch/arm32/src/exc_handler.S =================================================================== --- kernel/arch/arm32/src/exc_handler.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/arm32/src/exc_handler.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -97,5 +97,5 @@ # Stop stack traces here mov fp, #0 - + b 2f Index: kernel/arch/arm32/src/exception.c =================================================================== --- kernel/arch/arm32/src/exception.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/arm32/src/exception.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -71,9 +71,9 @@ volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET; - + /* make it LDR instruction and store at exception vector */ *vector = handler_address_ptr | LDR_OPCODE; smc_coherence(vector); - + /* store handler's address */ *(vector + EXC_VECTORS) = handler_addr; @@ -99,20 +99,20 @@ install_handler((unsigned) reset_exception_entry, (unsigned *) EXC_RESET_VEC); - + install_handler((unsigned) undef_instr_exception_entry, (unsigned *) EXC_UNDEF_INSTR_VEC); - + install_handler((unsigned) swi_exception_entry, (unsigned *) EXC_SWI_VEC); - + install_handler((unsigned) prefetch_abort_exception_entry, (unsigned *) EXC_PREFETCH_ABORT_VEC); - + install_handler((unsigned) data_abort_exception_entry, (unsigned *) EXC_DATA_ABORT_VEC); - + install_handler((unsigned) irq_exception_entry, (unsigned *) EXC_IRQ_VEC); - + install_handler((unsigned) fiq_exception_entry, (unsigned *) EXC_FIQ_VEC); @@ -140,8 +140,8 @@ { uint32_t control_reg = SCTLR_read(); - + /* switch on the high vectors bit */ control_reg |= SCTLR_HIGH_VECTORS_EN_FLAG; - + SCTLR_write(control_reg); } @@ -190,5 +190,5 @@ #endif install_exception_handlers(); - + exc_register(EXC_UNDEF_INSTR, "undefined instruction", true, (iroutine_t) undef_insn_exception); Index: kernel/arch/arm32/src/interrupt.c =================================================================== --- kernel/arch/arm32/src/interrupt.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/arm32/src/interrupt.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -49,5 +49,5 @@ current_status_reg_control_write(STATUS_REG_IRQ_DISABLED_BIT | ipl); - + return ipl; } @@ -62,5 +62,5 @@ current_status_reg_control_write(ipl & ~STATUS_REG_IRQ_DISABLED_BIT); - + return ipl; } Index: kernel/arch/arm32/src/mach/integratorcp/integratorcp.c =================================================================== --- kernel/arch/arm32/src/mach/integratorcp/integratorcp.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/arm32/src/mach/integratorcp/integratorcp.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -103,5 +103,5 @@ *(uint32_t *) ((char *)(icp.hw_map.vga) + 0x1C) = 0x182B; *(uint32_t *) ((char *)(icp.hw_map.cmcr) + 0xC) = 0x33805000; - + } @@ -259,5 +259,5 @@ uint32_t sources = icp_irqc_get_sources(); unsigned int i; - + for (i = 0; i < ICP_IRQC_MAX_IRQ; i++) { if (sources & (1 << i)) { @@ -295,5 +295,5 @@ vga_init = true; } - + fb_properties_t prop = { .addr = ICP_FB, @@ -304,5 +304,5 @@ .visual = VISUAL_RGB_8_8_8_0, }; - + outdev_t *fbdev = fb_init(&prop); if (fbdev) @@ -322,5 +322,5 @@ pl050->data = (ioport8_t *) icp.hw_map.kbd_data; pl050->ctrl = (ioport8_t *) icp.hw_map.kbd_ctrl; - + pl050_instance_t *pl050_instance = pl050_init(pl050, ICP_KBD_IRQ); if (pl050_instance) { Index: kernel/arch/arm32/src/mm/frame.c =================================================================== --- kernel/arch/arm32/src/mm/frame.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/arm32/src/mm/frame.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -49,5 +49,5 @@ base = ALIGN_UP(base, FRAME_SIZE); size = ALIGN_DOWN(size, FRAME_SIZE); - + if (!frame_adjust_zone_bounds(low, &base, &size)) return; @@ -64,5 +64,5 @@ ZONE_AVAILABLE | ZONE_HIGHMEM); } - + } Index: kernel/arch/arm32/src/mm/page.c =================================================================== --- kernel/arch/arm32/src/mm/page.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/arm32/src/mm/page.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -56,5 +56,5 @@ page_table_lock(AS_KERNEL, true); - + /* Kernel identity mapping */ //FIXME: We need to consider the possibility that @@ -66,5 +66,5 @@ cur += FRAME_SIZE) page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags); - + #ifdef HIGH_EXCEPTION_VECTORS /* Create mapping for exception table at high offset */ @@ -76,7 +76,7 @@ page_table_unlock(AS_KERNEL, true); - + as_switch(NULL, AS_KERNEL); - + boot_page_table_free(); } Index: kernel/arch/arm32/src/ras.c =================================================================== --- kernel/arch/arm32/src/ras.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/arm32/src/ras.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -55,8 +55,8 @@ if (!frame) frame = frame_alloc(1, FRAME_LOWMEM, 0); - + ras_page = (uintptr_t *) km_map(frame, PAGE_SIZE, PAGE_READ | PAGE_WRITE | PAGE_USER | PAGE_CACHEABLE); - + memsetb(ras_page, PAGE_SIZE, 0); ras_page[RAS_START] = 0; Index: kernel/arch/arm32/src/start.S =================================================================== --- kernel/arch/arm32/src/start.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/arm32/src/start.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -60,9 +60,9 @@ orr r3, r4, #0x13 msr cpsr_c, r3 - + ldr sp, =temp_stack - + bl arm32_pre_main - + # # Create the first stack frame. Index: kernel/arch/ia32/include/arch/asm.h =================================================================== --- kernel/arch/ia32/include/arch/asm.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/include/arch/asm.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -174,5 +174,5 @@ if (((void *)port) < IO_SPACE_BOUNDARY) { uint8_t val; - + asm volatile ( "inb %w[port], %b[val]\n" @@ -180,5 +180,5 @@ : [port] "d" (port) ); - + return val; } else @@ -198,5 +198,5 @@ if (((void *)port) < IO_SPACE_BOUNDARY) { uint16_t val; - + asm volatile ( "inw %w[port], %w[val]\n" @@ -204,5 +204,5 @@ : [port] "d" (port) ); - + return val; } else @@ -222,5 +222,5 @@ if (((void *)port) < IO_SPACE_BOUNDARY) { uint32_t val; - + asm volatile ( "inl %w[port], %[val]\n" @@ -228,5 +228,5 @@ : [port] "d" (port) ); - + return val; } else @@ -243,5 +243,5 @@ : [v] "=r" (eflags) ); - + return eflags; } @@ -276,7 +276,7 @@ { ipl_t ipl = interrupts_read(); - + asm volatile ("sti\n"); - + return ipl; } @@ -292,7 +292,7 @@ { ipl_t ipl = interrupts_read(); - + asm volatile ("cli\n"); - + return ipl; } @@ -336,5 +336,5 @@ { uint32_t ax, dx; - + asm volatile ( "rdmsr" @@ -343,5 +343,5 @@ : "c" (msr) ); - + return ((uint64_t) dx << 32) | ax; } @@ -360,5 +360,5 @@ { uintptr_t v; - + asm volatile ( "andl %%esp, %[v]\n" @@ -366,5 +366,5 @@ : "0" (~(STACK_SIZE - 1)) ); - + return v; } Index: kernel/arch/ia32/include/arch/atomic.h =================================================================== --- kernel/arch/ia32/include/arch/atomic.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/include/arch/atomic.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -75,5 +75,5 @@ { atomic_count_t r = 1; - + asm volatile ( "lock xaddl %[r], %[count]\n" @@ -81,5 +81,5 @@ [r] "+r" (r) ); - + return r; } @@ -88,5 +88,5 @@ { atomic_count_t r = -1; - + asm volatile ( "lock xaddl %[r], %[count]\n" @@ -94,5 +94,5 @@ [r] "+r" (r) ); - + return r; } @@ -104,5 +104,5 @@ { atomic_count_t v = 1; - + asm volatile ( "xchgl %[v], %[count]\n" @@ -110,5 +110,5 @@ [count] "+m" (val->count) ); - + return v; } @@ -119,5 +119,5 @@ { atomic_count_t tmp; - + preemption_disable(); asm volatile ( @@ -129,5 +129,5 @@ "testl %[tmp], %[tmp]\n" "jnz 0b\n" /* lightweight looping on locked spinlock */ - + "incl %[tmp]\n" /* now use the atomic operation */ "xchgl %[count], %[tmp]\n" @@ -137,5 +137,5 @@ [tmp] "=&r" (tmp) ); - + /* * Prevent critical section code from bleeding out this way up. Index: kernel/arch/ia32/include/arch/cpu.h =================================================================== --- kernel/arch/ia32/include/arch/cpu.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/include/arch/cpu.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -80,5 +80,5 @@ tss_t *tss; - + size_t iomapver_copy; /** Copy of TASK's I/O Permission bitmap generation count. */ } cpu_arch_t; Index: kernel/arch/ia32/include/arch/cpuid.h =================================================================== --- kernel/arch/ia32/include/arch/cpuid.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/include/arch/cpuid.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -83,17 +83,17 @@ uint32_t val; uint32_t ret; - + asm volatile ( "pushf\n" /* read flags */ "popl %[ret]\n" "movl %[ret], %[val]\n" - + "xorl %[eflags_id], %[val]\n" /* swap the ID bit */ - + "pushl %[val]\n" /* propagate the change into flags */ "popf\n" "pushf\n" "popl %[val]\n" - + "andl %[eflags_id], %[ret]\n" /* interrested only in ID bit */ "andl %[eflags_id], %[val]\n" @@ -102,5 +102,5 @@ : [eflags_id] "i" (EFLAGS_ID) ); - + return ret; } Index: kernel/arch/ia32/include/arch/cycle.h =================================================================== --- kernel/arch/ia32/include/arch/cycle.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/include/arch/cycle.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -44,10 +44,10 @@ #else uint64_t v; - + asm volatile( "rdtsc\n" : "=A" (v) ); - + return v; #endif Index: kernel/arch/ia32/include/arch/mm/page.h =================================================================== --- kernel/arch/ia32/include/arch/mm/page.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/include/arch/mm/page.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -183,5 +183,5 @@ { pte_t *p = &pt[i]; - + return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT | (!p->present) << PAGE_PRESENT_SHIFT | @@ -196,5 +196,5 @@ { pte_t *p = &pt[i]; - + p->page_cache_disable = !(flags & PAGE_CACHEABLE); p->present = !(flags & PAGE_NOT_PRESENT); @@ -202,5 +202,5 @@ p->writeable = (flags & PAGE_WRITE) != 0; p->global = (flags & PAGE_GLOBAL) != 0; - + /* * Ensure that there is at least one bit set even if the present bit is Index: kernel/arch/ia32/include/arch/smp/apic.h =================================================================== --- kernel/arch/ia32/include/arch/smp/apic.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/include/arch/smp/apic.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -334,5 +334,5 @@ } __attribute__ ((packed)); }; - + } __attribute__ ((packed)) io_redirection_reg_t; Index: kernel/arch/ia32/include/arch/smp/smp.h =================================================================== --- kernel/arch/ia32/include/arch/smp/smp.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/include/arch/smp/smp.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -43,11 +43,11 @@ /** Check whether a processor is enabled. */ bool (*cpu_enabled)(size_t); - + /** Check whether a processor is BSP. */ bool (*cpu_bootstrap)(size_t); - + /** Return APIC ID of a processor. */ uint8_t (*cpu_apic_id)(size_t); - + /** Return mapping between IRQ and APIC pin. */ int (*irq_to_pin)(unsigned int); Index: kernel/arch/ia32/src/asm.S =================================================================== --- kernel/arch/ia32/src/asm.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/src/asm.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -63,26 +63,26 @@ movl %edi, %edx /* save %edi */ movl %esi, %eax /* save %esi */ - + movl MEMCPY_SIZE(%esp), %ecx shrl $2, %ecx /* size / 4 */ - + movl MEMCPY_DST(%esp), %edi movl MEMCPY_SRC(%esp), %esi - + /* Copy whole words */ rep movsl - + movl MEMCPY_SIZE(%esp), %ecx andl $3, %ecx /* size % 4 */ jz 0f - + /* Copy the rest byte by byte */ rep movsb - + 0: - + movl %edx, %edi movl %eax, %esi - + /* MEMCPY_DST(%esp), success */ movl MEMCPY_DST(%esp), %eax @@ -99,5 +99,5 @@ movl %edx, %edi movl %eax, %esi - + /* Return 0, failure */ xorl %eax, %eax @@ -112,10 +112,10 @@ movl %cr0, %edx orl $CR0_PG, %edx /* paging on */ - + /* Clear Cache Disable and not Write Though */ andl $~(CR0_CD | CR0_NW), %edx movl %edx, %cr0 jmp 0f - + 0: ret @@ -174,5 +174,5 @@ movl %edi, ISTATE_OFFSET_EDI(%esp) /* observability; not needed */ movl %ebp, ISTATE_OFFSET_EBP(%esp) /* observability; not needed */ - + /* * Fake up the stack trace linkage. @@ -190,5 +190,5 @@ movl $(GDT_SELECTOR(VREG_DES)), %eax movl %eax, %gs - + /* * Sanitize EFLAGS. @@ -207,5 +207,5 @@ call syscall_handler - + /* * Prepare return address and userspace stack for SYSEXIT. @@ -252,5 +252,5 @@ movl %es, %ecx movl %ds, %edx - + movl %ecx, ISTATE_OFFSET_ES(%esp) movl %edx, ISTATE_OFFSET_DS(%esp) @@ -264,15 +264,15 @@ movl $(GDT_SELECTOR(VREG_DES)), %eax movl %eax, %gs - + movl $0, ISTATE_OFFSET_EBP_FRAME(%esp) movl ISTATE_OFFSET_EIP(%esp), %eax movl %eax, ISTATE_OFFSET_EIP_FRAME(%esp) leal ISTATE_OFFSET_EBP_FRAME(%esp), %ebp - + cld - + /* Call syscall_handler(edx, ecx, ebx, esi, edi, ebp, eax) */ call syscall_handler - + /* * Restore the segment registers. @@ -286,8 +286,8 @@ movl ISTATE_OFFSET_ES(%esp), %ecx movl ISTATE_OFFSET_DS(%esp), %edx - + movl %ecx, %es movl %edx, %ds - + /* * Restore the preserved registers the handler cloberred itself @@ -295,8 +295,8 @@ */ movl ISTATE_OFFSET_EBP(%esp), %ebp - + addl $(ISTATE_SOFT_SIZE + 4), %esp iret - + /** * Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int @@ -333,5 +333,5 @@ subl $(ISTATE_SOFT_SIZE + 4), %esp .endif - + /* * Save the general purpose registers. @@ -344,5 +344,5 @@ movl %esi, ISTATE_OFFSET_ESI(%esp) movl %ebp, ISTATE_OFFSET_EBP(%esp) - + /* * Save the segment registers. @@ -356,8 +356,8 @@ movl %es, %ecx movl %ds, %edx - + movl %ecx, ISTATE_OFFSET_ES(%esp) movl %edx, ISTATE_OFFSET_DS(%esp) - + /* * Switch to kernel selectors. @@ -368,5 +368,5 @@ movl $(GDT_SELECTOR(VREG_DES)), %eax movl %eax, %gs - + /* * Imitate a regular stack frame linkage. @@ -387,15 +387,15 @@ movl %eax, ISTATE_OFFSET_EIP_FRAME(%esp) leal ISTATE_OFFSET_EBP_FRAME(%esp), %ebp - + cld - + pushl %esp /* pass istate address */ pushl $(\i) /* pass intnum */ - + /* Call exc_dispatch(intnum, istate) */ call exc_dispatch - + addl $8, %esp /* clear arguments from the stack */ - + /* * Restore the selector registers. @@ -409,8 +409,8 @@ movl ISTATE_OFFSET_ES(%esp), %ecx movl ISTATE_OFFSET_DS(%esp), %edx - + movl %ecx, %es movl %edx, %ds - + /* * Restore the scratch registers and the preserved @@ -422,5 +422,5 @@ movl ISTATE_OFFSET_EDX(%esp), %edx movl ISTATE_OFFSET_EBP(%esp), %ebp - + addl $(ISTATE_SOFT_SIZE + 4), %esp iret @@ -452,7 +452,7 @@ */ FUNCTION_BEGIN(early_putchar) - + #if ((defined(CONFIG_EGA)) && (!defined(CONFIG_FB))) - + /* Prologue, save preserved registers */ pushl %ebp @@ -461,83 +461,83 @@ pushl %esi pushl %edi - + movl $(PA2KA(0xb8000)), %edi /* base of EGA text mode memory */ xorl %eax, %eax - + /* Read bits 8 - 15 of the cursor address */ movw $0x3d4, %dx movb $0xe, %al outb %al, %dx - + movw $0x3d5, %dx inb %dx, %al shl $8, %ax - + /* Read bits 0 - 7 of the cursor address */ movw $0x3d4, %dx movb $0xf, %al outb %al, %dx - + movw $0x3d5, %dx inb %dx, %al - + /* Sanity check for the cursor on screen */ cmp $2000, %ax jb early_putchar_cursor_ok - + movw $1998, %ax - + early_putchar_cursor_ok: - + movw %ax, %bx shl $1, %eax addl %eax, %edi - + movl 0x08(%ebp), %eax - + cmp $0x0a, %al jne early_putchar_backspace - + /* Interpret newline */ - + movw %bx, %ax /* %bx -> %dx:%ax */ xorw %dx, %dx - + movw $80, %cx idivw %cx, %ax /* %dx = %bx % 80 */ - + /* %bx <- %bx + 80 - (%bx % 80) */ addw %cx, %bx subw %dx, %bx - + jmp early_putchar_skip - + early_putchar_backspace: - + cmp $0x08, %al jne early_putchar_print - + /* Interpret backspace */ - + cmp $0x0000, %bx je early_putchar_skip - + dec %bx jmp early_putchar_skip - + early_putchar_print: - + /* Print character */ - + movb $0x0e, %ah /* black background, yellow foreground */ stosw inc %bx - + early_putchar_skip: - + /* Sanity check for the cursor on the last line */ cmp $2000, %bx jb early_putchar_no_scroll - + /* Scroll the screen (24 rows) */ movl $(PA2KA(0xb80a0)), %esi @@ -545,33 +545,33 @@ movl $960, %ecx rep movsl - + /* Clear the 24th row */ xorl %eax, %eax movl $40, %ecx rep stosl - + /* Go to row 24 */ movw $1920, %bx - + early_putchar_no_scroll: - + /* Write bits 8 - 15 of the cursor address */ movw $0x3d4, %dx movb $0xe, %al outb %al, %dx - + movw $0x3d5, %dx movb %bh, %al outb %al, %dx - + /* Write bits 0 - 7 of the cursor address */ movw $0x3d4, %dx movb $0xf, %al outb %al, %dx - + movw $0x3d5, %dx movb %bl, %al outb %al, %dx - + /* Epilogue, restore preserved registers */ popl %edi @@ -579,7 +579,7 @@ popl %ebx leave - + #endif - + ret FUNCTION_END(early_putchar) Index: kernel/arch/ia32/src/atomic.S =================================================================== --- kernel/arch/ia32/src/atomic.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/src/atomic.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -39,5 +39,5 @@ pushl %eax pushl %ebx - + movl 12(%esp),%ebx @@ -56,4 +56,4 @@ ret FUNCTION_END(spinlock_arch) - + #endif Index: kernel/arch/ia32/src/boot/multiboot.S =================================================================== --- kernel/arch/ia32/src/boot/multiboot.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/src/boot/multiboot.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -77,8 +77,8 @@ cli cld - + /* Initialize stack pointer */ movl $START_STACK, %esp - + /* * Initialize Global Descriptor Table and @@ -87,5 +87,5 @@ lgdtl bootstrap_gdtr lidtl bootstrap_idtr - + /* Kernel data + stack */ movw $GDT_SELECTOR(KDATA_DES), %cx @@ -95,61 +95,61 @@ movw %cx, %ds movw %cx, %ss - + jmpl $GDT_SELECTOR(KTEXT_DES), $multiboot_meeting_point multiboot_meeting_point: - + /* Save multiboot arguments */ movl %eax, multiboot_eax movl %ebx, multiboot_ebx - + pm_status $status_prot - + #include "vesa_prot.inc" - + #ifndef PROCESSOR_i486 - + pm_status $status_prot2 - + movl $(INTEL_CPUID_LEVEL), %eax cpuid cmp $0x0, %eax /* any function > 0? */ jbe pse_unsupported - + movl $(INTEL_CPUID_STANDARD), %eax cpuid bt $(INTEL_PSE), %edx jnc pse_unsupported - + /* Map kernel and turn paging on */ pm_status $status_pse call map_kernel_pse jmp stack_init - + #endif /* PROCESSOR_i486 */ - + pse_unsupported: - + /* Map kernel and turn paging on */ pm_status $status_non_pse call map_kernel_non_pse - + stack_init: - + /* Create the first stack frame */ pushl $0 movl %esp, %ebp - + pm2_status $status_prot3 - + /* Call ia32_pre_main(multiboot_eax, multiboot_ebx) */ pushl multiboot_ebx pushl multiboot_eax call ia32_pre_main - + pm2_status $status_main - + /* Call main_bsp() */ call main_bsp - + /* Not reached */ cli @@ -170,10 +170,10 @@ andl $~CR4_PAE, %ecx /* PAE off */ movl %ecx, %cr4 - + movl $(page_directory + 0), %esi movl $(page_directory + 2048), %edi xorl %ecx, %ecx xorl %ebx, %ebx - + floop_pse: movl $(PDE_4M | PDE_RW | PDE_P), %eax @@ -184,11 +184,11 @@ movl %eax, (%edi, %ecx, 4) addl $(4 * 1024 * 1024), %ebx - + incl %ecx cmpl $512, %ecx jl floop_pse - + movl %esi, %cr3 - + movl %cr0, %ebx orl $CR0_PG, %ebx /* paging on */ @@ -208,37 +208,37 @@ andl $~CR4_PAE, %ecx /* PAE off */ movl %ecx, %cr4 - + call calc_kernel_end call find_mem_for_pt - + mov kernel_end, %esi mov free_area, %ecx - + cmpl %esi, %ecx jbe use_kernel_end - + mov %ecx, %esi - + /* Align address down to 4k */ andl $(~(PAGE_SIZE - 1)), %esi - + use_kernel_end: - + /* Align address to 4k */ addl $(PAGE_SIZE - 1), %esi andl $(~(PAGE_SIZE - 1)), %esi - + /* Allocate space for page tables */ movl %esi, pt_loc movl $KA2PA(ballocs), %edi - + movl %esi, (%edi) addl $4, %edi movl $(2 * 1024 * 1024), (%edi) - + /* Fill page tables */ xorl %ecx, %ecx xorl %ebx, %ebx - + floop_pt: movl $(PTE_RW | PTE_P), %eax @@ -246,10 +246,10 @@ movl %eax, (%esi, %ecx, 4) addl $PAGE_SIZE, %ebx - + incl %ecx cmpl $(512 * 1024), %ecx - + jl floop_pt - + /* Fill page directory */ movl $(page_directory + 0), %esi @@ -257,27 +257,27 @@ xorl %ecx, %ecx movl pt_loc, %ebx - + floop: movl $(PDE_RW | PDE_P), %eax orl %ebx, %eax - + /* Mapping 0x00000000 + %ecx * 4M => 0x00000000 + %ecx * 4M */ movl %eax, (%esi, %ecx, 4) - + /* Mapping 0x80000000 + %ecx * 4M => 0x00000000 + %ecx * 4M */ movl %eax, (%edi, %ecx, 4) addl $PAGE_SIZE, %ebx - + incl %ecx cmpl $512, %ecx - + jl floop - + movl %esi, %cr3 - + movl %cr0, %ebx orl $CR0_PG, %ebx /* paging on */ movl %ebx, %cr0 - + ret FUNCTION_END(map_kernel_non_pse) @@ -288,14 +288,14 @@ movl (%edi), %esi leal KA2PA(0)(%esi), %esi - + movl $KA2PA(hardcoded_ktext_size), %edi addl (%edi), %esi leal KA2PA(0)(%esi), %esi - + movl $KA2PA(hardcoded_kdata_size), %edi addl (%edi), %esi leal KA2PA(0)(%esi), %esi movl %esi, kernel_end - + ret @@ -305,34 +305,34 @@ cmpl $MULTIBOOT_LOADER_MAGIC, multiboot_eax je check_multiboot_map - + ret - + check_multiboot_map: - + /* Copy address of the multiboot info to ebx */ movl multiboot_ebx, %ebx - + /* Check if memory map flag is present */ movl (%ebx), %edx andl $MULTIBOOT_INFO_FLAGS_MMAP, %edx jnz use_multiboot_map - + ret - + use_multiboot_map: - + /* Copy address of the memory map to edx */ movl MULTIBOOT_INFO_OFFSET_MMAP_ADDR(%ebx), %edx movl %edx, %ecx - + addl MULTIBOOT_INFO_OFFSET_MMAP_LENGTH(%ebx), %ecx - + /* Find a free region at least 2M in size */ check_memmap_loop: - + /* Is this a free region? */ cmpl $MEMMAP_MEMORY_AVAILABLE, MULTIBOOT_MEMMAP_OFFSET_MM_INFO + E820MEMMAP_OFFSET_TYPE(%edx) jnz next_region - + /* Check size */ cmpl $0, MULTIBOOT_MEMMAP_OFFSET_MM_INFO + E820MEMMAP_OFFSET_SIZE + 4(%edx) @@ -340,23 +340,23 @@ cmpl $(2 * 1024 * 1024 + PAGE_SIZE), MULTIBOOT_MEMMAP_OFFSET_MM_INFO + E820MEMMAP_OFFSET_SIZE(%edx) jbe next_region - + cmpl $0, MULTIBOOT_MEMMAP_OFFSET_MM_INFO + E820MEMMAP_OFFSET_BASE_ADDRESS + 4(%edx) jz found_region - + next_region: - + cmp %ecx, %edx jbe next_region_do - + ret - + next_region_do: - + addl MULTIBOOT_MEMMAP_OFFSET_SIZE(%edx), %edx addl $MULTIBOOT_MEMMAP_SIZE_SIZE, %edx jmp check_memmap_loop - + found_region: - + /* Use end of the found region */ mov MULTIBOOT_MEMMAP_OFFSET_MM_INFO + E820MEMMAP_OFFSET_BASE_ADDRESS(%edx), %ecx @@ -364,5 +364,5 @@ sub $(2 * 1024 * 1024), %ecx mov %ecx, free_area - + ret @@ -381,48 +381,48 @@ movl $0xb8000, %edi /* base of EGA text mode memory */ xorl %eax, %eax - + /* Read bits 8 - 15 of the cursor address */ movw $0x3d4, %dx movb $0xe, %al outb %al, %dx - + movw $0x3d5, %dx inb %dx, %al shl $8, %ax - + /* Read bits 0 - 7 of the cursor address */ movw $0x3d4, %dx movb $0xf, %al outb %al, %dx - + movw $0x3d5, %dx inb %dx, %al - + /* Sanity check for the cursor on screen */ cmp $2000, %ax jb err_cursor_ok - + movw $1998, %ax - + err_cursor_ok: - + movw %ax, %bx shl $1, %eax addl %eax, %edi - + err_ploop: lodsb - + cmp $0, %al je err_ploop_end - + movb $0x0c, %ah /* black background, light red foreground */ stosw - + /* Sanity check for the cursor on the last line */ inc %bx cmp $2000, %bx jb err_ploop - + /* Scroll the screen (24 rows) */ movl %esi, %edx @@ -431,36 +431,36 @@ movl $960, %ecx rep movsl - + /* Clear the 24th row */ xorl %eax, %eax movl $40, %ecx rep stosl - + /* Go to row 24 */ movl %edx, %esi movl $0xb8f00, %edi movw $1920, %bx - + jmp err_ploop err_ploop_end: - + /* Write bits 8 - 15 of the cursor address */ movw $0x3d4, %dx movb $0xe, %al outb %al, %dx - + movw $0x3d5, %dx movb %bh, %al outb %al, %dx - + /* Write bits 0 - 7 of the cursor address */ movw $0x3d4, %dx movb $0xf, %al outb %al, %dx - + movw $0x3d5, %dx movb %bl, %al outb %al, %dx - + cli hlt1: @@ -486,51 +486,51 @@ pushl %edx pushl %edi - + movl $0xb8000, %edi /* base of EGA text mode memory */ xorl %eax, %eax - + /* Read bits 8 - 15 of the cursor address */ movw $0x3d4, %dx movb $0xe, %al outb %al, %dx - + movw $0x3d5, %dx inb %dx, %al shl $8, %ax - + /* Read bits 0 - 7 of the cursor address */ movw $0x3d4, %dx movb $0xf, %al outb %al, %dx - + movw $0x3d5, %dx inb %dx, %al - + /* Sanity check for the cursor on screen */ cmp $2000, %ax jb pm_puts_cursor_ok - + movw $1998, %ax - + pm_puts_cursor_ok: - + movw %ax, %bx shl $1, %eax addl %eax, %edi - + pm_puts_ploop: lodsb - + cmp $0, %al je pm_puts_ploop_end - + movb $0x0a, %ah /* black background, light green foreground */ stosw - + /* Sanity check for the cursor on the last line */ inc %bx cmp $2000, %bx jb pm_puts_ploop - + /* Scroll the screen (24 rows) */ movl %esi, %edx @@ -539,36 +539,36 @@ movl $960, %ecx rep movsl - + /* Clear the 24th row */ xorl %eax, %eax movl $40, %ecx rep stosl - + /* Go to row 24 */ movl %edx, %esi movl $0xb8f00, %edi movw $1920, %bx - + jmp pm_puts_ploop pm_puts_ploop_end: - + /* Write bits 8 - 15 of the cursor address */ movw $0x3d4, %dx movb $0xe, %al outb %al, %dx - + movw $0x3d5, %dx movb %bh, %al outb %al, %dx - + /* Write bits 0 - 7 of the cursor address */ movw $0x3d4, %dx movb $0xf, %al outb %al, %dx - + movw $0x3d5, %dx movb %bl, %al outb %al, %dx - + popl %edi popl %edx @@ -576,5 +576,5 @@ popl %ebx popl %eax - + ret @@ -591,7 +591,7 @@ */ early_puts: - + #if ((defined(CONFIG_EGA)) && (!defined(CONFIG_FB))) - + /* Prologue, save preserved registers */ pushl %ebp @@ -600,52 +600,52 @@ pushl %esi pushl %edi - + movl 0x08(%ebp), %esi movl $(PA2KA(0xb8000)), %edi /* base of EGA text mode memory */ xorl %eax, %eax - + /* Read bits 8 - 15 of the cursor address */ movw $0x3d4, %dx movb $0xe, %al outb %al, %dx - + movw $0x3d5, %dx inb %dx, %al shl $8, %ax - + /* Read bits 0 - 7 of the cursor address */ movw $0x3d4, %dx movb $0xf, %al outb %al, %dx - + movw $0x3d5, %dx inb %dx, %al - + /* Sanity check for the cursor on screen */ cmp $2000, %ax jb early_puts_cursor_ok - + movw $1998, %ax - + early_puts_cursor_ok: - + movw %ax, %bx shl $1, %eax addl %eax, %edi - + early_puts_ploop: lodsb - + cmp $0, %al je early_puts_ploop_end - + movb $0x0e, %ah /* black background, yellow foreground */ stosw - + /* Sanity check for the cursor on the last line */ inc %bx cmp $2000, %bx jb early_puts_ploop - + /* Scroll the screen (24 rows) */ movl %esi, %edx @@ -654,36 +654,36 @@ movl $960, %ecx rep movsl - + /* Clear the 24th row */ xorl %eax, %eax movl $40, %ecx rep stosl - + /* Go to row 24 */ movl %edx, %esi movl $(PA2KA(0xb8f00)), %edi movw $1920, %bx - + jmp early_puts_ploop early_puts_ploop_end: - + /* Write bits 8 - 15 of the cursor address */ movw $0x3d4, %dx movb $0xe, %al outb %al, %dx - + movw $0x3d5, %dx movb %bh, %al outb %al, %dx - + /* Write bits 0 - 7 of the cursor address */ movw $0x3d4, %dx movb $0xf, %al outb %al, %dx - + movw $0x3d5, %dx movb %bl, %al outb %al, %dx - + /* Epilogue, restore preserved registers */ popl %edi @@ -691,7 +691,7 @@ popl %ebx leave - + #endif - + ret Index: kernel/arch/ia32/src/boot/multiboot2.S =================================================================== --- kernel/arch/ia32/src/boot/multiboot2.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/src/boot/multiboot2.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -45,5 +45,5 @@ .long multiboot2_header_end - multiboot2_header_start .long -(MULTIBOOT2_HEADER_MAGIC + MULTIBOOT2_HEADER_ARCH_I386 + (multiboot2_header_end - multiboot2_header_start)) - + /* Information request tag */ .align 8 @@ -59,5 +59,5 @@ #endif tag_info_req_end: - + /* Address tag */ .align 8 @@ -71,5 +71,5 @@ .long 0 tag_address_end: - + /* Entry address tag */ .align 8 @@ -80,5 +80,5 @@ .long multiboot2_image_start tag_entry_address_end: - + /* Flags tag */ .align 8 @@ -89,5 +89,5 @@ .long MULTIBOOT2_FLAGS_CONSOLE tag_flags_end: - + #ifdef CONFIG_FB /* Framebuffer tag */ @@ -102,5 +102,5 @@ tag_framebuffer_end: #endif - + /* Module alignment tag */ .align 8 @@ -111,5 +111,5 @@ .long 0 tag_module_align_end: - + /* Tag terminator */ .align 8 @@ -124,8 +124,8 @@ cli cld - + /* Initialize stack pointer */ movl $START_STACK, %esp - + /* * Initialize Global Descriptor Table and @@ -134,5 +134,5 @@ lgdtl bootstrap_gdtr lidtl bootstrap_idtr - + /* Kernel data + stack */ movw $GDT_SELECTOR(KDATA_DES), %cx @@ -142,49 +142,49 @@ movw %cx, %ds movw %cx, %ss - + jmpl $GDT_SELECTOR(KTEXT_DES), $multiboot2_meeting_point multiboot2_meeting_point: - + /* Save multiboot arguments */ movl %eax, multiboot_eax movl %ebx, multiboot_ebx - + #ifndef PROCESSOR_i486 - + movl $(INTEL_CPUID_LEVEL), %eax cpuid cmp $0x0, %eax /* any function > 0? */ jbe pse_unsupported - + movl $(INTEL_CPUID_STANDARD), %eax cpuid bt $(INTEL_PSE), %edx jnc pse_unsupported - + /* Map kernel and turn paging on */ call map_kernel_pse jmp stack_init - + #endif /* PROCESSOR_i486 */ - + pse_unsupported: - + /* Map kernel and turn paging on */ call map_kernel_non_pse - + stack_init: - + /* Create the first stack frame */ pushl $0 movl %esp, %ebp - + /* Call ia32_pre_main(multiboot_eax, multiboot_ebx) */ pushl multiboot_ebx pushl multiboot_eax call ia32_pre_main - + /* Call main_bsp() */ call main_bsp - + /* Not reached */ cli Index: kernel/arch/ia32/src/cpu/cpu.c =================================================================== --- kernel/arch/ia32/src/cpu/cpu.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/src/cpu/cpu.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -84,19 +84,19 @@ cpu_info_t info; uint32_t help = 0; - + CPU->arch.tss = tss_p; CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((uint8_t *) CPU->arch.tss); - + CPU->fpu_owner = NULL; - + cpuid(INTEL_CPUID_STANDARD, &info); - + CPU->arch.fi.word = info.cpuid_edx; - + if (CPU->arch.fi.bits.fxsr) fpu_fxsr(); else fpu_fsr(); - + if (CPU->arch.fi.bits.sse) { asm volatile ( @@ -108,5 +108,5 @@ ); } - + #ifndef PROCESSOR_i486 if (CPU->arch.fi.bits.sep) { @@ -132,5 +132,5 @@ && (info.cpuid_edx == AMD_CPUID_EDX)) CPU->arch.vendor = VendorAMD; - + /* * Check for Intel processor. @@ -140,5 +140,5 @@ && (info.cpuid_edx == INTEL_CPUID_EDX)) CPU->arch.vendor = VendorIntel; - + cpuid(INTEL_CPUID_STANDARD, &info); CPU->arch.family = (info.cpuid_eax >> 8) & 0x0fU; Index: kernel/arch/ia32/src/ddi/ddi.c =================================================================== --- kernel/arch/ia32/src/ddi/ddi.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/src/ddi/ddi.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -59,16 +59,16 @@ /* First, copy the I/O Permission Bitmap. */ irq_spinlock_lock(&TASK->lock, false); - + size_t ver = TASK->arch.iomapver; size_t elements = TASK->arch.iomap.elements; - + if (elements > 0) { assert(TASK->arch.iomap.bits); - + bitmap_t iomap; bitmap_initialize(&iomap, TSS_IOMAP_SIZE * 8, CPU->arch.tss->iomap); bitmap_copy(&iomap, &TASK->arch.iomap, elements); - + /* * Set the trailing bits in the last byte of the map to disable @@ -77,5 +77,5 @@ bitmap_set_range(&iomap, elements, ALIGN_UP(elements, 8) - elements); - + /* * It is safe to set the trailing eight bits because of the @@ -84,7 +84,7 @@ bitmap_set_range(&iomap, ALIGN_UP(elements, 8), 8); } - + irq_spinlock_unlock(&TASK->lock, false); - + /* * Second, adjust TSS segment limit. @@ -93,10 +93,10 @@ ptr_16_32_t cpugdtr; gdtr_store(&cpugdtr); - + descriptor_t *gdt_p = (descriptor_t *) cpugdtr.base; size_t size = bitmap_size(elements); gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + size); gdtr_load(&cpugdtr); - + /* * Before we load new TSS limit, the current TSS descriptor @@ -105,5 +105,5 @@ gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL; tr_load(GDT_SELECTOR(TSS_DES)); - + /* * Update the generation count so that faults caused by Index: kernel/arch/ia32/src/drivers/i8254.c =================================================================== --- kernel/arch/ia32/src/drivers/i8254.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/src/drivers/i8254.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -89,5 +89,5 @@ i8254_irq.handler = i8254_irq_handler; irq_register(&i8254_irq); - + i8254_normal_operation(); } @@ -111,9 +111,9 @@ pio_write_8(CLK_PORT1, 0xff); pio_write_8(CLK_PORT1, 0xff); - + uint8_t not_ok; uint32_t t1; uint32_t t2; - + do { /* will read both status and count */ @@ -123,11 +123,11 @@ t1 |= pio_read_8(CLK_PORT1) << 8; } while (not_ok); - + asm_delay_loop(LOOPS); - + pio_write_8(CLK_PORT4, 0xd2); t2 = pio_read_8(CLK_PORT1); t2 |= pio_read_8(CLK_PORT1) << 8; - + /* * We want to determine the overhead of the calibrating mechanism. @@ -136,21 +136,21 @@ uint32_t o1 = pio_read_8(CLK_PORT1); o1 |= pio_read_8(CLK_PORT1) << 8; - + asm_fake_loop(LOOPS); - + pio_write_8(CLK_PORT4, 0xd2); uint32_t o2 = pio_read_8(CLK_PORT1); o2 |= pio_read_8(CLK_PORT1) << 8; - + CPU->delay_loop_const = ((MAGIC_NUMBER * LOOPS) / 1000) / ((t1 - t2) - (o1 - o2)) + (((MAGIC_NUMBER * LOOPS) / 1000) % ((t1 - t2) - (o1 - o2)) ? 1 : 0); - + uint64_t clk1 = get_cycle(); delay(1 << SHIFT); uint64_t clk2 = get_cycle(); - + CPU->frequency_mhz = (clk2 - clk1) >> SHIFT; - + return; } Index: kernel/arch/ia32/src/fpu_context.c =================================================================== --- kernel/arch/ia32/src/fpu_context.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/src/fpu_context.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -59,5 +59,5 @@ X87_DENORMAL_EXC_FLAG = (1 << 1), X87_INVALID_OP_EXC_FLAG = (1 << 0), - + X87_ALL_MASK = X87_PRECISION_MASK | X87_UNDERFLOW_MASK | X87_OVERFLOW_MASK | X87_ZERO_DIV_MASK | X87_DENORMAL_OP_MASK | X87_INVALID_OP_MASK, }; @@ -129,5 +129,5 @@ uint32_t help0 = 0; uint32_t help1 = 0; - + asm volatile ( "fninit\n" Index: kernel/arch/ia32/src/ia32.c =================================================================== --- kernel/arch/ia32/src/ia32.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/src/ia32.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -92,5 +92,5 @@ multiboot_info_parse(signature, (multiboot_info_t *) info); multiboot2_info_parse(signature, (multiboot2_info_t *) info); - + #ifdef CONFIG_SMP /* Copy AP bootstrap routines below 1 MB. */ @@ -107,5 +107,5 @@ interrupt_init(); bios_init(); - + /* PIC */ i8259_init(); @@ -120,16 +120,16 @@ /* Initialize IRQ routing */ irq_init(IRQ_COUNT, IRQ_COUNT); - + /* hard clock */ i8254_init(); - + #if (defined(CONFIG_FB) || defined(CONFIG_EGA)) bool bfb = false; #endif - + #ifdef CONFIG_FB bfb = bfb_init(); #endif - + #ifdef CONFIG_EGA if (!bfb) { @@ -139,5 +139,5 @@ } #endif - + /* Merge all memory zones to 1 big zone */ zone_merge_all(); @@ -220,5 +220,5 @@ } #endif - + if (irqs_info != NULL) sysinfo_set_item_val(irqs_info, NULL, true); Index: kernel/arch/ia32/src/interrupt.c =================================================================== --- kernel/arch/ia32/src/interrupt.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/src/interrupt.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -72,16 +72,16 @@ "efl=%0#10" PRIx32 "\terr=%0#10" PRIx32 "\n", istate->cs, istate->eip, istate->eflags, istate->error_word); - + printf("ds =%0#10" PRIx32 "\tes =%0#10" PRIx32 "\t" "fs =%0#10" PRIx32 "\tgs =%0#10" PRIx32 "\n", istate->ds, istate->es, istate->fs, istate->gs); - + if (istate_from_uspace(istate)) printf("ss =%0#10" PRIx32 "\n", istate->ss); - + printf("eax=%0#10" PRIx32 "\tebx=%0#10" PRIx32 "\t" "ecx=%0#10" PRIx32 "\tedx=%0#10" PRIx32 "\n", istate->eax, istate->ebx, istate->ecx, istate->edx); - + printf("esi=%0#10" PRIx32 "\tedi=%0#10" PRIx32 "\t" "ebp=%0#10" PRIx32 "\tesp=%0#10" PRIxn "\n", @@ -119,5 +119,5 @@ size_t ver = TASK->arch.iomapver; irq_spinlock_unlock(&TASK->lock, false); - + if (CPU->arch.iomapver_copy != ver) { /* @@ -149,5 +149,5 @@ : [mxcsr] "=m" (mxcsr) ); - + fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR=%#0" PRIx32 ".", mxcsr); @@ -185,10 +185,10 @@ { assert(n >= IVT_IRQBASE); - + unsigned int inum = n - IVT_IRQBASE; bool ack = false; assert(inum < IRQ_COUNT); assert((inum != IRQ_PIC_SPUR) && (inum != IRQ_PIC1)); - + irq_t *irq = irq_dispatch_and_lock(inum); if (irq) { @@ -196,5 +196,5 @@ * The IRQ handler was found. */ - + if (irq->preack) { /* Send EOI before processing the interrupt */ @@ -212,5 +212,5 @@ #endif } - + if (!ack) trap_virtual_eoi(); @@ -220,8 +220,8 @@ { unsigned int i; - + for (i = 0; i < IVT_ITEMS; i++) exc_register(i, "null", false, (iroutine_t) null_interrupt); - + for (i = 0; i < IRQ_COUNT; i++) { if ((i != IRQ_PIC_SPUR) && (i != IRQ_PIC1)) @@ -229,5 +229,5 @@ (iroutine_t) irq_interrupt); } - + exc_register(VECTOR_DE, "de_fault", true, (iroutine_t) de_fault); exc_register(VECTOR_NM, "nm_fault", true, (iroutine_t) nm_fault); @@ -235,5 +235,5 @@ exc_register(VECTOR_GP, "gp_fault", true, (iroutine_t) gp_fault); exc_register(VECTOR_XM, "simd_fp", true, (iroutine_t) simd_fp_exception); - + #ifdef CONFIG_SMP exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", true, Index: kernel/arch/ia32/src/mm/frame.c =================================================================== --- kernel/arch/ia32/src/mm/frame.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/src/mm/frame.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -54,9 +54,9 @@ { unsigned int i; - + for (i = 0; i < e820counter; i++) { uint64_t base64 = e820table[i].base_address; uint64_t size64 = e820table[i].size; - + #ifdef KARCH_ia32 /* @@ -65,15 +65,15 @@ if (base64 >= PHYSMEM_LIMIT32) continue; - + if (base64 + size64 > PHYSMEM_LIMIT32) size64 = PHYSMEM_LIMIT32 - base64; #endif - + uintptr_t base = (uintptr_t) base64; size_t size = (size_t) size64; - + if (!frame_adjust_zone_bounds(low, &base, &size)) continue; - + if (e820table[i].type == MEMMAP_MEMORY_AVAILABLE) { /* To be safe, make the available zone possibly smaller */ @@ -81,9 +81,9 @@ uint64_t new_size = ALIGN_DOWN(size - (new_base - base), FRAME_SIZE); - + size_t count = SIZE2FRAMES(new_size); pfn_t pfn = ADDR2PFN(new_base); pfn_t conf; - + if (low) { if ((minconf < pfn) || (minconf >= pfn + count)) @@ -105,5 +105,5 @@ uint64_t new_size = ALIGN_UP(size + (base - new_base), FRAME_SIZE); - + zone_create(ADDR2PFN(new_base), SIZE2FRAMES(new_size), 0, ZONE_FIRMWARE); @@ -113,5 +113,5 @@ uint64_t new_size = ALIGN_UP(size + (base - new_base), FRAME_SIZE); - + zone_create(ADDR2PFN(new_base), SIZE2FRAMES(new_size), 0, ZONE_RESERVED); @@ -133,13 +133,13 @@ unsigned int i; printf("[base ] [size ] [name ]\n"); - + for (i = 0; i < e820counter; i++) { const char *name; - + if (e820table[i].type <= MEMMAP_MEMORY_UNUSABLE) name = e820names[e820table[i].type]; else name = "invalid"; - + printf("%#018" PRIx64 " %#018" PRIx64" %s\n", e820table[i].base_address, e820table[i].size, name); @@ -150,8 +150,8 @@ { pfn_t minconf; - + if (config.cpu_active == 1) { minconf = 1; - + #ifdef CONFIG_SMP minconf = max(minconf, @@ -159,10 +159,10 @@ hardcoded_unmapped_kdata_size)); #endif - + init_e820_memory(minconf, true); - + /* Reserve frame 0 (BIOS data) */ frame_mark_unavailable(0, 1); - + #ifdef CONFIG_SMP /* Reserve AP real mode bootstrap memory */ Index: kernel/arch/ia32/src/mm/page.c =================================================================== --- kernel/arch/ia32/src/mm/page.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/src/mm/page.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -54,5 +54,5 @@ uintptr_t cur; int flags; - + if (config.cpu_active > 1) { /* Fast path for non-boot CPUs */ @@ -63,5 +63,5 @@ page_mapping_operations = &pt_mapping_operations; - + /* * PA2KA(identity) mapping for all low-memory frames. @@ -74,8 +74,8 @@ } page_table_unlock(AS_KERNEL, true); - + exc_register(VECTOR_PF, "page_fault", true, (iroutine_t) page_fault); write_cr3((uintptr_t) AS_KERNEL->genarch.page_table); - + paging_on(); } @@ -85,15 +85,15 @@ uintptr_t badvaddr; pf_access_t access; - + badvaddr = read_cr2(); - + if (istate->error_word & PFERR_CODE_RSVD) panic("Reserved bit set in page directory."); - + if (istate->error_word & PFERR_CODE_RW) access = PF_ACCESS_WRITE; else access = PF_ACCESS_READ; - + (void) as_page_fault(badvaddr, access, istate); } Index: kernel/arch/ia32/src/pm.c =================================================================== --- kernel/arch/ia32/src/pm.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/src/pm.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -269,5 +269,5 @@ gdtr_load(&gdtr); idtr_load(&idtr); - + /* * Each CPU has its private GDT and TSS. @@ -289,9 +289,9 @@ tss_initialize(tss_p); - + gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL; gdt_p[TSS_DES].special = 1; gdt_p[TSS_DES].granularity = 0; - + gdt_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p); gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1); @@ -302,5 +302,5 @@ */ tr_load(GDT_SELECTOR(TSS_DES)); - + /* Disable I/O on nonprivileged levels and clear NT flag. */ write_eflags(read_eflags() & ~(EFLAGS_IOPL | EFLAGS_NT)); Index: kernel/arch/ia32/src/proc/scheduler.c =================================================================== --- kernel/arch/ia32/src/proc/scheduler.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/src/proc/scheduler.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -59,5 +59,5 @@ { uintptr_t kstk = (uintptr_t) &THREAD->kstack[STACK_SIZE]; - + #ifndef PROCESSOR_i486 if (CPU->arch.fi.bits.sep) { @@ -66,5 +66,5 @@ } #endif - + /* Set kernel stack for CPL3 -> CPL0 switch via interrupt */ CPU->arch.tss->esp0 = kstk; Index: kernel/arch/ia32/src/smp/ap.S =================================================================== --- kernel/arch/ia32/src/smp/ap.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/src/smp/ap.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -62,5 +62,5 @@ /* initialize Global Descriptor Table register */ lgdtl ap_gdtr - + /* switch to protected mode */ movl %cr0, %eax @@ -68,5 +68,5 @@ movl %eax, %cr0 jmpl $KTEXT, $jump_to_kernel - BOOT_OFFSET + AP_BOOT_OFFSET - + jump_to_kernel: .code32 @@ -84,7 +84,7 @@ */ call map_kernel_pse - + addl $PA2KA(0), %esp /* PA2KA(ctx.sp) */ - + /* create the first stack frame */ pushl $0 Index: kernel/arch/ia32/src/smp/apic.c =================================================================== --- kernel/arch/ia32/src/smp/apic.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/src/smp/apic.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -164,5 +164,5 @@ { l_apic_id_t idreg; - + idreg.value = l_apic[L_APIC_ID]; return idreg.apic_id; @@ -174,10 +174,10 @@ exc_register(VECTOR_APIC_SPUR, "apic_spurious", false, (iroutine_t) apic_spurious); - + enable_irqs_function = io_apic_enable_irqs; disable_irqs_function = io_apic_disable_irqs; eoi_function = l_apic_eoi; irqs_info = "apic"; - + /* * Configure interrupt routing. @@ -186,5 +186,5 @@ */ io_apic_disable_irqs(0xffffU); - + irq_initialize(&l_apic_timer_irq); l_apic_timer_irq.preack = true; @@ -193,18 +193,18 @@ l_apic_timer_irq.handler = l_apic_timer_irq_handler; irq_register(&l_apic_timer_irq); - + uint8_t i; for (i = 0; i < IRQ_COUNT; i++) { int pin; - + if ((pin = smp_irq_to_pin(i)) != -1) io_apic_change_ioredtbl((uint8_t) pin, DEST_ALL, (uint8_t) (IVT_IRQBASE + i), LOPRI); } - + /* * Ensure that io_apic has unique ID. */ io_apic_id_t idreg; - + idreg.value = io_apic_read(IOAPICID); if ((1 << idreg.apic_id) & apic_id_mask) { /* See if IO APIC ID is used already */ @@ -217,5 +217,5 @@ } } - + /* * Configure the BSP's lapic. @@ -223,5 +223,5 @@ l_apic_init(); l_apic_debug(); - + bsp_l_apic = l_apic_id(); } @@ -237,7 +237,7 @@ { esr_t esr; - + esr.value = l_apic[ESR]; - + if (esr.err_bitmap) { log_begin(LF_ARCH, LVL_ERROR); @@ -259,5 +259,5 @@ log_end(); } - + return !esr.err_bitmap; } @@ -267,5 +267,5 @@ { icr_t icr; - + do { icr.lo = l_apic[ICRlo]; @@ -286,8 +286,8 @@ /* Wait for a destination cpu to accept our previous ipi. */ l_apic_wait_for_delivery(); - + icr.lo = l_apic[ICRlo]; icr.hi = l_apic[ICRhi]; - + icr.delmod = DELMOD_FIXED; icr.destmod = DESTMOD_PHYS; @@ -301,5 +301,5 @@ l_apic[ICRhi] = icr.hi; l_apic[ICRlo] = icr.lo; - + return apic_poll_errors(); } @@ -318,5 +318,5 @@ /* Wait for a destination cpu to accept our previous ipi. */ l_apic_wait_for_delivery(); - + icr.lo = l_apic[ICRlo]; icr.delmod = DELMOD_FIXED; @@ -326,7 +326,7 @@ icr.trigger_mode = TRIGMOD_LEVEL; icr.vector = vector; - + l_apic[ICRlo] = icr.lo; - + return apic_poll_errors(); } @@ -345,8 +345,8 @@ */ icr_t icr; - + icr.lo = l_apic[ICRlo]; icr.hi = l_apic[ICRhi]; - + icr.delmod = DELMOD_INIT; icr.destmod = DESTMOD_PHYS; @@ -356,8 +356,8 @@ icr.vector = 0; icr.dest = apicid; - + l_apic[ICRhi] = icr.hi; l_apic[ICRlo] = icr.lo; - + /* * According to MP Specification, 20us should be enough to @@ -365,8 +365,8 @@ */ delay(20); - + if (!apic_poll_errors()) return 0; - + l_apic_wait_for_delivery(); @@ -379,10 +379,10 @@ icr.vector = 0; l_apic[ICRlo] = icr.lo; - + /* * Wait 10ms as MP Specification specifies. */ delay(10000); - + if (!is_82489DX_apic(l_apic[LAVR])) { /* @@ -402,5 +402,5 @@ } } - + return apic_poll_errors(); } @@ -411,32 +411,32 @@ /* Initialize LVT Error register. */ lvt_error_t error; - + error.value = l_apic[LVT_Err]; error.masked = true; l_apic[LVT_Err] = error.value; - + /* Initialize LVT LINT0 register. */ lvt_lint_t lint; - + lint.value = l_apic[LVT_LINT0]; lint.masked = true; l_apic[LVT_LINT0] = lint.value; - + /* Initialize LVT LINT1 register. */ lint.value = l_apic[LVT_LINT1]; lint.masked = true; l_apic[LVT_LINT1] = lint.value; - + /* Task Priority Register initialization. */ tpr_t tpr; - + tpr.value = l_apic[TPR]; tpr.pri_sc = 0; tpr.pri = 0; l_apic[TPR] = tpr.value; - + /* Spurious-Interrupt Vector Register initialization. */ svr_t svr; - + svr.value = l_apic[SVR]; svr.vector = VECTOR_APIC_SPUR; @@ -444,11 +444,11 @@ svr.focus_checking = true; l_apic[SVR] = svr.value; - + if (CPU->arch.family >= 6) enable_l_apic_in_msr(); - + /* Interrupt Command Register initialization. */ icr_t icr; - + icr.lo = l_apic[ICRlo]; icr.delmod = DELMOD_INIT; @@ -458,15 +458,15 @@ icr.trigger_mode = TRIGMOD_LEVEL; l_apic[ICRlo] = icr.lo; - + /* Timer Divide Configuration Register initialization. */ tdcr_t tdcr; - + tdcr.value = l_apic[TDCR]; tdcr.div_value = DIVIDE_1; l_apic[TDCR] = tdcr.value; - + /* Program local timer. */ lvt_tm_t tm; - + tm.value = l_apic[LVT_Tm]; tm.vector = VECTOR_CLK; @@ -474,5 +474,5 @@ tm.masked = false; l_apic[LVT_Tm] = tm.value; - + /* * Measure and configure the timer to generate timer @@ -481,24 +481,24 @@ uint32_t t1 = l_apic[CCRT]; l_apic[ICRT] = 0xffffffff; - + while (l_apic[CCRT] == t1); - + t1 = l_apic[CCRT]; delay(1000000 / HZ); uint32_t t2 = l_apic[CCRT]; - + l_apic[ICRT] = t1 - t2; - + /* Program Logical Destination Register. */ assert(CPU->id < 8); ldr_t ldr; - + ldr.value = l_apic[LDR]; ldr.id = (uint8_t) (1 << CPU->id); l_apic[LDR] = ldr.value; - + /* Program Destination Format Register for Flat mode. */ dfr_t dfr; - + dfr.value = l_apic[DFR]; dfr.model = MODEL_FLAT; @@ -519,5 +519,5 @@ log_printf("LVT on cpu%u, LAPIC ID: %" PRIu8 "\n", CPU->id, l_apic_id()); - + lvt_tm_t tm; tm.value = l_apic[LVT_Tm]; @@ -525,5 +525,5 @@ tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]); - + lvt_lint_t lint; lint.value = l_apic[LVT_LINT0]; @@ -532,5 +532,5 @@ intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); - + lint.value = l_apic[LVT_LINT1]; log_printf("LVT LINT1: vector=%" PRIu8 ", %s, %s, %s, irr=%u, %s, %s\n", @@ -538,5 +538,5 @@ intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); - + lvt_error_t error; error.value = l_apic[LVT_Err]; @@ -557,5 +557,5 @@ { io_regsel_t regsel; - + regsel.value = io_apic[IOREGSEL]; regsel.reg_addr = address; @@ -573,5 +573,5 @@ { io_regsel_t regsel; - + regsel.value = io_apic[IOREGSEL]; regsel.reg_addr = address; @@ -592,14 +592,14 @@ { unsigned int dlvr; - + if (flags & LOPRI) dlvr = DELMOD_LOWPRI; else dlvr = DELMOD_FIXED; - + io_redirection_reg_t reg; reg.lo = io_apic_read((uint8_t) (IOREDTBL + pin * 2)); reg.hi = io_apic_read((uint8_t) (IOREDTBL + pin * 2 + 1)); - + reg.dest = dest; reg.destmod = DESTMOD_LOGIC; @@ -608,5 +608,5 @@ reg.delmod = dlvr; reg.intvec = vec; - + io_apic_write((uint8_t) (IOREDTBL + pin * 2), reg.lo); io_apic_write((uint8_t) (IOREDTBL + pin * 2 + 1), reg.hi); @@ -630,10 +630,10 @@ if (pin != -1) { io_redirection_reg_t reg; - + reg.lo = io_apic_read((uint8_t) (IOREDTBL + pin * 2)); reg.masked = true; io_apic_write((uint8_t) (IOREDTBL + pin * 2), reg.lo); } - + } } @@ -657,10 +657,10 @@ if (pin != -1) { io_redirection_reg_t reg; - + reg.lo = io_apic_read((uint8_t) (IOREDTBL + pin * 2)); reg.masked = false; io_apic_write((uint8_t) (IOREDTBL + pin * 2), reg.lo); } - + } } Index: kernel/arch/ia32/src/smp/mps.c =================================================================== --- kernel/arch/ia32/src/smp/mps.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/src/smp/mps.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -75,5 +75,5 @@ { assert(i < processor_entry_cnt); - + return processor_entries[i].l_apic_id; } @@ -82,5 +82,5 @@ { assert(i < processor_entry_cnt); - + /* * FIXME: The current local APIC driver limits usable @@ -90,5 +90,5 @@ if (i > 7) return false; - + return ((processor_entries[i].cpu_flags & 0x01) == 0x01); } @@ -97,5 +97,5 @@ { assert(i < processor_entry_cnt); - + return ((processor_entries[i].cpu_flags & 0x02) == 0x02); } @@ -104,5 +104,5 @@ { size_t i; - + for (i = 0; i < io_intr_entry_cnt; i++) { if (io_intr_entries[i].src_bus_irq == irq && @@ -110,5 +110,5 @@ return io_intr_entries[i].dst_io_apic_pin; } - + return -1; } @@ -131,8 +131,8 @@ unsigned int i; uint8_t sum; - + for (i = 0, sum = 0; i < 16; i++) sum = (uint8_t) (sum + base[i]); - + return (sum == 0); } @@ -147,16 +147,16 @@ uint8_t sum; uint16_t i; - + /* Compute the checksum for the base table */ for (i = 0, sum = 0; i < ct->base_table_length; i++) sum = (uint8_t) (sum + base[i]); - + if (sum) return false; - + /* Compute the checksum for the extended table */ for (i = 0, sum = 0; i < ct->ext_table_length; i++) sum = (uint8_t) (sum + ext[i]); - + return (sum == ct->ext_table_checksum); } @@ -169,5 +169,5 @@ if ((pr->cpu_flags & (1 << 0)) == 0) return; - + apic_id_mask |= (1 << pr->l_apic_id); } @@ -177,8 +177,8 @@ #ifdef MPSCT_VERBOSE char buf[7]; - + memcpy((void *) buf, (void *) bus->bus_type, 6); buf[6] = 0; - + log(LF_ARCH, LVL_DEBUG, "MPS: bus=%" PRIu8 " (%s)", bus->bus_id, buf); #endif @@ -190,5 +190,5 @@ if ((ioa->io_apic_flags & 1) == 0) return; - + if (io_apic_cnt++ > 0) { /* @@ -197,5 +197,5 @@ return; } - + io_apic = (uint32_t *) (uintptr_t) ioa->io_apic; } @@ -207,5 +207,5 @@ log_begin(LF_ARCH, LVL_DEBUG); log_printf("MPS: "); - + switch (iointr->intr_type) { case 0: @@ -222,7 +222,7 @@ break; } - + log_printf(", "); - + switch (iointr->poel & 3) { case 0: @@ -239,7 +239,7 @@ break; } - + log_printf(", "); - + switch ((iointr->poel >> 2) & 3) { case 0: @@ -256,5 +256,5 @@ break; } - + log_printf(", bus=%" PRIu8 " irq=%" PRIu8 " io_apic=%" PRIu8" pin=%" PRIu8, iointr->src_bus_id, iointr->src_bus_irq, @@ -270,5 +270,5 @@ log_begin(LF_ARCH, LVL_DEBUG); log_printf("MPS: "); - + switch (lintr->intr_type) { case 0: @@ -285,7 +285,7 @@ break; } - + log_printf(", "); - + switch (lintr->poel & 3) { case 0: @@ -302,7 +302,7 @@ break; } - + log_printf(", "); - + switch ((lintr->poel >> 2) & 3) { case 0: @@ -319,5 +319,5 @@ break; } - + log_printf(", bus=%" PRIu8 " irq=%" PRIu8 " l_apic=%" PRIu8" pin=%" PRIu8, lintr->src_bus_id, lintr->src_bus_irq, @@ -331,5 +331,5 @@ uint8_t *ext = (uint8_t *) ct + ct->base_table_length; uint8_t *cur; - + for (cur = ext; cur < ext + ct->ext_table_length; cur += cur[CT_EXT_ENTRY_LEN]) { @@ -349,20 +349,20 @@ return; } - + if (!mps_ct_check()) { log(LF_ARCH, LVL_WARN, "MPS: Wrong ct checksum"); return; } - + if (ct->oem_table) { log(LF_ARCH, LVL_WARN, "MPS: ct->oem_table not supported"); return; } - + l_apic = (uint32_t *) (uintptr_t) ct->l_apic; - + uint8_t *cur = &ct->base_table[0]; uint16_t i; - + for (i = 0; i < ct->entry_count; i++) { switch (*cur) { @@ -411,5 +411,5 @@ } } - + /* * Process extended entries. @@ -432,5 +432,5 @@ unsigned int j; unsigned int length[2] = { 1024, 64 * 1024 }; - + /* * Find MP Floating Pointer Structure @@ -439,5 +439,5 @@ * 2. search 64K starting at 0xf0000 */ - + addr[0] = (uint8_t *) PA2KA(ebda ? ebda : 639 * 1024); for (i = 0; i < 2; i++) { @@ -450,10 +450,10 @@ } } - + return; - + fs_found: log(LF_ARCH, LVL_NOTE, "%p: MPS Floating Pointer Structure", fs); - + if ((fs->config_type == 0) && (fs->configuration_table)) { if (fs->mpfib2 >> 7) { @@ -461,10 +461,10 @@ return; } - + ct = (struct mps_ct *) PA2KA((uintptr_t) fs->configuration_table); configure_via_ct(); } else configure_via_default(fs->config_type); - + if (processor_entry_cnt > 0) config.cpu_count = processor_entry_cnt; Index: kernel/arch/ia32/src/smp/smp.c =================================================================== --- kernel/arch/ia32/src/smp/smp.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/src/smp/smp.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -68,10 +68,10 @@ ops = &madt_config_operations; } - + if (config.cpu_count == 1) { mps_init(); ops = &mps_config_operations; } - + if (config.cpu_count > 1) { l_apic = (uint32_t *) km_map((uintptr_t) l_apic, PAGE_SIZE, @@ -86,5 +86,5 @@ assert(ops != NULL); assert(cpus != NULL); - + for (unsigned int i = 0; i < config.cpu_count; ++i) { cpus[i].arch.id = ops->cpu_apic_id(i); @@ -102,5 +102,5 @@ { unsigned int i; - + assert(ops != NULL); @@ -110,10 +110,10 @@ */ cpu_arch_id_init(); - + /* * We need to access data in frame 0. * We boldly make use of kernel address space mapping. */ - + /* * Set the warm-reset vector to the real-mode address of 4K-aligned ap_boot() @@ -122,5 +122,5 @@ (uint16_t) (((uintptr_t) ap_boot) >> 4); /* segment */ *((uint16_t *) (PA2KA(0x467 + 2))) = 0; /* offset */ - + /* * Save 0xa to address 0xf of the CMOS RAM. @@ -129,8 +129,8 @@ pio_write_8((ioport8_t *) 0x70, 0xf); pio_write_8((ioport8_t *) 0x71, 0xa); - + pic_disable_irqs(0xffff); apic_init(); - + for (i = 0; i < config.cpu_count; i++) { /* @@ -139,5 +139,5 @@ if (!ops->cpu_enabled(i)) continue; - + /* * The bootstrap processor is already up. @@ -145,5 +145,5 @@ if (ops->cpu_bootstrap(i)) continue; - + if (ops->cpu_apic_id(i) == bsp_l_apic) { log(LF_ARCH, LVL_ERROR, "kmp: bad processor entry #%u, " @@ -151,9 +151,9 @@ continue; } - + /* * Prepare new GDT for CPU in question. */ - + /* XXX Flag FRAME_LOW_4_GiB was removed temporarily, * it needs to be replaced by a generic fuctionality of @@ -165,5 +165,5 @@ if (!gdt_new) panic("Cannot allocate memory for GDT."); - + memcpy(gdt_new, gdt, GDT_ITEMS * sizeof(descriptor_t)); memsetb(&gdt_new[TSS_DES], sizeof(descriptor_t), 0); @@ -171,5 +171,5 @@ protected_ap_gdtr.base = KA2PA((uintptr_t) gdt_new); gdtr.base = (uintptr_t) gdt_new; - + if (l_apic_send_init_ipi(ops->cpu_apic_id(i))) { /* Index: kernel/arch/ia32/src/userspace.c =================================================================== --- kernel/arch/ia32/src/userspace.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia32/src/userspace.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -50,9 +50,9 @@ { uint32_t eflags = read_eflags(); - + asm volatile ( /* Set up GS register (virtual register segment) */ "movl %[vreg_des], %%gs\n" - + "pushl %[udata_des]\n" "pushl %[stack_top]\n" @@ -61,8 +61,8 @@ "pushl %[entry]\n" "movl %[uarg], %%eax\n" - + /* %edi is defined to hold pcb_ptr - set it to 0 */ "xorl %%edi, %%edi\n" - + "iret\n" : @@ -77,5 +77,5 @@ [vreg_des] "r" (GDT_SELECTOR(VREG_DES)) : "eax"); - + /* Unreachable */ while (1); Index: kernel/arch/ia64/include/arch/asm.h =================================================================== --- kernel/arch/ia64/include/arch/asm.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/include/arch/asm.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -51,5 +51,5 @@ return legacyio_virt_base + (((prt >> 2) << 12) | (prt & 0xfff)); } - + NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v) { @@ -58,5 +58,5 @@ else *port = v; - + asm volatile ( "mf\n" @@ -72,5 +72,5 @@ else *port = v; - + asm volatile ( "mf\n" @@ -86,5 +86,5 @@ else *port = v; - + asm volatile ( "mf\n" @@ -112,5 +112,5 @@ ::: "memory" ); - + return v; } @@ -134,5 +134,5 @@ ::: "memory" ); - + return v; } @@ -141,10 +141,10 @@ { uint32_t v; - - asm volatile ( - "mf\n" - ::: "memory" - ); - + + asm volatile ( + "mf\n" + ::: "memory" + ); + if (port < (ioport32_t *) IO_SPACE_BOUNDARY) v = *((ioport32_t *) p2a(port)); @@ -169,10 +169,10 @@ { uint64_t value; - + asm volatile ( "mov %[value] = r12" : [value] "=r" (value) ); - + return (value & (~(STACK_SIZE / 2 - 1))); } @@ -186,10 +186,10 @@ { uint64_t v; - + asm volatile ( "mov %[value] = psr\n" : [value] "=r" (v) ); - + return v; } @@ -203,10 +203,10 @@ { uint64_t v; - + asm volatile ( "mov %[value] = cr.iva\n" : [value] "=r" (v) ); - + return v; } @@ -234,10 +234,10 @@ { uint64_t v; - + asm volatile ( "mov %[value] = cr.ivr\n" : [value] "=r" (v) ); - + return v; } @@ -246,10 +246,10 @@ { uint64_t v; - + asm volatile ( "mov %[value] = cr64\n" : [value] "=r" (v) ); - + return v; } @@ -276,10 +276,10 @@ { uint64_t v; - + asm volatile ( "mov %[value] = ar.itc\n" : [value] "=r" (v) ); - + return v; } @@ -306,10 +306,10 @@ { uint64_t v; - + asm volatile ( "mov %[value] = cr.itm\n" : [value] "=r" (v) ); - + return v; } @@ -323,10 +323,10 @@ { uint64_t v; - + asm volatile ( "mov %[value] = cr.itv\n" : [value] "=r" (v) ); - + return v; } @@ -366,10 +366,10 @@ { uint64_t v; - + asm volatile ( "mov %[value] = cr.tpr\n" : [value] "=r" (v) ); - + return v; } @@ -399,5 +399,5 @@ { uint64_t v; - + asm volatile ( "mov %[value] = psr\n" @@ -406,5 +406,5 @@ : [mask] "i" (PSR_I_MASK) ); - + return (ipl_t) v; } @@ -421,5 +421,5 @@ { uint64_t v; - + asm volatile ( "mov %[value] = psr\n" @@ -430,5 +430,5 @@ : [mask] "i" (PSR_I_MASK) ); - + return (ipl_t) v; } Index: kernel/arch/ia64/include/arch/atomic.h =================================================================== --- kernel/arch/ia64/include/arch/atomic.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/include/arch/atomic.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -41,5 +41,5 @@ { atomic_count_t v; - + asm volatile ( "movl %[v] = 0x1;;\n" @@ -48,5 +48,5 @@ [count] "+m" (val->count) ); - + return v; } @@ -62,5 +62,5 @@ { atomic_count_t v; - + asm volatile ( "fetchadd8.rel %[v] = %[count], 1\n" @@ -73,5 +73,5 @@ { atomic_count_t v; - + asm volatile ( "fetchadd8.rel %[v] = %[count], -1\n" @@ -84,5 +84,5 @@ { atomic_count_t v; - + asm volatile ( "fetchadd8.rel %[v] = %[count], 1\n" @@ -90,5 +90,5 @@ [count] "+m" (val->count) ); - + return (v + 1); } @@ -97,5 +97,5 @@ { atomic_count_t v; - + asm volatile ( "fetchadd8.rel %[v] = %[count], -1\n" @@ -103,5 +103,5 @@ [count] "+m" (val->count) ); - + return (v - 1); } @@ -110,5 +110,5 @@ { atomic_count_t v; - + asm volatile ( "fetchadd8.rel %[v] = %[count], 1\n" @@ -116,5 +116,5 @@ [count] "+m" (val->count) ); - + return v; } @@ -123,5 +123,5 @@ { atomic_count_t v; - + asm volatile ( "fetchadd8.rel %[v] = %[count], -1\n" @@ -129,5 +129,5 @@ [count] "+m" (val->count) ); - + return v; } Index: kernel/arch/ia64/include/arch/bootinfo.h =================================================================== --- kernel/arch/ia64/include/arch/bootinfo.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/include/arch/bootinfo.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -44,5 +44,5 @@ char name[BOOTINFO_TASK_NAME_BUFLEN]; } binit_task_t; - + typedef struct { size_t cnt; @@ -58,8 +58,8 @@ typedef struct { binit_t taskmap; - + memmap_item_t memmap[MEMMAP_ITEMS]; unsigned int memmap_items; - + sysarg_t *sapic; unsigned long sys_freq; Index: kernel/arch/ia64/include/arch/cpu.h =================================================================== --- kernel/arch/ia64/include/arch/cpu.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/include/arch/cpu.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -66,5 +66,5 @@ { uint64_t v; - + asm volatile ( "mov %[v] = cpuid[%[r]]\n" @@ -72,5 +72,5 @@ : [r] "r" (n) ); - + return v; } Index: kernel/arch/ia64/include/arch/istate.h =================================================================== --- kernel/arch/ia64/include/arch/istate.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/include/arch/istate.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -65,5 +65,5 @@ { /* FIXME */ - + return 0; } Index: kernel/arch/ia64/include/arch/mm/page.h =================================================================== --- kernel/arch/ia64/include/arch/mm/page.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/include/arch/mm/page.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -117,5 +117,5 @@ unsigned int ed : 1; unsigned int ig1 : 11; - + /* Word 1 */ unsigned int : 2; @@ -123,8 +123,8 @@ unsigned int key : 24; unsigned int : 32; - + /* Word 2 */ union vhpt_tag tag; - + /* Word 3 */ uint64_t ig3 : 64; @@ -136,13 +136,13 @@ unsigned long long ig0 : 52; unsigned int ig1 : 11; - + /* Word 1 */ unsigned int : 2; unsigned int ps : 6; unsigned long long ig2 : 56; - + /* Word 2 */ union vhpt_tag tag; - + /* Word 3 */ uint64_t ig3 : 64; @@ -194,5 +194,5 @@ { uint64_t ret; - + asm volatile ( "thash %[ret] = %[va]\n" @@ -200,5 +200,5 @@ : [va] "r" (va) ); - + return ret; } @@ -216,5 +216,5 @@ { uint64_t ret; - + asm volatile ( "ttag %[ret] = %[va]\n" @@ -222,5 +222,5 @@ : [va] "r" (va) ); - + return ret; } @@ -235,7 +235,7 @@ { uint64_t ret; - + assert(i < REGION_REGISTERS); - + asm volatile ( "mov %[ret] = rr[%[index]]\n" @@ -243,5 +243,5 @@ : [index] "r" (i << VRN_SHIFT) ); - + return ret; } @@ -255,5 +255,5 @@ { assert(i < REGION_REGISTERS); - + asm volatile ( "mov rr[%[index]] = %[value]\n" @@ -270,10 +270,10 @@ { uint64_t ret; - + asm volatile ( "mov %[ret] = cr.pta\n" : [ret] "=r" (ret) ); - + return ret; } Index: kernel/arch/ia64/include/arch/mm/tlb.h =================================================================== --- kernel/arch/ia64/include/arch/mm/tlb.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/include/arch/mm/tlb.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -63,5 +63,5 @@ unsigned int ed : 1; unsigned int ig1 : 11; - + /* Word 1 */ unsigned int : 2; Index: kernel/arch/ia64/include/arch/mm/vhpt.h =================================================================== --- kernel/arch/ia64/include/arch/mm/vhpt.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/include/arch/mm/vhpt.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -32,5 +32,5 @@ /** @file */ - + #ifndef KERN_ia64_VHPT_H_ #define KERN_ia64_VHPT_H_ @@ -44,8 +44,8 @@ { vhpt_entry_t ventry; - + ventry.word[0] = tentry.word[0]; ventry.word[1] = tentry.word[1]; - + return ventry; } Index: kernel/arch/ia64/src/asm.S =================================================================== --- kernel/arch/ia64/src/asm.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/src/asm.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -46,5 +46,5 @@ FUNCTION_BEGIN(memcpy_to_uspace) alloc loc0 = ar.pfs, 3, 1, 0, 0 - + adds r14 = 7, in1 mov r2 = ar.lc @@ -53,7 +53,7 @@ cmp.ne p6, p7 = r14, in1 (p7) br.cond.dpnt 3f ;; - + 0: - + cmp.ne p6, p7 = 0, in2 (p7) br.cond.dpnt 2f ;; @@ -62,7 +62,7 @@ (p6) mov r17 = r0 ;; (p6) mov ar.lc = r14 - + 1: - + add r14 = r16, in1 add r15 = r16, in0 @@ -72,13 +72,13 @@ st1 [r15] = r14 br.cloop.sptk.few 1b ;; - + 2: - + mov ar.lc = r2 mov ar.pfs = loc0 br.ret.sptk.many rp - + 3: - + adds r14 = 7, in0 ;; and r14 = -8, r14 ;; @@ -92,7 +92,7 @@ (p6) mov r17 = r0 ;; (p6) mov ar.lc = r14 - + 4: - + shladd r14 = r16, 3, r0 adds r16 = 1, r17 ;; @@ -103,7 +103,7 @@ st8 [r14] = r15 br.cloop.sptk.few 4b - + 5: - + and r15 = 7, in2 shladd r14 = r18, 3, r0 @@ -116,7 +116,7 @@ (p6) br.cond.dpnt 2b ;; mov ar.lc = r15 - + 6: - + add r14 = r16, r17 add r15 = r16, in0 @@ -155,37 +155,37 @@ FUNCTION_BEGIN(switch_to_userspace) alloc loc0 = ar.pfs, 6, 3, 0, 0 - + /* Disable interruption collection and interrupts */ rsm (PSR_IC_MASK | PSR_I_MASK) srlz.d ;; srlz.i ;; - + mov cr.ipsr = in4 mov cr.iip = in0 mov r12 = in1 - + xor r1 = r1, r1 - + /* r2 is defined to hold pcb_ptr - set it to 0 */ xor r2 = r2, r2 - + mov loc1 = cr.ifs movl loc2 = PFM_MASK ;; and loc1 = loc2, loc1 ;; mov cr.ifs = loc1 ;; /* prevent decrementing BSP by rfi */ - + invala - + mov loc1 = ar.rsc ;; and loc1 = ~3, loc1 ;; mov ar.rsc = loc1 ;; /* put RSE into enforced lazy mode */ - + flushrs ;; - + mov ar.bspstore = in2 ;; mov ar.rsc = in5 ;; - + mov r8 = in3 - + rfi ;; FUNCTION_END(switch_to_userspace) Index: kernel/arch/ia64/src/context.S =================================================================== --- kernel/arch/ia64/src/context.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/src/context.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -45,5 +45,5 @@ flushrs mov loc4 = ar.bsp - + /* * Put RSE to enforced lazy mode. @@ -117,5 +117,5 @@ mov loc2 = ar.unat - + /* * Save application registers @@ -177,5 +177,5 @@ mov ar.unat = loc1 - + add r8 = r0, r0, 1 /* context_save returns 1 */ br.ret.sptk.many b0 @@ -239,5 +239,5 @@ ld8 loc5 = [loc14] /* load ar.rnat */ ld8 loc6 = [loc15] /* load ar.lc */ - + .auto @@ -274,5 +274,5 @@ mov ar.unat = loc2 ;; mov ar.lc = loc6 - + /* * Restore general registers including NaT bits @@ -332,7 +332,7 @@ ldf.fill f30 = [loc48] ldf.fill f31 = [loc49] - + mov ar.unat = loc1 - + mov r8 = r0 /* context_restore returns 0 */ br.ret.sptk.many b0 Index: kernel/arch/ia64/src/cpu/cpu.c =================================================================== --- kernel/arch/ia64/src/cpu/cpu.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/src/cpu/cpu.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -54,9 +54,9 @@ const char *family_str; char vendor[2 * sizeof(uint64_t) + 1]; - + memcpy(vendor, &CPU->arch.cpuid0, 8); memcpy(vendor + 8, &CPU->arch.cpuid1, 8); vendor[sizeof(vendor) - 1] = 0; - + switch (m->arch.cpuid3.family) { case FAMILY_ITANIUM: @@ -70,5 +70,5 @@ break; } - + printf("cpu%d: %s (%s), archrev=%d, model=%d, revision=%d\n", CPU->id, family_str, vendor, CPU->arch.cpuid3.archrev, Index: kernel/arch/ia64/src/ddi/ddi.c =================================================================== --- kernel/arch/ia64/src/ddi/ddi.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/src/ddi/ddi.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -59,17 +59,17 @@ if (task->arch.iomap == NULL) return ENOMEM; - + void *store = malloc(bitmap_size(IO_MEMMAP_PAGES), 0); if (store == NULL) return ENOMEM; - + bitmap_initialize(task->arch.iomap, IO_MEMMAP_PAGES, store); bitmap_clear_range(task->arch.iomap, 0, IO_MEMMAP_PAGES); } - + uintptr_t iopage = ioaddr / PORTS_PER_PAGE; size = ALIGN_UP(size + ioaddr - 4 * iopage, PORTS_PER_PAGE); bitmap_set_range(task->arch.iomap, iopage, size / 4); - + return EOK; } @@ -93,5 +93,5 @@ size = ALIGN_UP(size + ioaddr - 4 * iopage, PORTS_PER_PAGE); bitmap_clear_range(task->arch.iomap, iopage, size / 4); - + return EOK; } Index: kernel/arch/ia64/src/drivers/it.c =================================================================== --- kernel/arch/ia64/src/drivers/it.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/src/drivers/it.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -68,5 +68,5 @@ it_irq.handler = it_interrupt; irq_register(&it_irq); - + uint64_t base_freq; base_freq = ((bootinfo->freq_scale) & FREQ_NUMERATOR_MASK) >> @@ -75,22 +75,22 @@ base_freq /= ((bootinfo->freq_scale) & FREQ_DENOMINATOR_MASK) >> FREQ_DENOMINATOR_SHIFT; - + it_delta = base_freq / HZ; } - + /* Initialize Interval Timer external interrupt vector */ cr_itv_t itv; - + itv.value = itv_read(); itv.vector = INTERRUPT_TIMER; itv.m = 0; itv_write(itv.value); - + /* Set Interval Timer Counter to zero */ itc_write(0); - + /* Generate first Interval Timer interrupt in IT_DELTA ticks */ itm_write(IT_DELTA); - + /* Propagate changes */ srlz_d(); @@ -113,11 +113,11 @@ { eoi_write(EOI); - + int64_t itm = itm_read(); - + while (true) { int64_t itc = itc_read(); itc += IT_SERVICE_CLOCKS; - + itm += IT_DELTA; if (itm - itc < 0) @@ -126,8 +126,8 @@ break; } - + itm_write(itm); srlz_d(); /* Propagate changes */ - + /* * We are holding a lock which prevents preemption. Index: kernel/arch/ia64/src/drivers/ski.c =================================================================== --- kernel/arch/ia64/src/drivers/ski.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/src/drivers/ski.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -49,8 +49,8 @@ /** Interval between polling in microseconds */ POLL_INTERVAL = 10000, /* 0.01 s */ - + /** Max. number of characters to pull out at a time */ POLL_LIMIT = 30, - + SKI_INIT_CONSOLE = 20, SKI_GETCHAR = 21, @@ -82,15 +82,15 @@ { uint64_t ch; - + asm volatile ( "mov r15 = %1\n" "break 0x80000;;\n" /* modifies r8 */ "mov %0 = r8;;\n" - + : "=r" (ch) : "i" (SKI_GETCHAR) : "r15", "r8" ); - + return (wchar_t) ch; } @@ -103,11 +103,11 @@ { int count = POLL_LIMIT; - + while (count > 0) { wchar_t ch = ski_getchar(); - + if (ch == '\0') break; - + indev_push_character(instance->srlnin, ch); --count; @@ -119,5 +119,5 @@ { ski_instance_t *instance = (ski_instance_t *) arg; - + while (true) { // TODO FIXME: @@ -126,5 +126,5 @@ if (console_override) poll_keyboard(instance); - + thread_usleep(POLL_INTERVAL); } @@ -141,5 +141,5 @@ if (instance) return; - + asm volatile ( "mov r15 = %0\n" @@ -149,11 +149,11 @@ : "r15", "r8" ); - + instance = malloc(sizeof(ski_instance_t), FRAME_ATOMIC); - + if (instance) { instance->thread = thread_create(kskipoll, instance, TASK, THREAD_FLAG_UNCOUNTED, "kskipoll"); - + if (!instance->thread) { free(instance); @@ -161,5 +161,5 @@ return; } - + instance->srlnin = NULL; } @@ -196,5 +196,5 @@ if (ch == '\n') ski_do_putchar('\r'); - + ski_do_putchar(ch); } else @@ -208,12 +208,12 @@ if (!instance) return NULL; - + outdev_t *skidev = malloc(sizeof(outdev_t), FRAME_ATOMIC); if (!skidev) return NULL; - + outdev_initialize("skidev", skidev, &skidev_ops); skidev->data = instance; - + if (!fb_exported) { /* @@ -224,8 +224,8 @@ sysinfo_set_item_val("fb", NULL, true); sysinfo_set_item_val("fb.kind", NULL, 6); - + fb_exported = true; } - + return skidev; } @@ -241,8 +241,8 @@ assert(instance); assert(srlnin); - + instance->srlnin = srlnin; thread_ready(instance->thread); - + sysinfo_set_item_val("kbd", NULL, true); sysinfo_set_item_val("kbd.type", NULL, KBD_SKI); Index: kernel/arch/ia64/src/fpu_context.c =================================================================== --- kernel/arch/ia64/src/fpu_context.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/src/fpu_context.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -103,5 +103,5 @@ [f61] "=m" (fctx->fr[29]) ); - + asm volatile ( "stf.spill %[f62] = f62\n" @@ -314,5 +314,5 @@ [f61] "m" (fctx->fr[29]) ); - + asm volatile ( "ldf.fill f62 = %[f62]\n" Index: kernel/arch/ia64/src/ia64.c =================================================================== --- kernel/arch/ia64/src/ia64.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/src/ia64.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -108,7 +108,7 @@ PAGE_WRITE | PAGE_NOT_CACHEABLE); int i; - + int myid, myeid; - + myid = ia64_get_cpu_id(); myeid = ia64_get_cpu_eid(); @@ -167,10 +167,10 @@ } } - + outdev_t *skidev = skiout_init(); if (skidev) stdout_wire(skidev); #endif - + #ifdef CONFIG_EGA outdev_t *egadev = ega_init(EGA_BASE, EGA_VIDEORAM); @@ -178,5 +178,5 @@ stdout_wire(egadev); #endif - + #ifdef CONFIG_NS16550 ns16550_instance_t *ns16550_instance @@ -191,5 +191,5 @@ } } - + sysinfo_set_item_val("kbd", NULL, true); sysinfo_set_item_val("kbd.inr", NULL, NS16550_IRQ); @@ -198,5 +198,5 @@ (uintptr_t) NS16550_BASE); #endif - + #ifdef CONFIG_I8042 i8042_instance_t *i8042_instance = i8042_init((i8042_t *) I8042_BASE, @@ -211,5 +211,5 @@ } #endif - + sysinfo_set_item_val("ia64_iospace", NULL, true); sysinfo_set_item_val("ia64_iospace.address", NULL, true); @@ -251,5 +251,5 @@ kernel_uarg->uspace_stack_size / 2, (uintptr_t) kernel_uarg->uspace_uarg, psr.value, rsc.value); - + while (1); } @@ -274,5 +274,5 @@ fptr->fnc = (sysarg_t) addr; fptr->gp = ((sysarg_t *) caller)[1]; - + return (void *) fptr; } Index: kernel/arch/ia64/src/interrupt.c =================================================================== --- kernel/arch/ia64/src/interrupt.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/src/interrupt.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -124,5 +124,5 @@ { assert(n <= VECTOR_MAX); - + if (n >= VECTORS_16_BUNDLE_START) return vector_names_16_bundle[n - VECTORS_16_BUNDLE_START]; @@ -141,5 +141,5 @@ printf("cr.isr=%#0" PRIx64 "\tcr.ipsr=%#0" PRIx64 "\n", istate->cr_isr.value, istate->cr_ipsr.value); - + printf("cr.iip=%#0" PRIxPTR ", #%u\t(%s)\n", istate->cr_iip, istate->cr_isr.ei, @@ -154,5 +154,5 @@ { const char *desc; - + switch (istate->cr_isr.ge_code) { case GE_ILLEGALOP: @@ -178,5 +178,5 @@ break; } - + fault_if_from_uspace(istate, "General Exception (%s).", desc); panic_badtrap(istate, n, "General Exception (%s).", desc); @@ -209,5 +209,5 @@ istate->cr_ipsr.ri++; } - + interrupts_enable(); ret = syscall_handler(istate->in0, istate->in1, istate->in2, @@ -236,10 +236,10 @@ { cr_ivr_t ivr; - + ivr.value = ivr_read(); srlz_d(); - + irq_t *irq; - + switch (ivr.vector) { case INTERRUPT_SPURIOUS: @@ -248,5 +248,5 @@ #endif break; - + #ifdef CONFIG_SMP case VECTOR_TLB_SHOOTDOWN_IPI: @@ -255,5 +255,5 @@ break; #endif - + case INTERRUPT_TIMER: irq = irq_dispatch_and_lock(ivr.vector); Index: kernel/arch/ia64/src/ivt.S =================================================================== --- kernel/arch/ia64/src/ivt.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/src/ivt.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -57,8 +57,8 @@ mov r19 = cr.ipsr mov r20 = cr.isr ;; - + /* 2. Move IIP to IIPA. */ mov cr.iipa = r18 - + /* 3. Sign extend IIM[20:0], shift left by 4 and add to IIP. */ shl r17 = r17, 43 ;; /* shift bit 20 to bit 63 */ @@ -66,9 +66,9 @@ add r18 = r18, r17 ;; mov cr.iip = r18 - + /* 4. Set IPSR.ri to 0. */ dep r19 = 0, r19, PSR_RI_SHIFT, PSR_RI_LEN ;; mov cr.ipsr = r19 - + /* 5. Check whether IPSR.tb or IPSR.ss is set. */ @@ -76,5 +76,5 @@ * Implement this when Taken Branch and Single Step traps can occur. */ - + /* 6. Restore predicates and return from interruption. */ mov pr = r16 ;; @@ -104,9 +104,9 @@ SYMBOL(heavyweight_handler) /* 1. copy interrupt registers into bank 0 */ - + /* * Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0. */ - + /* Set up FPU as in interrupted context. */ mov r24 = psr @@ -126,8 +126,8 @@ mov r27 = cr.isr mov r28 = cr.ifa - + /* 2. preserve predicate register into bank 0 */ mov r29 = pr ;; - + /* 3. switch to kernel memory stack */ mov r30 = cr.ipsr @@ -149,5 +149,5 @@ */ (p3) cmp.eq p3, p4 = VRN_KERNEL, r31 ;; - + /* * Now, p4 is true iff the stack needs to be switched to kernel stack. @@ -155,5 +155,5 @@ mov r30 = r12 (p4) mov r12 = R_KSTACK ;; - + add r12 = -STACK_FRAME_SIZE, r12 ;; add r31 = STACK_SCRATCH_AREA_SIZE + ISTATE_OFFSET_IN6, r12 @@ -166,5 +166,5 @@ */ cmp.eq p6, p5 = EXC_BREAK_INSTRUCTION, R_VECTOR ;; - + /* * From now on, if this is break_instruction handler, p6 is true and p5 @@ -181,7 +181,7 @@ (p6) st8 [r31] = r32, -STACK_ITEM_SIZE ;; /* save in0 */ (p5) add r31 = -(7 * STACK_ITEM_SIZE), r31 ;; - + st8 [r31] = r30, -STACK_ITEM_SIZE ;; /* save old stack pointer */ - + st8 [r31] = r29, -STACK_ITEM_SIZE ;; /* save predicate registers */ @@ -197,16 +197,16 @@ cover mov r26 = cr.ifs - + st8 [r31] = r24, -STACK_ITEM_SIZE ;; /* save ar.rsc */ st8 [r31] = r25, -STACK_ITEM_SIZE ;; /* save ar.pfs */ st8 [r31] = r26, -STACK_ITEM_SIZE /* save ar.ifs */ - + and r24 = ~(RSC_PL_MASK), r24 ;; and r30 = ~(RSC_MODE_MASK), r24 ;; mov ar.rsc = r30 ;; /* update RSE state */ - + mov r27 = ar.rnat mov r28 = ar.bspstore ;; - + /* * Inspect BSPSTORE to figure out whether it is necessary to switch to @@ -215,5 +215,5 @@ (p1) shr.u r30 = r28, VRN_SHIFT ;; (p1) cmp.eq p1, p2 = VRN_KERNEL, r30 ;; - + /* * If BSPSTORE needs to be switched, p1 is false and p2 is true. @@ -222,14 +222,14 @@ (p2) mov r30 = R_KSTACK_BSP ;; (p2) mov ar.bspstore = r30 ;; - + mov r29 = ar.bsp - + st8 [r31] = r27, -STACK_ITEM_SIZE ;; /* save ar.rnat */ st8 [r31] = r30, -STACK_ITEM_SIZE ;; /* save new value written to ar.bspstore */ st8 [r31] = r28, -STACK_ITEM_SIZE ;; /* save ar.bspstore */ st8 [r31] = r29, -STACK_ITEM_SIZE /* save ar.bsp */ - + mov ar.rsc = r24 /* restore RSE's setting + kernel privileges */ - + /* steps 6 - 15 are done by heavyweight_handler_inner() */ mov R_RET = b0 /* save b0 belonging to interrupted context */ @@ -292,5 +292,5 @@ ld8 r29 = [r31], +STACK_ITEM_SIZE ;; /* load predicate registers */ mov pr = r29 - + /* 19. return from interruption */ ld8 r12 = [r31] /* load stack pointer */ @@ -303,10 +303,10 @@ */ alloc loc0 = ar.pfs, 0, 48, 2, 0 ;; - + /* bank 0 is going to be shadowed, copy essential data from there */ mov loc1 = R_RET /* b0 belonging to interrupted context */ mov loc2 = R_HANDLER mov out0 = R_VECTOR - + add out1 = STACK_SCRATCH_AREA_SIZE, r12 @@ -315,5 +315,5 @@ bsw.1 ;; srlz.d - + /* 7. preserve branch and application registers */ mov loc3 = ar.unat @@ -323,5 +323,5 @@ mov loc7 = ar.csd mov loc8 = ar.ssd - + mov loc9 = b0 mov loc10 = b1 @@ -332,5 +332,5 @@ mov loc15 = b6 mov loc16 = b7 - + /* 8. preserve general and floating-point registers */ mov loc17 = r1 @@ -374,5 +374,5 @@ add r30 = ISTATE_OFFSET_F6 + STACK_SCRATCH_AREA_SIZE, r12 add r31 = ISTATE_OFFSET_F7 + STACK_SCRATCH_AREA_SIZE, r12 ;; - + stf.spill [r26] = f2, 8 * FLOAT_ITEM_SIZE stf.spill [r27] = f3, 8 * FLOAT_ITEM_SIZE @@ -410,5 +410,5 @@ mov loc47 = ar.fpsr /* preserve floating point status register */ - + /* 9. skipped (will not enable interrupts) */ /* @@ -420,5 +420,5 @@ /* 10. call handler */ movl r1 = __gp - + mov b1 = loc2 br.call.sptk.many b0 = b1 @@ -426,5 +426,5 @@ /* 11. return from handler */ 0: - + /* 12. skipped (will not disable interrupts) */ /* @@ -477,5 +477,5 @@ ldf.fill f30 = [r30] ldf.fill f31 = [r31] ;; - + mov r1 = loc17 mov r2 = loc18 @@ -511,5 +511,5 @@ mov ar.fpsr = loc47 /* restore floating point status register */ - + /* 14. restore branch and application registers */ mov ar.unat = loc3 @@ -519,5 +519,5 @@ mov ar.csd = loc7 mov ar.ssd = loc8 - + mov b0 = loc9 mov b1 = loc10 @@ -528,5 +528,5 @@ mov b6 = loc15 mov b7 = loc16 - + /* 15. disable PSR.ic and switch to bank 0 */ rsm PSR_IC_MASK @@ -578,5 +578,5 @@ HEAVYWEIGHT_HANDLER 0x5e HEAVYWEIGHT_HANDLER 0x5f - + HEAVYWEIGHT_HANDLER 0x60 HEAVYWEIGHT_HANDLER 0x61 Index: kernel/arch/ia64/src/mm/as.c =================================================================== --- kernel/arch/ia64/src/mm/as.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/src/mm/as.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -58,7 +58,7 @@ region_register_t rr; int i; - + assert(as->asid != ASID_INVALID); - + /* * Load respective ASID (7 consecutive RIDs) to @@ -68,5 +68,5 @@ if (i == VRN_KERNEL) continue; - + rr.word = rr_read(i); rr.map.ve = false; /* disable VHPT walker */ Index: kernel/arch/ia64/src/mm/frame.c =================================================================== --- kernel/arch/ia64/src/mm/frame.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/src/mm/frame.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -92,7 +92,7 @@ if (config.cpu_active > 1) return; - + frame_common_arch_init(true); - + /* * Blacklist ROM regions. @@ -112,5 +112,5 @@ if (config.cpu_active > 1) return; - + frame_common_arch_init(false); } Index: kernel/arch/ia64/src/mm/page.c =================================================================== --- kernel/arch/ia64/src/mm/page.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/src/mm/page.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -124,5 +124,5 @@ vrn = page >> VRN_SHIFT; rid = ASID2RID(asid, vrn); - + rr_save.word = rr_read(vrn); if (rr_save.map.rid == rid) { @@ -133,5 +133,5 @@ return v; } - + /* * The RID must be written to some region register. @@ -171,5 +171,5 @@ vrn = page >> VRN_SHIFT; rid = ASID2RID(asid, vrn); - + rr_save.word = rr_read(vrn); if (rr_save.map.rid == rid) { @@ -179,5 +179,5 @@ return ttag(page) == v->present.tag.tag_word; } - + /* * The RID must be written to some region register. @@ -218,5 +218,5 @@ vrn = page >> VRN_SHIFT; rid = ASID2RID(asid, vrn); - + /* * Compute ttag. @@ -231,5 +231,5 @@ srlz_i(); srlz_d(); - + /* * Clear the entry. @@ -239,5 +239,5 @@ v->word[2] = 0; v->word[3] = 0; - + v->present.p = true; v->present.ma = (flags & PAGE_CACHEABLE) ? Index: kernel/arch/ia64/src/mm/tlb.c =================================================================== --- kernel/arch/ia64/src/mm/tlb.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/src/mm/tlb.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -61,7 +61,7 @@ uintptr_t adr; uint32_t count1, count2, stride1, stride2; - + unsigned int i, j; - + adr = PAL_PTCE_INFO_BASE(); count1 = PAL_PTCE_INFO_COUNT1(); @@ -69,7 +69,7 @@ stride1 = PAL_PTCE_INFO_STRIDE1(); stride2 = PAL_PTCE_INFO_STRIDE2(); - + ipl = interrupts_disable(); - + for (i = 0; i < count1; i++) { for (j = 0; j < count2; j++) { @@ -82,10 +82,10 @@ adr += stride1; } - + interrupts_restore(ipl); - + srlz_d(); srlz_i(); - + #ifdef CONFIG_VHPT vhpt_invalidate_all(); @@ -110,8 +110,8 @@ int b = 0; int c = cnt; - + uintptr_t va; va = page; - + rr.word = rr_read(VA2VRN(page)); if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(page))))) { @@ -121,5 +121,5 @@ */ region_register_t rr0; - + rr0 = rr; rr0.map.rid = ASID2RID(asid, VA2VRN(page)); @@ -128,10 +128,10 @@ srlz_i(); } - + while (c >>= 1) b++; b >>= 1; uint64_t ps; - + switch (b) { case 0: /* cnt 1 - 3 */ @@ -172,5 +172,5 @@ break; } - + for (; va < (page + cnt * PAGE_SIZE); va += (1UL << ps)) asm volatile ( @@ -179,8 +179,8 @@ [ps] "r" (ps << 2) ); - + srlz_d(); srlz_i(); - + if (restore_rr) { rr_write(VA2VRN(page), rr.word); @@ -229,5 +229,5 @@ region_register_t rr; bool restore_rr = false; - + rr.word = rr_read(VA2VRN(va)); if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) { @@ -237,5 +237,5 @@ */ region_register_t rr0; - + rr0 = rr; rr0.map.rid = ASID2RID(asid, VA2VRN(va)); @@ -244,5 +244,5 @@ srlz_i(); } - + asm volatile ( "mov r8 = psr ;;\n" @@ -264,5 +264,5 @@ : "p6", "p7", "r8" ); - + if (restore_rr) { rr_write(VA2VRN(va), rr.word); @@ -316,5 +316,5 @@ region_register_t rr; bool restore_rr = false; - + rr.word = rr_read(VA2VRN(va)); if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) { @@ -324,5 +324,5 @@ */ region_register_t rr0; - + rr0 = rr; rr0.map.rid = ASID2RID(asid, VA2VRN(va)); @@ -331,5 +331,5 @@ srlz_i(); } - + asm volatile ( "mov r8 = psr ;;\n" @@ -352,5 +352,5 @@ : "p6", "p7", "r8" ); - + if (restore_rr) { rr_write(VA2VRN(va), rr.word); @@ -373,8 +373,8 @@ { tlb_entry_t entry; - + entry.word[0] = 0; entry.word[1] = 0; - + entry.p = true; /* present */ entry.ma = MA_WRITEBACK; @@ -385,5 +385,5 @@ entry.ppn = frame >> PPN_SHIFT; entry.ps = PAGE_WIDTH; - + if (dtr) dtr_mapping_insert(page, ASID_KERNEL, entry, tr); @@ -418,8 +418,8 @@ { tlb_entry_t entry; - + entry.word[0] = 0; entry.word[1] = 0; - + entry.p = t->p; entry.ma = t->c ? MA_WRITEBACK : MA_UNCACHEABLE; @@ -430,7 +430,7 @@ entry.ppn = t->frame >> PPN_SHIFT; entry.ps = PAGE_WIDTH; - + dtc_mapping_insert(t->page, t->as->asid, entry); - + #ifdef CONFIG_VHPT vhpt_mapping_insert(t->page, t->as->asid, entry); @@ -446,10 +446,10 @@ { tlb_entry_t entry; - + entry.word[0] = 0; entry.word[1] = 0; - + assert(t->x); - + entry.p = t->p; entry.ma = t->c ? MA_WRITEBACK : MA_UNCACHEABLE; @@ -459,7 +459,7 @@ entry.ppn = t->frame >> PPN_SHIFT; entry.ps = PAGE_WIDTH; - + itc_mapping_insert(t->page, t->as->asid, entry); - + #ifdef CONFIG_VHPT vhpt_mapping_insert(t->page, t->as->asid, entry); @@ -486,7 +486,7 @@ uintptr_t va; pte_t t; - + va = istate->cr_ifa; /* faulting address */ - + assert(!is_kernel_fault(va)); @@ -532,18 +532,18 @@ uint64_t io_page = (va & ((1 << LEGACYIO_PAGE_WIDTH) - 1)) >> LEGACYIO_SINGLE_PAGE_WIDTH; - + if (is_io_page_accessible(io_page)) { uint64_t page, frame; - + page = LEGACYIO_USER_BASE + (1 << LEGACYIO_SINGLE_PAGE_WIDTH) * io_page; frame = LEGACYIO_PHYS_BASE + (1 << LEGACYIO_SINGLE_PAGE_WIDTH) * io_page; - + tlb_entry_t entry; - + entry.word[0] = 0; entry.word[1] = 0; - + entry.p = true; /* present */ entry.ma = MA_UNCACHEABLE; @@ -554,5 +554,5 @@ entry.ppn = frame >> PPN_SHIFT; entry.ps = LEGACYIO_SINGLE_PAGE_WIDTH; - + dtc_mapping_insert(page, TASK->as->asid, entry); return 1; @@ -563,5 +563,5 @@ } } - + return 0; } @@ -586,8 +586,8 @@ return; } - + uintptr_t va = istate->cr_ifa; /* faulting address */ as_t *as = AS; - + if (is_kernel_fault(va)) { if (va < end_of_identity) { @@ -601,6 +601,6 @@ } } - - + + pte_t t; bool found = page_mapping_find(as, va, true, &t); @@ -616,5 +616,5 @@ if (try_memmap_io_insertion(va, istate)) return; - + /* * Forward the page fault to the address space page fault @@ -649,7 +649,7 @@ pte_t t; as_t *as = AS; - + va = istate->cr_ifa; /* faulting address */ - + if (is_kernel_fault(va)) as = AS_KERNEL; @@ -683,9 +683,9 @@ uintptr_t va; pte_t t; - + va = istate->cr_ifa; /* faulting address */ assert(!is_kernel_fault(va)); - + bool found = page_mapping_find(AS, va, true, &t); @@ -717,7 +717,7 @@ pte_t t; as_t *as = AS; - + va = istate->cr_ifa; /* faulting address */ - + if (is_kernel_fault(va)) as = AS_KERNEL; @@ -755,9 +755,9 @@ uintptr_t va; pte_t t; - + va = istate->cr_ifa; /* faulting address */ assert(!is_kernel_fault(va)); - + /* * Assume a write to a read-only page. @@ -782,7 +782,7 @@ uintptr_t va; pte_t t; - + va = istate->cr_ifa; /* faulting address */ - + assert(!is_kernel_fault(va)); @@ -790,5 +790,5 @@ assert(found); - + if (t.p) { /* Index: kernel/arch/ia64/src/mm/vhpt.c =================================================================== --- kernel/arch/ia64/src/mm/vhpt.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/src/mm/vhpt.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -46,5 +46,5 @@ if (!vhpt_frame) panic("Kernel configured with VHPT but no memory for table."); - + vhpt_base = (vhpt_entry_t *) PA2KA(vhpt_frame); vhpt_invalidate_all(); @@ -59,10 +59,10 @@ rid_t rid; uint64_t tag; - + vhpt_entry_t *ventry; - + vrn = va >> VRN_SHIFT; rid = ASID2RID(asid, vrn); - + rr_save.word = rr_read(vrn); rr.word = rr_save.word; @@ -70,5 +70,5 @@ rr_write(vrn, rr.word); srlz_i(); - + ventry = (vhpt_entry_t *) thash(va); tag = ttag(va); @@ -76,5 +76,5 @@ srlz_i(); srlz_d(); - + ventry->word[0] = entry.word[0]; ventry->word[1] = entry.word[1]; Index: kernel/arch/ia64/src/proc/scheduler.c =================================================================== --- kernel/arch/ia64/src/proc/scheduler.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/src/proc/scheduler.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -54,5 +54,5 @@ { uintptr_t base; - + base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); @@ -63,8 +63,8 @@ * Use DTR[TR_KSTACK1] and DTR[TR_KSTACK2] to map it. */ - + /* purge DTR[TR_STACK1] and DTR[TR_STACK2] */ dtr_purge((uintptr_t) THREAD->kstack, PAGE_WIDTH+1); - + /* insert DTR[TR_STACK1] and DTR[TR_STACK2] */ dtlb_kernel_mapping_insert((uintptr_t) THREAD->kstack, @@ -74,5 +74,5 @@ DTR_KSTACK2); } - + /* * Record address of kernel backing store to bank 0 r22. Index: kernel/arch/ia64/src/start.S =================================================================== --- kernel/arch/ia64/src/start.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ia64/src/start.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -54,46 +54,46 @@ SYMBOL(kernel_image_start) .auto - + mov psr.l = r0 srlz.i srlz.d - + # Fill TR.i and TR.d using Region Register #VRN_KERNEL - + movl r8 = (VRN_KERNEL << VRN_SHIFT) mov r9 = rr[r8] - + movl r10 = (RR_MASK) and r9 = r10, r9 movl r10 = (((RID_KERNEL7) << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT)) or r9 = r10, r9 - + mov rr[r8] = r9 - + movl r8 = (VRN_KERNEL << VRN_SHIFT) mov cr.ifa = r8 - + mov r11 = cr.itir movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT) or r10 = r10, r11 mov cr.itir = r10 - + movl r10 = (KERNEL_TRANSLATION_I) itr.i itr[r0] = r10 movl r10 = (KERNEL_TRANSLATION_D) itr.d dtr[r0] = r10 - + # Initialize DCR - + movl r10 = (DCR_DP_MASK | DCR_DK_MASK | DCR_DX_MASK | DCR_DR_MASK | DCR_DA_MASK | DCR_DD_MASK | DCR_LC_MASK) mov r9 = cr.dcr or r10 = r10, r9 mov cr.dcr = r10 - + # Initialize PSR - + movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK) /* Enable paging */ mov r9 = psr - + or r10 = r10, r9 mov cr.ipsr = r10 @@ -103,7 +103,7 @@ srlz.d srlz.i - + .explicit - + /* * Return From Interrupt is the only way to @@ -113,5 +113,5 @@ paging_start: - + /* * Now we are paging. @@ -126,8 +126,8 @@ srlz.d ;; - + # Switch to register bank 1 bsw.1 - + # Initialize register stack mov ar.rsc = r0 @@ -135,5 +135,5 @@ mov ar.bspstore = r8 loadrs - + # # Initialize memory stack to some sane value and allocate a scratch area @@ -142,8 +142,8 @@ movl sp = stack0 ;; add sp = -16, sp - + # Initialize gp (Global Pointer) register movl gp = __gp - + # # Initialize bootinfo on BSP. @@ -153,9 +153,9 @@ addl r21 = @gprel(bootinfo), gp ;; st8 [r21] = r20 - + ssm (1 << 19) ;; /* Disable f32 - f127 */ srlz.i srlz.d ;; - + br.call.sptk.many b0 = ia64_pre_main 0: Index: kernel/arch/mips32/include/arch/asm.h =================================================================== --- kernel/arch/mips32/include/arch/asm.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/mips32/include/arch/asm.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -55,5 +55,5 @@ { uintptr_t base; - + asm volatile ( "and %[base], $29, %[mask]\n" @@ -61,5 +61,5 @@ : [mask] "r" (~(STACK_SIZE - 1)) ); - + return base; } Index: kernel/arch/mips32/include/arch/atomic.h =================================================================== --- kernel/arch/mips32/include/arch/atomic.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/mips32/include/arch/atomic.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -60,5 +60,5 @@ atomic_count_t tmp; atomic_count_t v; - + asm volatile ( "1:\n" @@ -75,5 +75,5 @@ "i" (0) ); - + return v; } @@ -83,5 +83,5 @@ atomic_count_t tmp; atomic_count_t v; - + asm volatile ( "1:\n" @@ -98,5 +98,5 @@ : "i" (1) ); - + return v; } Index: kernel/arch/mips32/include/arch/mm/page.h =================================================================== --- kernel/arch/mips32/include/arch/mm/page.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/mips32/include/arch/mm/page.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -165,5 +165,5 @@ { pte_t *p = &pt[i]; - + return ((p->cacheable << PAGE_CACHEABLE_SHIFT) | ((!p->p) << PAGE_PRESENT_SHIFT) | @@ -178,10 +178,10 @@ { pte_t *p = &pt[i]; - + p->cacheable = (flags & PAGE_CACHEABLE) != 0; p->p = !(flags & PAGE_NOT_PRESENT); p->g = (flags & PAGE_GLOBAL) != 0; p->w = (flags & PAGE_WRITE) != 0; - + /* * Ensure that valid entries have at least one bit set. Index: kernel/arch/mips32/src/asm.S =================================================================== --- kernel/arch/mips32/src/asm.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/mips32/src/asm.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -62,5 +62,5 @@ FUNCTION_BEGIN(memcpy_to_uspace) move $t2, $a0 /* save dst */ - + addiu $v0, $a1, 3 li $v1, -4 /* 0xfffffffffffffffc */ @@ -68,9 +68,9 @@ beq $a1, $v0, 3f move $t0, $a0 - + 0: beq $a2, $zero, 2f move $a3, $zero - + 1: addu $v0, $a1, $a3 @@ -80,9 +80,9 @@ bne $a3, $a2, 1b sb $a0, 0($v1) - + 2: jr $ra move $v0, $t2 - + 3: addiu $v0, $a0, 3 @@ -90,11 +90,11 @@ bne $a0, $v0, 0b srl $t1, $a2, 2 - + beq $t1, $zero, 5f move $a3, $zero - + move $a3, $zero move $a0, $zero - + 4: addu $v0, $a1, $a0 @@ -105,15 +105,15 @@ bne $a3, $t1, 4b addiu $a0, $a0, 4 - + 5: andi $a2, $a2, 0x3 beq $a2, $zero, 2b nop - + sll $v0, $a3, 2 addu $t1, $v0, $t0 move $a3, $zero addu $t0, $v0, $a1 - + 6: addu $v0, $t0, $a3 @@ -123,5 +123,5 @@ bne $a3, $a2, 6b sb $a0, 0($v1) - + jr $ra move $v0, $t2 @@ -188,5 +188,5 @@ fpu_gp_save 30, $a0 fpu_gp_save 31, $a0 - + fpu_ct_save 1, $a0 fpu_ct_save 2, $a0 @@ -259,5 +259,5 @@ fpu_gp_restore 30, $a0 fpu_gp_restore 31, $a0 - + fpu_ct_restore 1, $a0 fpu_ct_restore 2, $a0 Index: kernel/arch/mips32/src/context.S =================================================================== --- kernel/arch/mips32/src/context.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/mips32/src/context.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -47,8 +47,8 @@ sw $s8, CONTEXT_OFFSET_S8($a0) sw $gp, CONTEXT_OFFSET_GP($a0) - + sw $ra, CONTEXT_OFFSET_PC($a0) sw $sp, CONTEXT_OFFSET_SP($a0) - + # context_save returns 1 j $31 @@ -67,8 +67,8 @@ lw $s8, CONTEXT_OFFSET_S8($a0) lw $gp, CONTEXT_OFFSET_GP($a0) - + lw $ra, CONTEXT_OFFSET_PC($a0) lw $sp, CONTEXT_OFFSET_SP($a0) - + # context_restore returns 0 j $31 Index: kernel/arch/mips32/src/debug/stacktrace.c =================================================================== --- kernel/arch/mips32/src/debug/stacktrace.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/mips32/src/debug/stacktrace.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -157,5 +157,5 @@ * We have a candidate for frame pointer. */ - + /* Seek to the end of this function. */ for (cur = inst + 1; !IS_JR_RA(*cur); cur++) @@ -170,5 +170,5 @@ continue; } - + if (IS_JR_RA(*inst)) { if (!ctx->istate) @@ -189,5 +189,5 @@ } while ((!IS_ADDIU_SP_SP_IMM(*inst) && !IS_ADDI_SP_SP_IMM(*inst)) || (IMM_GET(*inst) >= 0)); - + /* * We are at the instruction which allocates the space for the current @@ -210,5 +210,5 @@ if (base == SP || (has_fp && base == fp)) { uint32_t *addr = (void *) (ctx->fp + offset); - + if (offset % 4 != 0) return false; Index: kernel/arch/mips32/src/debugger.c =================================================================== --- kernel/arch/mips32/src/debugger.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/mips32/src/debugger.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -138,10 +138,10 @@ { unsigned int i; - + for (i = 0; jmpinstr[i].andmask; i++) { if ((instr & jmpinstr[i].andmask) == jmpinstr[i].value) return true; } - + return false; } @@ -158,7 +158,7 @@ return 1; } - + irq_spinlock_lock(&bkpoint_lock, true); - + /* Check, that the breakpoints do not conflict */ unsigned int i; @@ -176,9 +176,9 @@ return 0; } - - } - + + } + bpinfo_t *cur = NULL; - + for (i = 0; i < BKPOINTS_MAX; i++) { if (!breakpoints[i].address) { @@ -187,5 +187,5 @@ } } - + if (!cur) { printf("Too many breakpoints.\n"); @@ -193,7 +193,7 @@ return 0; } - + printf("Adding breakpoint on address %p\n", (void *) argv->intval); - + cur->address = (uintptr_t) argv->intval; cur->instruction = ((sysarg_t *) cur->address)[0]; @@ -205,16 +205,16 @@ cur->bkfunc = (void (*)(void *, istate_t *)) argv[1].intval; } - + if (is_jump(cur->instruction)) cur->flags |= BKPOINT_ONESHOT; - + cur->counter = 0; - + /* Set breakpoint */ *((sysarg_t *) cur->address) = 0x0d; smc_coherence(cur->address); - + irq_spinlock_unlock(&bkpoint_lock, true); - + return 1; } @@ -229,7 +229,7 @@ return 0; } - + irq_spinlock_lock(&bkpoint_lock, true); - + bpinfo_t *cur = &breakpoints[argv->intval]; if (!cur->address) { @@ -238,5 +238,5 @@ return 0; } - + if ((cur->flags & BKPOINT_INPROG) && (cur->flags & BKPOINT_ONESHOT)) { printf("Cannot remove one-shot breakpoint in-progress\n"); @@ -244,12 +244,12 @@ return 0; } - + ((uint32_t *) cur->address)[0] = cur->instruction; smc_coherence(((uint32_t *) cur->address)[0]); ((uint32_t *) cur->address)[1] = cur->nextinstruction; smc_coherence(((uint32_t *) cur->address)[1]); - + cur->address = (uintptr_t) NULL; - + irq_spinlock_unlock(&bkpoint_lock, true); return 1; @@ -262,12 +262,12 @@ { unsigned int i; - + printf("[nr] [count] [address ] [inprog] [oneshot] [funccall] [in symbol\n"); - + for (i = 0; i < BKPOINTS_MAX; i++) { if (breakpoints[i].address) { const char *symbol = symtab_fmt_name_lookup( breakpoints[i].address); - + printf("%-4u %7zu %p %-8s %-9s %-10s %s\n", i, breakpoints[i].counter, (void *) breakpoints[i].address, @@ -278,5 +278,5 @@ } } - + return 1; } @@ -290,8 +290,8 @@ { unsigned int i; - + for (i = 0; i < BKPOINTS_MAX; i++) breakpoints[i].address = (uintptr_t) NULL; - + #ifdef CONFIG_KCONSOLE cmd_initialize(&bkpts_info); @@ -299,15 +299,15 @@ log(LF_OTHER, LVL_WARN, "Cannot register command %s", bkpts_info.name); - + cmd_initialize(&delbkpt_info); if (!cmd_register(&delbkpt_info)) log(LF_OTHER, LVL_WARN, "Cannot register command %s", delbkpt_info.name); - + cmd_initialize(&addbkpt_info); if (!cmd_register(&addbkpt_info)) log(LF_OTHER, LVL_WARN, "Cannot register command %s", addbkpt_info.name); - + cmd_initialize(&addbkpte_info); if (!cmd_register(&addbkpte_info)) @@ -331,11 +331,11 @@ if (cp0_cause_read() & 0x80000000) panic("Breakpoint in branch delay slot not supported."); - + irq_spinlock_lock(&bkpoint_lock, false); - + bpinfo_t *cur = NULL; uintptr_t fireaddr = istate->epc; unsigned int i; - + for (i = 0; i < BKPOINTS_MAX; i++) { /* Normal breakpoint */ @@ -345,5 +345,5 @@ break; } - + /* Reinst only breakpoint */ if ((breakpoints[i].flags & BKPOINT_REINST) && @@ -353,5 +353,5 @@ } } - + if (cur) { if (cur->flags & BKPOINT_REINST) { @@ -359,17 +359,17 @@ ((uint32_t *) cur->address)[0] = 0x0d; smc_coherence(((uint32_t *)cur->address)[0]); - + /* Return back the second */ ((uint32_t *) cur->address)[1] = cur->nextinstruction; smc_coherence(((uint32_t *) cur->address)[1]); - + cur->flags &= ~BKPOINT_REINST; irq_spinlock_unlock(&bkpoint_lock, false); return; } - + if (cur->flags & BKPOINT_INPROG) printf("Warning: breakpoint recursion\n"); - + if (!(cur->flags & BKPOINT_FUNCCALL)) { printf("***Breakpoint %u: %p in %s.\n", i, @@ -377,5 +377,5 @@ symtab_fmt_name_lookup(fireaddr)); } - + /* Return first instruction back */ ((uint32_t *)cur->address)[0] = cur->instruction; @@ -392,12 +392,12 @@ (void *) fireaddr, symtab_fmt_name_lookup(fireaddr)); - + /* Move on to next instruction */ istate->epc += 4; } - + if (cur) cur->counter++; - + if (cur && (cur->flags & BKPOINT_FUNCCALL)) { /* Allow zero bkfunc, just for counting */ @@ -414,12 +414,12 @@ atomic_set(&haltstate, 1); irq_spinlock_unlock(&bkpoint_lock, false); - + kconsole("debug", "Debug console ready.\n", false); - + irq_spinlock_lock(&bkpoint_lock, false); atomic_set(&haltstate, 0); #endif } - + if ((cur) && (cur->address == fireaddr) && ((cur->flags & BKPOINT_INPROG))) { @@ -427,9 +427,9 @@ if ((cur->flags & BKPOINT_ONESHOT)) cur->address = (uintptr_t) NULL; - + /* Remove in-progress flag */ cur->flags &= ~BKPOINT_INPROG; } - + irq_spinlock_unlock(&bkpoint_lock, false); } Index: kernel/arch/mips32/src/exception.c =================================================================== --- kernel/arch/mips32/src/exception.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/mips32/src/exception.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -77,33 +77,33 @@ "lo =%#010" PRIx32 "\thi =%#010" PRIx32 "\n", istate->epc, istate->status, istate->lo, istate->hi); - + log_printf("a0 =%#010" PRIx32 "\ta1 =%#010" PRIx32 "\t" "a2 =%#010" PRIx32 "\ta3 =%#010" PRIx32 "\n", istate->a0, istate->a1, istate->a2, istate->a3); - + log_printf("t0 =%#010" PRIx32 "\tt1 =%#010" PRIx32 "\t" "t2 =%#010" PRIx32 "\tt3 =%#010" PRIx32 "\n", istate->t0, istate->t1, istate->t2, istate->t3); - + log_printf("t4 =%#010" PRIx32 "\tt5 =%#010" PRIx32 "\t" "t6 =%#010" PRIx32 "\tt7 =%#010" PRIx32 "\n", istate->t4, istate->t5, istate->t6, istate->t7); - + log_printf("t8 =%#010" PRIx32 "\tt9 =%#010" PRIx32 "\t" "v0 =%#010" PRIx32 "\tv1 =%#010" PRIx32 "\n", istate->t8, istate->t9, istate->v0, istate->v1); - + log_printf("s0 =%#010" PRIx32 "\ts1 =%#010" PRIx32 "\t" "s2 =%#010" PRIx32 "\ts3 =%#010" PRIx32 "\n", istate->s0, istate->s1, istate->s2, istate->s3); - + log_printf("s4 =%#010" PRIx32 "\ts5 =%#010" PRIx32 "\t" "s6 =%#010" PRIx32 "\ts7 =%#010" PRIx32 "\n", istate->s4, istate->s5, istate->s6, istate->s7); - + log_printf("s8 =%#010" PRIx32 "\tat =%#010" PRIx32 "\t" "kt0=%#010" PRIx32 "\tkt1=%#010" PRIx32 "\n", istate->s8, istate->at, istate->kt0, istate->kt1); - + log_printf("sp =%#010" PRIx32 "\tra =%#010" PRIx32 "\t" "gp =%#010" PRIx32 "\n", @@ -171,5 +171,5 @@ ip = (cp0_cause_read() & cp0_cause_ip_mask) >> cp0_cause_ip_shift; im = (cp0_status_read() & cp0_status_im_mask) >> cp0_status_im_shift; - + unsigned int i; for (i = 0; i < 8; i++) { @@ -212,10 +212,10 @@ { unsigned int i; - + /* Clear exception table */ for (i = 0; i < IVT_ITEMS; i++) exc_register(i, "undef", false, (iroutine_t) unhandled_exception); - + exc_register(EXC_Bp, "bkpoint", true, (iroutine_t) breakpoint_exception); @@ -230,10 +230,10 @@ exc_register(EXC_Int, "interrupt", true, (iroutine_t) interrupt_exception); - + #ifdef CONFIG_FPU_LAZY exc_register(EXC_CpU, "cpunus", true, (iroutine_t) cpuns_exception); #endif - + exc_register(EXC_Sys, "syscall", true, (iroutine_t) syscall_exception); Index: kernel/arch/mips32/src/interrupt.c =================================================================== --- kernel/arch/mips32/src/interrupt.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/mips32/src/interrupt.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -132,7 +132,7 @@ /* Count overflow detected */ count_hi++; - + lastcount = cp0_count_read(); - + unsigned long drift = cp0_count_read() - nextcount; while (drift > cp0_compare_value) { @@ -140,8 +140,8 @@ CPU->missed_clock_ticks++; } - + nextcount = cp0_count_read() + cp0_compare_value - drift; cp0_compare_write(nextcount); - + /* * We are holding a lock which prevents preemption. @@ -151,5 +151,5 @@ clock(); irq_spinlock_lock(&irq->lock, false); - + if (virtual_timer_fnc != NULL) virtual_timer_fnc(); @@ -172,5 +172,5 @@ { irq_init(IRQ_COUNT, IRQ_COUNT); - + irq_initialize(&timer_irq); timer_irq.inr = TIMER_IRQ; @@ -178,8 +178,8 @@ timer_irq.handler = timer_irq_handler; irq_register(&timer_irq); - + timer_start(); cp0_unmask_int(TIMER_IRQ); - + #ifdef MACHINE_msim irq_initialize(&dorder_irq); @@ -188,5 +188,5 @@ dorder_irq.handler = dorder_irq_handler; irq_register(&dorder_irq); - + cp0_unmask_int(DORDER_IRQ); #endif Index: kernel/arch/mips32/src/mips32.c =================================================================== --- kernel/arch/mips32/src/mips32.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/mips32/src/mips32.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -86,5 +86,5 @@ { init.cnt = min3(bootinfo->cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS); - + size_t i; for (i = 0; i < init.cnt; i++) { @@ -94,5 +94,5 @@ bootinfo->tasks[i].name); } - + for (i = 0; i < CPUMAP_MAX_RECORDS; i++) { if ((bootinfo->cpumap & (1 << i)) != 0) @@ -112,5 +112,5 @@ /* It is not assumed by default */ interrupts_disable(); - + /* Initialize dispatch table */ exception_init(); @@ -123,5 +123,5 @@ memcpy(CACHE_EXC, (char *) cache_error_entry, EXCEPTION_JUMP_SIZE); smc_coherence_block(CACHE_EXC, EXCEPTION_JUMP_SIZE); - + /* * Switch to BEV normal level so that exception vectors point to the @@ -130,10 +130,10 @@ cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit | cp0_status_erl_error_bit)); - + /* * Mask all interrupts */ cp0_mask_all_int(); - + debugger_init(); } @@ -171,5 +171,5 @@ (uintptr_t) kernel_uarg->uspace_uarg, (uintptr_t) kernel_uarg->uspace_entry); - + while (1); } Index: kernel/arch/mips32/src/mm/frame.c =================================================================== --- kernel/arch/mips32/src/mm/frame.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/mips32/src/mm/frame.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -82,5 +82,5 @@ if (frame == (KA2PA(MSIM_VIDEORAM) >> ZERO_PAGE_WIDTH)) return false; - + /* MSIM device (dkeyboard) */ if (frame == (KA2PA(MSIM_KBD_ADDRESS) >> ZERO_PAGE_WIDTH)) @@ -92,5 +92,5 @@ return false; #endif - + return true; } @@ -108,15 +108,15 @@ if ((frame << ZERO_PAGE_WIDTH) < KA2PA(config.base)) return false; - + /* Kernel */ if (overlaps(frame << ZERO_PAGE_WIDTH, ZERO_PAGE_SIZE, KA2PA(config.base), config.kernel_size)) return false; - + /* Kernel stack */ if (overlaps(frame << ZERO_PAGE_WIDTH, ZERO_PAGE_SIZE, KA2PA(config.stack_base), config.stack_size)) return false; - + /* Init tasks */ bool safe = true; @@ -128,5 +128,5 @@ break; } - + return safe; } @@ -161,5 +161,5 @@ ZONE_AVAILABLE | ZONE_HIGHMEM); } - + if (phys_regions_count < MAX_REGIONS) { phys_regions[phys_regions_count].start = first; @@ -182,5 +182,5 @@ { ipl_t ipl = interrupts_disable(); - + /* Clear and initialize TLB */ cp0_pagemask_write(ZERO_PAGE_MASK); @@ -194,9 +194,9 @@ tlbwi(); } - + pfn_t start_frame = 0; pfn_t frame; bool avail = true; - + /* Walk through all 1 MB frames */ for (frame = 0; frame < ZERO_FRAMES; frame++) { @@ -211,5 +211,5 @@ tlb_prepare_entry_lo(&lo1, false, false, false, false, 0); tlb_prepare_entry_hi(&hi, ZERO_PAGE_ASID, ZERO_PAGE_ADDR); - + cp0_pagemask_write(ZERO_PAGE_MASK); cp0_entry_lo0_write(lo0.value); @@ -218,5 +218,5 @@ cp0_index_write(ZERO_PAGE_TLBI); tlbwi(); - + ZERO_PAGE_VALUE = 0; if (ZERO_PAGE_VALUE != 0) @@ -229,5 +229,5 @@ } } - + if (!avail) { frame_add_region(start_frame, frame, true); @@ -236,7 +236,7 @@ } } - + frame_add_region(start_frame, frame, true); - + /* Blacklist interrupt vector frame */ frame_mark_unavailable(0, 1); @@ -267,5 +267,5 @@ frame_mark_unavailable(0, 1024 * 1024 / FRAME_SIZE); #endif - + /* Cleanup */ cp0_pagemask_write(ZERO_PAGE_MASK); @@ -275,5 +275,5 @@ cp0_index_write(ZERO_PAGE_TLBI); tlbwi(); - + interrupts_restore(ipl); } @@ -286,5 +286,5 @@ { printf("[base ] [size ]\n"); - + size_t i; for (i = 0; i < phys_regions_count; i++) { Index: kernel/arch/mips32/src/mm/tlb.c =================================================================== --- kernel/arch/mips32/src/mm/tlb.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/mips32/src/mm/tlb.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -76,10 +76,10 @@ /* Clear and initialize TLB. */ - + for (i = 0; i < TLB_ENTRY_COUNT; i++) { cp0_index_write(i); tlbwi(); } - + /* * The kernel is going to make use of some wired @@ -98,5 +98,5 @@ uintptr_t badvaddr; pte_t pte; - + badvaddr = cp0_badvaddr_read(); @@ -291,16 +291,16 @@ lo1_save.value = cp0_entry_lo1_read(); mask_save.value = cp0_pagemask_read(); - + printf("[nr] [asid] [vpn2 ] [mask] [gvdc] [pfn ]\n"); - + for (i = 0; i < TLB_ENTRY_COUNT; i++) { cp0_index_write(i); tlbr(); - + mask.value = cp0_pagemask_read(); hi.value = cp0_entry_hi_read(); lo0.value = cp0_entry_lo0_read(); lo1.value = cp0_entry_lo1_read(); - + printf("%-4u %-6u %0#10x %-#6x %1u%1u%1u%1u %0#10x\n", i, hi.asid, HI_VPN22ADDR(hi.vpn2), mask.mask, @@ -309,5 +309,5 @@ lo1.g, lo1.v, lo1.d, lo1.c, LO_PFN2ADDR(lo1.pfn)); } - + cp0_entry_hi_write(hi_save.value); cp0_entry_lo0_write(lo0_save.value); @@ -339,8 +339,8 @@ cp0_entry_lo0_write(lo0.value); cp0_entry_lo1_write(lo1.value); - + tlbwi(); } - + cp0_entry_hi_write(hi_save.value); } @@ -360,11 +360,11 @@ hi_save.value = cp0_entry_hi_read(); - + for (i = 0; i < TLB_ENTRY_COUNT; i++) { cp0_index_write(i); tlbr(); - + hi.value = cp0_entry_hi_read(); - + if (hi.asid == asid) { lo0.value = cp0_entry_lo0_read(); @@ -380,5 +380,5 @@ } } - + cp0_entry_hi_write(hi_save.value); } @@ -399,5 +399,5 @@ assert(interrupts_disabled()); - + if (asid == ASID_INVALID) return; @@ -431,5 +431,5 @@ } } - + cp0_entry_hi_write(hi_save.value); } Index: kernel/arch/mips32/src/start.S =================================================================== --- kernel/arch/mips32/src/start.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/mips32/src/start.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -89,25 +89,25 @@ sw $s7, ISTATE_OFFSET_S7(\r) sw $s8, ISTATE_OFFSET_S8(\r) - + mflo $at sw $at, ISTATE_OFFSET_LO(\r) mfhi $at sw $at, ISTATE_OFFSET_HI(\r) - + sw $gp, ISTATE_OFFSET_GP(\r) sw $ra, ISTATE_OFFSET_RA(\r) sw $k0, ISTATE_OFFSET_KT0(\r) sw $k1, ISTATE_OFFSET_KT1(\r) - + mfc0 $t0, $status mfc0 $t1, $epc - + /* save only KSU, EXL, ERL, IE */ and $t2, $t0, REG_SAVE_MASK - + /* clear KSU, EXL, ERL, IE */ li $t3, ~(REG_SAVE_MASK) and $t0, $t0, $t3 - + sw $t2, ISTATE_OFFSET_STATUS(\r) sw $t1, ISTATE_OFFSET_EPC(\r) @@ -122,13 +122,13 @@ mfc0 $t0, $status lw $t1, ISTATE_OFFSET_STATUS(\r) - + /* mask UM, EXL, ERL, IE */ li $t2, ~REG_SAVE_MASK and $t0, $t0, $t2 - + /* copy UM, EXL, ERL, IE from saved status */ or $t0, $t0, $t1 mtc0 $t0, $status - + lw $v0, ISTATE_OFFSET_V0(\r) lw $v1, ISTATE_OFFSET_V1(\r) @@ -147,17 +147,17 @@ lw $t8, ISTATE_OFFSET_T8(\r) lw $t9, ISTATE_OFFSET_T9(\r) - + lw $gp, ISTATE_OFFSET_GP(\r) lw $ra, ISTATE_OFFSET_RA(\r) lw $k1, ISTATE_OFFSET_KT1(\r) - + lw $at, ISTATE_OFFSET_LO(\r) mtlo $at lw $at, ISTATE_OFFSET_HI(\r) mthi $at - + lw $at, ISTATE_OFFSET_EPC(\r) mtc0 $at, $epc - + lw $at, ISTATE_OFFSET_AT(\r) lw $sp, ISTATE_OFFSET_SP(\r) @@ -172,14 +172,14 @@ mfc0 $k0, $status andi $k0, 0x10 - + beq $k0, $0, 1f move $k0, $sp - + /* move $k0 pointer to kernel stack */ la $k0, supervisor_sp - + /* move $k0 (supervisor_sp) */ lw $k0, ($k0) - + 1: .endm @@ -190,12 +190,12 @@ lui $sp, %hi(end_stack) ori $sp, $sp, %lo(end_stack) - + /* not sure about this, but might be needed for PIC code */ lui $gp, 0x8000 - + /* $a1 contains physical address of bootinfo_t */ jal mips32_pre_main addiu $sp, -ABI_STACK_FRAME - + j main_bsp nop @@ -219,20 +219,20 @@ exception_handler: KERNEL_STACK_TO_K0 - + sub $k0, ISTATE_SIZE sw $sp, ISTATE_OFFSET_SP($k0) move $sp, $k0 - + mfc0 $k0, $cause - + sra $k0, $k0, 0x2 /* cp0_exc_cause() part 1 */ andi $k0, $k0, 0x1f /* cp0_exc_cause() part 2 */ sub $k0, 8 /* 8 = SYSCALL */ - + beqz $k0, syscall_shortcut add $k0, 8 /* revert $k0 back to correct exc number */ - + REGISTERS_STORE_AND_EXC_RESET $sp - + move $a1, $sp move $a0, $k0 @@ -240,5 +240,5 @@ addiu $sp, -ABI_STACK_FRAME addiu $sp, ABI_STACK_FRAME - + REGISTERS_LOAD $sp /* the $sp is automatically restored to former value */ @@ -265,13 +265,13 @@ sw $t3, ISTATE_OFFSET_EPC($sp) /* save EPC */ sw $k1, ISTATE_OFFSET_KT1($sp) /* save $k1 not saved on context switch */ - + and $t4, $t2, REG_SAVE_MASK /* save only KSU, EXL, ERL, IE */ li $t5, ~(0x1f) and $t2, $t2, $t5 /* clear KSU, EXL, ERL */ ori $t2, $t2, 0x1 /* set IE */ - + sw $t4, ISTATE_OFFSET_STATUS($sp) mtc0 $t2, $status - + /* * Call the higher level system call handler. @@ -280,12 +280,12 @@ sw $t0, ISTATE_OFFSET_T0($sp) /* save the 5th argument on the stack */ sw $t1, ISTATE_OFFSET_T1($sp) /* save the 6th argument on the stack */ - + jal syscall_handler sw $v0, ISTATE_OFFSET_V0($sp) /* save the syscall number on the stack */ - + /* restore status */ mfc0 $t2, $status lw $t3, ISTATE_OFFSET_STATUS($sp) - + /* * Change back to EXL = 1 (from last exception), otherwise @@ -297,5 +297,5 @@ or $t2, $t2, $t3 /* copy saved UM, EXL, ERL, IE */ mtc0 $t2, $status - + /* restore epc + 4 */ lw $t2, ISTATE_OFFSET_EPC($sp) @@ -303,5 +303,5 @@ addi $t2, $t2, 4 mtc0 $t2, $epc - + lw $sp, ISTATE_OFFSET_SP($sp) /* restore $sp */ eret @@ -314,10 +314,10 @@ sw $sp, ISTATE_OFFSET_SP($k0) move $sp, $k0 - + move $a0, $sp jal tlb_refill addiu $sp, -ABI_STACK_FRAME addiu $sp, ABI_STACK_FRAME - + REGISTERS_LOAD $sp eret @@ -330,10 +330,10 @@ sw $sp, ISTATE_OFFSET_SP($k0) move $sp, $k0 - + move $a0, $sp jal cache_error addiu $sp, -ABI_STACK_FRAME addiu $sp, ABI_STACK_FRAME - + REGISTERS_LOAD $sp eret Index: kernel/arch/ppc32/include/arch/asm.h =================================================================== --- kernel/arch/ppc32/include/arch/asm.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ppc32/include/arch/asm.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -45,10 +45,10 @@ { uint32_t msr; - + asm volatile ( "mfmsr %[msr]\n" : [msr] "=r" (msr) ); - + return msr; } @@ -77,5 +77,5 @@ { uint32_t vsid; - + asm volatile ( "mfsrin %[vsid], %[vaddr]\n" @@ -83,5 +83,5 @@ : [vaddr] "r" (vaddr) ); - + return vsid; } @@ -90,10 +90,10 @@ { uint32_t sdr1; - + asm volatile ( "mfsdr1 %[sdr1]\n" : [sdr1] "=r" (sdr1) ); - + return sdr1; } @@ -173,5 +173,5 @@ { uintptr_t base; - + asm volatile ( "and %[base], %%sp, %[mask]\n" @@ -179,5 +179,5 @@ : [mask] "r" (~(STACK_SIZE - 1)) ); - + return base; } Index: kernel/arch/ppc32/include/arch/atomic.h =================================================================== --- kernel/arch/ppc32/include/arch/atomic.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ppc32/include/arch/atomic.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -41,5 +41,5 @@ { atomic_count_t tmp; - + asm volatile ( "1:\n" @@ -59,5 +59,5 @@ { atomic_count_t tmp; - + asm volatile ( "1:\n" Index: kernel/arch/ppc32/include/arch/barrier.h =================================================================== --- kernel/arch/ppc32/include/arch/barrier.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ppc32/include/arch/barrier.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -77,5 +77,5 @@ { unsigned int i; - + for (i = 0; i < len; i += COHERENCE_INVAL_MIN) asm volatile ( @@ -83,7 +83,7 @@ :: [addr] "r" (addr + i) ); - + memory_barrier(); - + for (i = 0; i < len; i += COHERENCE_INVAL_MIN) asm volatile ( @@ -91,5 +91,5 @@ :: [addr] "r" (addr + i) ); - + instruction_barrier(); } Index: kernel/arch/ppc32/include/arch/cycle.h =================================================================== --- kernel/arch/ppc32/include/arch/cycle.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ppc32/include/arch/cycle.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -43,5 +43,5 @@ uint32_t upper; uint32_t tmp; - + do { asm volatile ( @@ -54,5 +54,5 @@ ); } while (upper != tmp); - + return ((uint64_t) upper << 32) + (uint64_t) lower; } Index: kernel/arch/ppc32/include/arch/mm/frame.h =================================================================== --- kernel/arch/ppc32/include/arch/mm/frame.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ppc32/include/arch/mm/frame.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -49,10 +49,10 @@ { uint32_t physmem; - + asm volatile ( "mfsprg3 %[physmem]\n" : [physmem] "=r" (physmem) ); - + return physmem; } Index: kernel/arch/ppc32/include/arch/mm/page.h =================================================================== --- kernel/arch/ppc32/include/arch/mm/page.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ppc32/include/arch/mm/page.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -165,5 +165,5 @@ { pte_t *entry = &pt[i]; - + return (((!entry->page_cache_disable) << PAGE_CACHEABLE_SHIFT) | ((!entry->present) << PAGE_PRESENT_SHIFT) | @@ -178,5 +178,5 @@ { pte_t *entry = &pt[i]; - + entry->page_cache_disable = !(flags & PAGE_CACHEABLE); entry->present = !(flags & PAGE_NOT_PRESENT); Index: kernel/arch/ppc32/src/asm.S =================================================================== --- kernel/arch/ppc32/src/asm.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ppc32/src/asm.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -40,32 +40,32 @@ * r5 = entry */ - + /* Disable interrupts */ - + mfmsr r31 rlwinm r31, r31, 0, 17, 15 mtmsr r31 isync - + /* Set entry point */ - + mtsrr0 r5 - + /* Set privileged state, enable interrupts */ - + ori r31, r31, MSR_PR ori r31, r31, MSR_EE mtsrr1 r31 - + /* Set stack */ - + mr sp, r4 - + /* %r6 is defined to hold pcb_ptr - set it to 0 */ - + xor r6, r6, r6 - + /* Jump to userspace */ - + rfi FUNCTION_END(userspace_asm) @@ -73,10 +73,10 @@ SYMBOL(iret) /* Disable interrupts */ - + mfmsr r31 rlwinm r31, r31, 0, 17, 15 mtmsr r31 isync - + lwz r0, ISTATE_OFFSET_R0(sp) lwz r2, ISTATE_OFFSET_R2(sp) @@ -109,36 +109,36 @@ lwz r30, ISTATE_OFFSET_R30(sp) lwz r31, ISTATE_OFFSET_R31(sp) - + lwz r12, ISTATE_OFFSET_CR(sp) mtcr r12 - + lwz r12, ISTATE_OFFSET_PC(sp) mtsrr0 r12 - + lwz r12, ISTATE_OFFSET_SRR1(sp) mtsrr1 r12 - + lwz r12, ISTATE_OFFSET_LR(sp) mtlr r12 - + lwz r12, ISTATE_OFFSET_CTR(sp) mtctr r12 - + lwz r12, ISTATE_OFFSET_XER(sp) mtxer r12 - + lwz r12, ISTATE_OFFSET_R12(sp) lwz sp, ISTATE_OFFSET_SP(sp) - + rfi SYMBOL(iret_syscall) /* Disable interrupts */ - + mfmsr r31 rlwinm r31, r31, 0, 17, 15 mtmsr r31 isync - + lwz r0, ISTATE_OFFSET_R0(sp) lwz r2, ISTATE_OFFSET_R2(sp) @@ -170,26 +170,26 @@ lwz r30, ISTATE_OFFSET_R30(sp) lwz r31, ISTATE_OFFSET_R31(sp) - + lwz r12, ISTATE_OFFSET_CR(sp) mtcr r12 - + lwz r12, ISTATE_OFFSET_PC(sp) mtsrr0 r12 - + lwz r12, ISTATE_OFFSET_SRR1(sp) mtsrr1 r12 - + lwz r12, ISTATE_OFFSET_LR(sp) mtlr r12 - + lwz r12, ISTATE_OFFSET_CTR(sp) mtctr r12 - + lwz r12, ISTATE_OFFSET_XER(sp) mtxer r12 - + lwz r12, ISTATE_OFFSET_R12(sp) lwz sp, ISTATE_OFFSET_SP(sp) - + rfi @@ -200,11 +200,11 @@ addi r4, r4, -4 beq 2f - + andi. r0, r6, 3 mtctr r7 bne 5f - + 1: - + lwz r7, 4(r4) lwzu r8, 8(r4) @@ -212,18 +212,18 @@ stwu r8, 8(r6) bdnz 1b - + andi. r5, r5, 7 - + 2: - + cmplwi 0, r5, 4 blt 3f - + lwzu r0, 4(r4) addi r5, r5, -4 stwu r0, 4(r6) - + 3: - + cmpwi 0, r5, 0 beqlr @@ -231,19 +231,19 @@ addi r4, r4, 3 addi r6, r6, 3 - + 4: - + lbzu r0, 1(r4) stbu r0, 1(r6) bdnz 4b blr - + 5: - + subfic r0, r0, 4 mtctr r0 - + 6: - + lbz r7, 4(r4) addi r4, r4, 1 Index: kernel/arch/ppc32/src/boot/boot.S =================================================================== --- kernel/arch/ppc32/src/boot/boot.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ppc32/src/boot/boot.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -35,16 +35,16 @@ SYMBOL(kernel_image_start) # load temporal kernel stack - + lis sp, kernel_stack@ha addi sp, sp, kernel_stack@l - + # set kernel stack for interrupt handling - + mr r31, sp subis r31, r31, 0x8000 mtsprg0 r31 - + # r3 contains physical address of bootinfo_t - + addis r3, r3, 0x8000 bl ppc32_pre_main Index: kernel/arch/ppc32/src/context.S =================================================================== --- kernel/arch/ppc32/src/context.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ppc32/src/context.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -55,11 +55,11 @@ stw r30, CONTEXT_OFFSET_R30(r3) stw r31, CONTEXT_OFFSET_R31(r3) - + mflr r4 stw r4, CONTEXT_OFFSET_PC(r3) - + mfcr r4 stw r4, CONTEXT_OFFSET_CR(r3) - + # context_save returns 1 li r3, 1 @@ -89,11 +89,11 @@ lwz r30, CONTEXT_OFFSET_R30(r3) lwz r31, CONTEXT_OFFSET_R31(r3) - + lwz r4, CONTEXT_OFFSET_CR(r3) mtcr r4 - + lwz r4, CONTEXT_OFFSET_PC(r3) mtlr r4 - + # context_restore returns 0 li r3, 0 Index: kernel/arch/ppc32/src/cpu/cpu.c =================================================================== --- kernel/arch/ppc32/src/cpu/cpu.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ppc32/src/cpu/cpu.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -54,5 +54,5 @@ { const char *name; - + switch (cpu->arch.version) { case 8: @@ -71,5 +71,5 @@ name = "unknown"; } - + printf("cpu%u: version=%" PRIu16" (%s), revision=%" PRIu16 "\n", cpu->id, cpu->arch.version, name, cpu->arch.revision); Index: kernel/arch/ppc32/src/drivers/pic.c =================================================================== --- kernel/arch/ppc32/src/drivers/pic.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ppc32/src/drivers/pic.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -55,5 +55,5 @@ pic[PIC_MASK_HIGH] = pic[PIC_MASK_HIGH] | (1 << (intnum - 32)); } - + } @@ -85,14 +85,14 @@ if (pic) { uint32_t pending; - + pending = pic[PIC_PENDING_LOW]; if (pending != 0) return fnzb32(pending); - + pending = pic[PIC_PENDING_HIGH]; if (pending != 0) return fnzb32(pending) + 32; } - + return 255; } Index: kernel/arch/ppc32/src/exception.S =================================================================== --- kernel/arch/ppc32/src/exception.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ppc32/src/exception.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -38,29 +38,29 @@ .macro CONTEXT_STORE - + # save r12 in SPRG1, backup CR in r12 # save SP in SPRG2 - + mtsprg1 r12 mfcr r12 mtsprg2 sp - + # check whether the previous mode was user or kernel - + mfsrr1 sp # use sp as a temporary register to hold SRR1 andi. sp, sp, MSR_PR bne 1f # previous mode was kernel - + mfsprg2 sp subis sp, sp, 0x8000 b 2f - + 1: # previous mode was user - + mfsprg0 sp 2: - + subi sp, sp, ALIGN_UP(ISTATE_SIZE, STACK_ALIGNMENT) stw r0, ISTATE_OFFSET_R0(sp) @@ -94,28 +94,28 @@ stw r30, ISTATE_OFFSET_R30(sp) stw r31, ISTATE_OFFSET_R31(sp) - + stw r12, ISTATE_OFFSET_CR(sp) - + mfsrr0 r12 stw r12, ISTATE_OFFSET_PC(sp) - + mfsrr1 r12 stw r12, ISTATE_OFFSET_SRR1(sp) - + mflr r12 stw r12, ISTATE_OFFSET_LR(sp) - + mfctr r12 stw r12, ISTATE_OFFSET_CTR(sp) - + mfxer r12 stw r12, ISTATE_OFFSET_XER(sp) - + mfdar r12 stw r12, ISTATE_OFFSET_DAR(sp) - + mfsprg1 r12 stw r12, ISTATE_OFFSET_R12(sp) - + mfsprg2 r12 stw r12, ISTATE_OFFSET_SP(sp) @@ -129,5 +129,5 @@ SYMBOL(exc_system_reset) CONTEXT_STORE - + li r3, 0 b jump_to_kernel @@ -136,5 +136,5 @@ SYMBOL(exc_machine_check) CONTEXT_STORE - + li r3, 1 b jump_to_kernel @@ -143,5 +143,5 @@ SYMBOL(exc_data_storage) CONTEXT_STORE - + li r3, 2 b jump_to_kernel @@ -150,5 +150,5 @@ SYMBOL(exc_instruction_storage) CONTEXT_STORE - + li r3, 3 b jump_to_kernel @@ -157,5 +157,5 @@ SYMBOL(exc_external) CONTEXT_STORE - + li r3, 4 b jump_to_kernel @@ -164,5 +164,5 @@ SYMBOL(exc_alignment) CONTEXT_STORE - + li r3, 5 b jump_to_kernel @@ -171,5 +171,5 @@ SYMBOL(exc_program) CONTEXT_STORE - + li r3, 6 b jump_to_kernel @@ -178,5 +178,5 @@ SYMBOL(exc_fp_unavailable) CONTEXT_STORE - + li r3, 7 b jump_to_kernel @@ -185,5 +185,5 @@ SYMBOL(exc_decrementer) CONTEXT_STORE - + li r3, 8 b jump_to_kernel @@ -192,5 +192,5 @@ SYMBOL(exc_reserved0) CONTEXT_STORE - + li r3, 9 b jump_to_kernel @@ -199,5 +199,5 @@ SYMBOL(exc_reserved1) CONTEXT_STORE - + li r3, 10 b jump_to_kernel @@ -206,5 +206,5 @@ SYMBOL(exc_syscall) CONTEXT_STORE - + b jump_to_kernel_syscall @@ -212,5 +212,5 @@ SYMBOL(exc_trace) CONTEXT_STORE - + li r3, 12 b jump_to_kernel @@ -219,5 +219,5 @@ SYMBOL(exc_itlb_miss) CONTEXT_STORE - + li r3, 13 b jump_to_kernel @@ -226,5 +226,5 @@ SYMBOL(exc_dtlb_miss_load) CONTEXT_STORE - + li r3, 14 b jump_to_kernel @@ -233,5 +233,5 @@ SYMBOL(exc_dtlb_miss_store) CONTEXT_STORE - + li r3, 15 b jump_to_kernel @@ -244,5 +244,5 @@ # Previous mode was kernel. # We can construct a proper frame linkage. - + mfsrr0 r12 stw r12, ISTATE_OFFSET_LR_FRAME(sp) @@ -265,8 +265,8 @@ ori r12, r12, (MSR_IR | MSR_DR) mtsrr1 r12 - + addis sp, sp, 0x8000 mr r4, sp - + rfi @@ -275,5 +275,5 @@ addi r12, r12, syscall_handler@l mtsrr0 r12 - + lis r12, iret_syscall@ha addi r12, r12, iret_syscall@l @@ -286,5 +286,5 @@ ori r12, r12, (MSR_IR | MSR_DR | MSR_EE) mtsrr1 r12 - + addis sp, sp, 0x8000 rfi Index: kernel/arch/ppc32/src/fpu_context.S =================================================================== --- kernel/arch/ppc32/src/fpu_context.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ppc32/src/fpu_context.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -106,8 +106,8 @@ FUNCTION_BEGIN(fpu_context_save) FPU_CONTEXT_STORE r3 - + mffs fr0 stfd fr0, FPU_CONTEXT_OFFSET_FPSCR(r3) - + blr FUNCTION_END(fpu_context_save) @@ -116,7 +116,7 @@ lfd fr0, FPU_CONTEXT_OFFSET_FPSCR(r3) mtfsf 0xff, fr0 - + FPU_CONTEXT_LOAD r3 - + blr FUNCTION_END(fpu_context_restore) @@ -125,12 +125,12 @@ mfmsr r0 ori r0, r0, MSR_FP - + # Disable FPU exceptions li r3, MSR_FE0 | MSR_FE1 andc r0, r0, r3 - + mtmsr r0 isync - + blr FUNCTION_END(fpu_init) Index: kernel/arch/ppc32/src/interrupt.c =================================================================== --- kernel/arch/ppc32/src/interrupt.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ppc32/src/interrupt.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -66,41 +66,41 @@ log_printf("r0 =%0#10" PRIx32 "\tr1 =%0#10" PRIx32 "\t" "r2 =%0#10" PRIx32 "\n", istate->r0, istate->sp, istate->r2); - + log_printf("r3 =%0#10" PRIx32 "\tr4 =%0#10" PRIx32 "\t" "r5 =%0#10" PRIx32 "\n", istate->r3, istate->r4, istate->r5); - + log_printf("r6 =%0#10" PRIx32 "\tr7 =%0#10" PRIx32 "\t" "r8 =%0#10" PRIx32 "\n", istate->r6, istate->r7, istate->r8); - + log_printf("r9 =%0#10" PRIx32 "\tr10=%0#10" PRIx32 "\t" "r11=%0#10" PRIx32 "\n", istate->r9, istate->r10, istate->r11); - + log_printf("r12=%0#10" PRIx32 "\tr13=%0#10" PRIx32 "\t" "r14=%0#10" PRIx32 "\n", istate->r12, istate->r13, istate->r14); - + log_printf("r15=%0#10" PRIx32 "\tr16=%0#10" PRIx32 "\t" "r17=%0#10" PRIx32 "\n", istate->r15, istate->r16, istate->r17); - + log_printf("r18=%0#10" PRIx32 "\tr19=%0#10" PRIx32 "\t" "r20=%0#10" PRIx32 "\n", istate->r18, istate->r19, istate->r20); - + log_printf("r21=%0#10" PRIx32 "\tr22=%0#10" PRIx32 "\t" "r23=%0#10" PRIx32 "\n", istate->r21, istate->r22, istate->r23); - + log_printf("r24=%0#10" PRIx32 "\tr25=%0#10" PRIx32 "\t" "r26=%0#10" PRIx32 "\n", istate->r24, istate->r25, istate->r26); - + log_printf("r27=%0#10" PRIx32 "\tr28=%0#10" PRIx32 "\t" "r29=%0#10" PRIx32 "\n", istate->r27, istate->r28, istate->r29); - + log_printf("r30=%0#10" PRIx32 "\tr31=%0#10" PRIx32 "\n", istate->r30, istate->r31); - + log_printf("cr =%0#10" PRIx32 "\tpc =%0#10" PRIx32 "\t" "lr =%0#10" PRIx32 "\n", istate->cr, istate->pc, istate->lr); - + log_printf("ctr=%0#10" PRIx32 "\txer=%0#10" PRIx32 "\t" "dar=%0#10" PRIx32 "\n", istate->ctr, istate->xer, istate->dar); - + log_printf("srr1=%0#10" PRIx32 "\n", istate->srr1); } @@ -119,5 +119,5 @@ * The IRQ handler was found. */ - + if (irq->preack) { /* Acknowledge the interrupt before processing */ @@ -125,12 +125,12 @@ irq->cir(irq->cir_arg, irq->inr); } - + irq->handler(irq); - + if (!irq->preack) { if (irq->cir) irq->cir(irq->cir_arg, irq->inr); } - + irq_spinlock_unlock(&irq->lock, false); } else { Index: kernel/arch/ppc32/src/mm/as.c =================================================================== --- kernel/arch/ppc32/src/mm/as.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ppc32/src/mm/as.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -56,9 +56,9 @@ { uint32_t sr; - + /* Lower 2 GB, user and supervisor access */ for (sr = 0; sr < 8; sr++) sr_set(0x6000, as->asid, sr); - + /* Upper 2 GB, only supervisor access */ for (sr = 8; sr < 16; sr++) Index: kernel/arch/ppc32/src/mm/frame.c =================================================================== --- kernel/arch/ppc32/src/mm/frame.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ppc32/src/mm/frame.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -45,5 +45,5 @@ { printf("[base ] [size ]\n"); - + size_t i; for (i = 0; i < memmap.cnt; i++) { @@ -57,5 +57,5 @@ pfn_t minconf = 2; size_t i; - + for (i = 0; i < memmap.cnt; i++) { /* To be safe, make the available zone possibly smaller */ @@ -64,5 +64,5 @@ size_t size = ALIGN_DOWN(memmap.zones[i].size - (base - ((uintptr_t) memmap.zones[i].start)), FRAME_SIZE); - + if (!frame_adjust_zone_bounds(low, &base, &size)) return; @@ -86,5 +86,5 @@ } } - + } @@ -92,12 +92,12 @@ { frame_common_arch_init(true); - + /* First is exception vector, second is 'implementation specific', third and fourth is reserved, other contain real mode code */ frame_mark_unavailable(0, 8); - + /* Mark the Page Hash Table frames as unavailable */ uint32_t sdr1 = sdr1_get(); - + // FIXME: compute size of PHT exactly frame_mark_unavailable(ADDR2PFN(sdr1 & 0xffff000), 16); Index: kernel/arch/ppc32/src/mm/pht.c =================================================================== --- kernel/arch/ppc32/src/mm/pht.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ppc32/src/mm/pht.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -93,11 +93,11 @@ uint32_t page = (vaddr >> 12) & 0xffff; uint32_t api = (vaddr >> 22) & 0x3f; - + uint32_t vsid = sr_get(vaddr); uint32_t sdr1 = sdr1_get(); - + // FIXME: compute size of PHT exactly phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); - + /* Primary hash (xor) */ uint32_t h = 0; @@ -106,5 +106,5 @@ uint32_t i; bool found = false; - + /* Find colliding PTE in PTEG */ for (i = 0; i < 8; i++) { @@ -117,5 +117,5 @@ } } - + if (!found) { /* Find unused PTE in PTEG */ @@ -127,9 +127,9 @@ } } - + if (!found) { /* Secondary hash (not) */ uint32_t base2 = (~hash & 0x3ff) << 3; - + /* Find colliding PTE in PTEG */ for (i = 0; i < 8; i++) { @@ -144,5 +144,5 @@ } } - + if (!found) { /* Find unused PTE in PTEG */ @@ -156,9 +156,9 @@ } } - + if (!found) i = RANDI(seed) % 8; } - + phte[base + i].v = 1; phte[base + i].vsid = vsid; @@ -181,14 +181,14 @@ { uintptr_t badvaddr; - + if (n == VECTOR_DATA_STORAGE) badvaddr = istate->dar; else badvaddr = istate->pc; - + pte_t pte; bool found = find_mapping_and_check(AS, badvaddr, PF_ACCESS_READ /* FIXME */, istate, &pte); - + if (found) { /* Record access to PTE */ @@ -201,8 +201,8 @@ { uint32_t sdr1 = sdr1_get(); - + // FIXME: compute size of PHT exactly phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); - + // FIXME: this invalidates all PHT entries, // which is an overkill, invalidate only Index: kernel/arch/ppc32/src/mm/tlb.c =================================================================== --- kernel/arch/ppc32/src/mm/tlb.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ppc32/src/mm/tlb.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -42,5 +42,5 @@ ptehi_t ptehi; ptelo_t ptelo; - + asm volatile ( "mfspr %[tlbmiss], 980\n" @@ -51,15 +51,15 @@ [ptelo] "=r" (ptelo) ); - + uint32_t badvaddr = tlbmiss & 0xfffffffc; uint32_t physmem = physmem_top(); - + if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) return; // FIXME - + ptelo.rpn = KA2PA(badvaddr) >> 12; ptelo.wimg = 0; ptelo.pp = 2; // FIXME - + uint32_t index = 0; asm volatile ( @@ -84,5 +84,5 @@ "sync\n" ); - + for (unsigned int i = 0; i < 0x00040000; i += 0x00001000) { asm volatile ( @@ -91,5 +91,5 @@ ); } - + asm volatile ( "eieio\n" @@ -143,8 +143,8 @@ { uint32_t sr; - + for (sr = 0; sr < 16; sr++) { uint32_t vsid = sr_get(sr << 28); - + printf("sr[%02" PRIu32 "]: vsid=%#0" PRIx32 " (asid=%" PRIu32 ")" "%s%s\n", sr, vsid & UINT32_C(0x00ffffff), @@ -153,15 +153,15 @@ ((vsid >> 29) & 1) ? " user" : ""); } - + uint32_t upper; uint32_t lower; uint32_t mask; uint32_t length; - + PRINT_BAT("ibat[0]", 528, 529); PRINT_BAT("ibat[1]", 530, 531); PRINT_BAT("ibat[2]", 532, 533); PRINT_BAT("ibat[3]", 534, 535); - + PRINT_BAT("dbat[0]", 536, 537); PRINT_BAT("dbat[1]", 538, 539); Index: kernel/arch/ppc32/src/ppc32.c =================================================================== --- kernel/arch/ppc32/src/ppc32.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ppc32/src/ppc32.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -91,5 +91,5 @@ bootinfo->taskmap.tasks[i].name); } - + /* Copy physical memory map. */ memmap.total = bootinfo->memmap.total; @@ -99,9 +99,9 @@ memmap.zones[i].size = bootinfo->memmap.zones[i].size; } - + /* Copy boot allocations info. */ ballocs.base = bootinfo->ballocs.base; ballocs.size = bootinfo->ballocs.size; - + /* Copy OFW tree. */ ofw_tree_init(bootinfo->ofw_root); @@ -112,5 +112,5 @@ /* Initialize dispatch table */ interrupt_init(); - + ofw_tree_node_t *cpus_node; ofw_tree_node_t *cpu_node; @@ -144,17 +144,17 @@ uint32_t fb_scanline = 0; unsigned int visual = VISUAL_UNKNOWN; - + ofw_tree_property_t *prop = ofw_tree_getprop(node, "address"); if ((prop) && (prop->value)) fb_addr = *((uintptr_t *) prop->value); - + prop = ofw_tree_getprop(node, "width"); if ((prop) && (prop->value)) fb_width = *((uint32_t *) prop->value); - + prop = ofw_tree_getprop(node, "height"); if ((prop) && (prop->value)) fb_height = *((uint32_t *) prop->value); - + prop = ofw_tree_getprop(node, "depth"); if ((prop) && (prop->value)) { @@ -180,9 +180,9 @@ } } - + prop = ofw_tree_getprop(node, "linebytes"); if ((prop) && (prop->value)) fb_scanline = *((uint32_t *) prop->value); - + if ((fb_addr) && (fb_width > 0) && (fb_height > 0) && (fb_scanline > 0) && (visual != VISUAL_UNKNOWN)) { @@ -195,10 +195,10 @@ .visual = visual, }; - + outdev_t *fbdev = fb_init(&fb_prop); if (fbdev) stdout_wire(fbdev); } - + return true; } @@ -213,8 +213,8 @@ /* Map OFW information into sysinfo */ ofw_sysinfo_map(); - + /* Initialize IRQ routing */ irq_init(IRQ_COUNT, IRQ_COUNT); - + /* Merge all zones to 1 big zone */ zone_merge_all(); @@ -225,14 +225,14 @@ { ofw_pci_reg_t *assigned_address = NULL; - + ofw_tree_property_t *prop = ofw_tree_getprop(node, "assigned-addresses"); if ((prop) && (prop->value)) assigned_address = ((ofw_pci_reg_t *) prop->value); - + if (assigned_address) { /* Initialize PIC */ pic_init(assigned_address[0].addr, PAGE_SIZE, &pic_cir, &pic_cir_arg); - + #ifdef CONFIG_MAC_KBD uintptr_t pa = assigned_address[0].addr + 0x16000; @@ -240,8 +240,8 @@ size_t offset = pa - aligned_addr; size_t size = 2 * PAGE_SIZE; - + cuda_t *cuda = (cuda_t *) (km_map(aligned_addr, offset + size, PAGE_WRITE | PAGE_NOT_CACHEABLE) + offset); - + /* Initialize I/O controller */ cuda_instance_t *cuda_instance = @@ -256,5 +256,5 @@ } } - + /* * This is the necessary evil until the userspace driver is entirely @@ -266,5 +266,5 @@ #endif } - + /* Consider only a single device for now */ return false; @@ -299,5 +299,5 @@ kernel_uarg->uspace_stack_size - SP_DELTA, (uintptr_t) kernel_uarg->uspace_entry); - + /* Unreachable */ while (true); Index: kernel/arch/ppc32/src/proc/scheduler.c =================================================================== --- kernel/arch/ppc32/src/proc/scheduler.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/ppc32/src/proc/scheduler.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -52,5 +52,5 @@ { tlb_invalidate_all(); - + asm volatile ( "mtsprg0 %[ksp]\n" Index: kernel/arch/riscv64/include/arch/asm.h =================================================================== --- kernel/arch/riscv64/include/arch/asm.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/riscv64/include/arch/asm.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -45,10 +45,10 @@ { ipl_t ipl; - + asm volatile ( "csrrsi %[ipl], sstatus, " STRING(SSTATUS_SIE_MASK) "\n" : [ipl] "=r" (ipl) ); - + return ipl; } @@ -57,10 +57,10 @@ { ipl_t ipl; - + asm volatile ( "csrrci %[ipl], sstatus, " STRING(SSTATUS_SIE_MASK) "\n" : [ipl] "=r" (ipl) ); - + return ipl; } @@ -77,10 +77,10 @@ { ipl_t ipl; - + asm volatile ( "csrr %[ipl], sstatus\n" : [ipl] "=r" (ipl) ); - + return ipl; } @@ -94,5 +94,5 @@ { uintptr_t base; - + asm volatile ( "and %[base], sp, %[mask]\n" @@ -100,5 +100,5 @@ : [mask] "r" (~(STACK_SIZE - 1)) ); - + return base; } Index: kernel/arch/riscv64/include/arch/atomic.h =================================================================== --- kernel/arch/riscv64/include/arch/atomic.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/riscv64/include/arch/atomic.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -59,5 +59,5 @@ { atomic_count_t orig; - + asm volatile ( "amoadd.d %[orig], %[inc], %[addr]\n" @@ -65,5 +65,5 @@ : [inc] "r" (1) ); - + return orig; } @@ -72,5 +72,5 @@ { atomic_count_t orig; - + asm volatile ( "amoadd.d %[orig], %[inc], %[addr]\n" @@ -78,5 +78,5 @@ : [inc] "r" (-1) ); - + return orig; } @@ -85,5 +85,5 @@ { atomic_count_t orig; - + asm volatile ( "amoadd.d %[orig], %[inc], %[addr]\n" @@ -91,5 +91,5 @@ : [inc] "r" (1) ); - + return orig - 1; } @@ -98,5 +98,5 @@ { atomic_count_t orig; - + asm volatile ( "amoadd.d %[orig], %[inc], %[addr]\n" @@ -104,5 +104,5 @@ : [inc] "r" (-1) ); - + return orig + 1; } Index: kernel/arch/riscv64/include/arch/cycle.h =================================================================== --- kernel/arch/riscv64/include/arch/cycle.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/riscv64/include/arch/cycle.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -41,10 +41,10 @@ { uint64_t cycle; - + asm volatile ( "rdcycle %[cycle]\n" : [cycle] "=r" (cycle) ); - + return cycle; } Index: kernel/arch/riscv64/include/arch/mm/page.h =================================================================== --- kernel/arch/riscv64/include/arch/mm/page.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/riscv64/include/arch/mm/page.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -182,5 +182,5 @@ { pte_t *entry = &pt[i]; - + return (((!entry->valid) << PAGE_PRESENT_SHIFT) | (entry->user << PAGE_USER_SHIFT) | @@ -194,5 +194,5 @@ { pte_t *entry = &pt[i]; - + entry->valid = !(flags & PAGE_NOT_PRESENT); entry->readable = (flags & PAGE_READ) != 0; Index: kernel/arch/riscv64/src/boot/boot.S =================================================================== --- kernel/arch/riscv64/src/boot/boot.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/riscv64/src/boot/boot.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -36,14 +36,14 @@ /* Setup temporary stack */ la sp, temp_stack - + /* Create the first stack frame */ addi sp, sp, -16 - + /* Call riscv64_pre_main() */ jal riscv64_pre_main - + /* Call main_bsp() */ jal main_bsp - + /* Not reached */ csrci sstatus, SSTATUS_SIE_MASK Index: kernel/arch/riscv64/src/context.S =================================================================== --- kernel/arch/riscv64/src/context.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/riscv64/src/context.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -47,8 +47,8 @@ sd s10, CONTEXT_OFFSET_S10(a0) sd s11, CONTEXT_OFFSET_S11(a0) - + sd ra, CONTEXT_OFFSET_PC(a0) sd sp, CONTEXT_OFFSET_SP(a0) - + # context_save returns 1 li a0, 1 @@ -71,8 +71,8 @@ ld s10, CONTEXT_OFFSET_S10(a0) ld s11, CONTEXT_OFFSET_S11(a0) - + ld ra, CONTEXT_OFFSET_PC(a0) ld sp, CONTEXT_OFFSET_SP(a0) - + # context_restore returns 0 li a0, 0 Index: kernel/arch/riscv64/src/drivers/ucb.c =================================================================== --- kernel/arch/riscv64/src/drivers/ucb.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/riscv64/src/drivers/ucb.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -53,5 +53,5 @@ if (!val) return; - + *fromhost = 0; } @@ -68,5 +68,5 @@ if (!htifdev) return NULL; - + outdev_initialize("htifdev", htifdev, &htifdev_ops); return htifdev; @@ -78,8 +78,8 @@ (((uint64_t) cmd) << 48) | (payload & UINT64_C(0xffffffffffff)); - + while (*tohost) poll_fromhost(); - + *tohost = val; } Index: kernel/arch/riscv64/src/mm/frame.c =================================================================== --- kernel/arch/riscv64/src/mm/frame.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/riscv64/src/mm/frame.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -56,5 +56,5 @@ pfn_t minconf = max3(ADDR2PFN(physmem_start), htif_frame + 1, pt_frame + 1); - + for (size_t i = 0; i < memmap.cnt; i++) { /* To be safe, make the available zone possibly smaller */ @@ -63,12 +63,12 @@ size_t size = ALIGN_DOWN(memmap.zones[i].size - (base - ((uintptr_t) memmap.zones[i].start)), FRAME_SIZE); - + if (!frame_adjust_zone_bounds(low, &base, &size)) return; - + pfn_t pfn = ADDR2PFN(base); size_t count = SIZE2FRAMES(size); pfn_t conf; - + if (low) { if ((minconf < pfn) || (minconf >= pfn + count)) @@ -76,5 +76,5 @@ else conf = minconf; - + zone_create(pfn, count, conf, ZONE_AVAILABLE | ZONE_LOWMEM); @@ -91,5 +91,5 @@ { frame_common_arch_init(true); - + frame_mark_unavailable(htif_frame, 1); frame_mark_unavailable(pt_frame, 1); Index: kernel/arch/riscv64/src/mm/page.c =================================================================== --- kernel/arch/riscv64/src/mm/page.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/riscv64/src/mm/page.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -53,7 +53,7 @@ if (config.cpu_active == 1) { page_mapping_operations = &pt_mapping_operations; - + page_table_lock(AS_KERNEL, true); - + /* * PA2KA(identity) mapping for all low-memory frames. @@ -64,11 +64,11 @@ page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, PAGE_GLOBAL | PAGE_CACHEABLE | PAGE_EXEC | PAGE_WRITE | PAGE_READ); - + page_table_unlock(AS_KERNEL, true); - + // FIXME: register page fault extension handler - + write_satp((uintptr_t) AS_KERNEL->genarch.page_table); - + /* The boot page table is no longer needed. */ // FIXME: frame_mark_available(pt_frame, 1); @@ -84,5 +84,5 @@ uint64_t satp = ((ptl0 >> FRAME_WIDTH) & SATP_PFN_MASK) | SATP_MODE_SV48; - + asm volatile ( "csrw sptbr, %[satp]\n" Index: kernel/arch/riscv64/src/riscv64.c =================================================================== --- kernel/arch/riscv64/src/riscv64.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/riscv64/src/riscv64.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -69,11 +69,11 @@ htif_frame = bootinfo->htif_frame; pt_frame = bootinfo->pt_frame; - + htif_init(bootinfo->ucbinfo.tohost, bootinfo->ucbinfo.fromhost); - + /* Copy tasks map. */ init.cnt = min3(bootinfo->taskmap.cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS); - + for (size_t i = 0; i < init.cnt; i++) { init.tasks[i].paddr = KA2PA(bootinfo->taskmap.tasks[i].addr); @@ -82,5 +82,5 @@ bootinfo->taskmap.tasks[i].name); } - + /* Copy physical memory map. */ memmap.total = bootinfo->memmap.total; Index: kernel/arch/sparc64/include/arch/asm.h =================================================================== --- kernel/arch/sparc64/include/arch/asm.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/include/arch/asm.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -91,10 +91,10 @@ { uint64_t v; - + asm volatile ( "rdpr %%pstate, %[v]\n" : [v] "=r" (v) ); - + return v; } @@ -122,10 +122,10 @@ { uint64_t v; - + asm volatile ( "rd %%tick_cmpr, %[v]\n" : [v] "=r" (v) ); - + return v; } @@ -153,10 +153,10 @@ { uint64_t v; - + asm volatile ( "rd %%asr25, %[v]\n" : [v] "=r" (v) ); - + return v; } @@ -184,10 +184,10 @@ { uint64_t v; - + asm volatile ( "rdpr %%tick, %[v]\n" : [v] "=r" (v) ); - + return v; } @@ -215,10 +215,10 @@ { uint64_t v; - + asm volatile ( "rd %%fprs, %[v]\n" : [v] "=r" (v) ); - + return v; } @@ -246,10 +246,10 @@ { uint64_t v; - + asm volatile ( "rd %%softint, %[v]\n" : [v] "=r" (v) ); - + return v; } @@ -312,9 +312,9 @@ pstate_reg_t pstate; uint64_t value = pstate_read(); - + pstate.value = value; pstate.ie = true; pstate_write(pstate.value); - + return (ipl_t) value; } @@ -331,9 +331,9 @@ pstate_reg_t pstate; uint64_t value = pstate_read(); - + pstate.value = value; pstate.ie = false; pstate_write(pstate.value); - + return (ipl_t) value; } @@ -348,5 +348,5 @@ NO_TRACE static inline void interrupts_restore(ipl_t ipl) { pstate_reg_t pstate; - + pstate.value = pstate_read(); pstate.ie = ((pstate_reg_t)(uint64_t) ipl).ie; @@ -373,5 +373,5 @@ { pstate_reg_t pstate; - + pstate.value = pstate_read(); return !pstate.ie; @@ -388,5 +388,5 @@ { uintptr_t unbiased_sp; - + asm volatile ( "add %%sp, %[stack_bias], %[unbiased_sp]\n" @@ -394,5 +394,5 @@ : [stack_bias] "i" (STACK_BIAS) ); - + return ALIGN_DOWN(unbiased_sp, STACK_SIZE); } @@ -406,10 +406,10 @@ { uint64_t v; - + asm volatile ( "rdpr %%ver, %[v]\n" : [v] "=r" (v) ); - + return v; } @@ -423,10 +423,10 @@ { uint64_t v; - + asm volatile ( "rdpr %%tpc, %[v]\n" : [v] "=r" (v) ); - + return v; } @@ -440,10 +440,10 @@ { uint64_t v; - + asm volatile ( "rdpr %%tl, %[v]\n" : [v] "=r" (v) ); - + return v; } @@ -457,10 +457,10 @@ { uint64_t v; - + asm volatile ( "rdpr %%tba, %[v]\n" : [v] "=r" (v) ); - + return v; } @@ -492,5 +492,5 @@ { uint64_t v; - + asm volatile ( "ldxa [%[va]] %[asi], %[v]\n" @@ -499,5 +499,5 @@ [asi] "i" ((unsigned int) asi) ); - + return v; } Index: kernel/arch/sparc64/include/arch/atomic.h =================================================================== --- kernel/arch/sparc64/include/arch/atomic.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/include/arch/atomic.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -56,11 +56,11 @@ atomic_count_t a; atomic_count_t b; - + do { volatile uintptr_t ptr = (uintptr_t) &val->count; - + a = *((atomic_count_t *) ptr); b = a + i; - + asm volatile ( "casx %0, %2, %1\n" @@ -70,5 +70,5 @@ ); } while (a != b); - + return a; } @@ -108,5 +108,5 @@ atomic_count_t v = 1; volatile uintptr_t ptr = (uintptr_t) &val->count; - + asm volatile ( "casx %0, %2, %1\n" @@ -115,5 +115,5 @@ : "r" (0) ); - + return v; } @@ -123,9 +123,9 @@ atomic_count_t tmp1 = 1; atomic_count_t tmp2 = 0; - + volatile uintptr_t ptr = (uintptr_t) &val->count; - + preemption_disable(); - + asm volatile ( "0:\n" @@ -144,5 +144,5 @@ : "r" (0) ); - + /* * Prevent critical section code from bleeding out this way up. Index: kernel/arch/sparc64/include/arch/barrier.h =================================================================== --- kernel/arch/sparc64/include/arch/barrier.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/include/arch/barrier.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -83,5 +83,5 @@ { unsigned long pc; - + /* * The FLUSH instruction takes address parameter. @@ -94,5 +94,5 @@ * */ - + asm volatile ( "rd %%pc, %[pc]\n" Index: kernel/arch/sparc64/include/arch/cpu_family.h =================================================================== --- kernel/arch/sparc64/include/arch/cpu_family.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/include/arch/cpu_family.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -76,5 +76,5 @@ return (impl == IMPL_ULTRASPARCIV) || (impl == IMPL_ULTRASPARCIV_PLUS); } - + #endif Index: kernel/arch/sparc64/include/arch/mm/sun4u/mmu.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/sun4u/mmu.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/include/arch/mm/sun4u/mmu.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -111,5 +111,5 @@ unsigned dc : 1; /**< D-Cache enable. */ unsigned ic : 1; /**< I-Cache enable. */ - + } __attribute__ ((packed)); } lsu_cr_reg_t; Index: kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -79,5 +79,5 @@ #define TLB_DBIG_0 2 #define TLB_DBIG_1 3 - + /* I-MMU: one small (16-entry) TLB and one big TLB */ #define TLB_ISMALL 0 @@ -327,5 +327,5 @@ { itlb_data_access_addr_t reg; - + reg.value = 0; reg.tlb_entry = entry; @@ -341,5 +341,5 @@ { itlb_data_access_addr_t reg; - + reg.value = 0; reg.tlb_entry = entry; @@ -358,5 +358,5 @@ { dtlb_data_access_addr_t reg; - + reg.value = 0; reg.tlb_entry = entry; @@ -372,5 +372,5 @@ { dtlb_data_access_addr_t reg; - + reg.value = 0; reg.tlb_entry = entry; @@ -423,5 +423,5 @@ { itlb_data_access_addr_t reg; - + reg.value = 0; reg.tlb_number = tlb; @@ -439,5 +439,5 @@ { itlb_data_access_addr_t reg; - + reg.value = 0; reg.tlb_number = tlb; @@ -458,5 +458,5 @@ { dtlb_data_access_addr_t reg; - + reg.value = 0; reg.tlb_number = tlb; @@ -475,5 +475,5 @@ { dtlb_data_access_addr_t reg; - + reg.value = 0; reg.tlb_number = tlb; @@ -638,12 +638,12 @@ tlb_demap_addr_t da; page_address_t pg; - + da.value = 0; pg.address = page; - + da.type = type; da.context = context_encoding; da.vpn = pg.vpn; - + /* da.value is the address within the ASI */ asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); @@ -664,12 +664,12 @@ tlb_demap_addr_t da; page_address_t pg; - + da.value = 0; pg.address = page; - + da.type = type; da.context = context_encoding; da.vpn = pg.vpn; - + /* da.value is the address within the ASI */ asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); Index: kernel/arch/sparc64/include/arch/mm/sun4v/mmu.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/sun4v/mmu.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/include/arch/mm/sun4v/mmu.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -41,5 +41,5 @@ #define VA_PRIMARY_CONTEXT_REG 0x8 /**< primary context register VA. */ #define ASI_PRIMARY_CONTEXT_REG 0x21 /**< primary context register ASI. */ - + #define VA_SECONDARY_CONTEXT_REG 0x10 /**< secondary context register VA. */ #define ASI_SECONDARY_CONTEXT_REG 0x21 /**< secondary context register ASI. */ Index: kernel/arch/sparc64/include/arch/sun4u/asm.h =================================================================== --- kernel/arch/sparc64/include/arch/sun4u/asm.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/include/arch/sun4u/asm.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -46,10 +46,10 @@ { uint64_t v; - + asm volatile ( "rdpr %%ver, %[v]\n" : [v] "=r" (v) ); - + return v; } Index: kernel/arch/sparc64/include/arch/sun4u/cpu.h =================================================================== --- kernel/arch/sparc64/include/arch/sun4u/cpu.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/include/arch/sun4u/cpu.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -78,5 +78,5 @@ uint64_t icbus_config = asi_u64_read(ASI_ICBUS_CONFIG, 0); icbus_config = icbus_config >> ICBUS_CONFIG_MID_SHIFT; - + #if defined (US) return icbus_config & 0x1f; Index: kernel/arch/sparc64/include/arch/sun4v/hypercall.h =================================================================== --- kernel/arch/sparc64/include/arch/sun4v/hypercall.h (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/include/arch/sun4v/hypercall.h (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -105,5 +105,5 @@ set function_number, %o5; \ ta FAST_TRAP; - + /** * Performs a fast hypervisor API call from the assembly language code. @@ -197,5 +197,5 @@ register uint64_t a4 asm("o3") = p4; register uint64_t a5 asm("o4") = p5; - + asm volatile ( "ta %8\n" @@ -239,5 +239,5 @@ : "memory" ); - + return a1; } Index: kernel/arch/sparc64/src/asm.S =================================================================== --- kernel/arch/sparc64/src/asm.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/asm.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -47,12 +47,12 @@ add %o0, 7, %g1 mov 0, %g3 - + 0: - + brz,pn %o2, 2f mov 0, %g2 - + 1: - + lduba [%g3 + %o1] ASI_AIUS, %g1 add %g2, 1, %g2 @@ -61,12 +61,12 @@ bne,pt %xcc, 1b mov %g2, %g3 - + 2: - + jmp %o7 + 8 /* exit point */ mov %o3, %o0 - + 3: - + and %g1, -8, %g1 cmp %o0, %g1 @@ -76,7 +76,7 @@ brz,pn %g4, 5f mov 0, %g5 - + 4: - + sllx %g3, 3, %g2 add %g5, 1, %g3 @@ -86,7 +86,7 @@ bne,pt %xcc, 4b stx %g1, [%o0 + %g2] - + 5: - + and %o2, 7, %o2 brz,pn %o2, 2b @@ -96,7 +96,7 @@ add %g1, %o1, %g4 mov 0, %g3 - + 6: - + lduba [%g2 + %g4] ASI_AIUS, %g1 stb %g1, [%g2 + %o0] @@ -105,5 +105,5 @@ bne,pt %xcc, 6b mov %g2, %g3 - + jmp %o7 + 8 /* exit point */ mov %o3, %o0 @@ -121,12 +121,12 @@ add %o0, 7, %g1 mov 0, %g3 - + 0: - + brz,pn %o2, 2f mov 0, %g2 - + 1: - + ldub [%g3 + %o1], %g1 add %g2, 1, %g2 @@ -135,12 +135,12 @@ bne,pt %xcc, 1b mov %g2, %g3 - + 2: - + jmp %o7 + 8 /* exit point */ mov %o3, %o0 - + 3: - + and %g1, -8, %g1 cmp %o0, %g1 @@ -150,7 +150,7 @@ brz,pn %g4, 5f mov 0, %g5 - + 4: - + sllx %g3, 3, %g2 add %g5, 1, %g3 @@ -160,7 +160,7 @@ bne,pt %xcc, 4b stxa %g1, [%o0 + %g2] ASI_AIUS - + 5: - + and %o2, 7, %o2 brz,pn %o2, 2b @@ -170,7 +170,7 @@ add %g1, %o1, %g4 mov 0, %g3 - + 6: - + ldub [%g2 + %g4], %g1 stba %g1, [%g2 + %o0] ASI_AIUS @@ -179,5 +179,5 @@ bne,pt %xcc, 6b mov %g2, %g3 - + jmp %o7 + 8 /* exit point */ mov %o3, %o0 Index: kernel/arch/sparc64/src/console.c =================================================================== --- kernel/arch/sparc64/src/console.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/console.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -69,5 +69,5 @@ if (!screen) panic("Cannot find %s.", (char *) prop_scr->value); - + scr_init(screen); #endif @@ -82,5 +82,5 @@ if (!keyboard) panic("Cannot find %s.", (char *) prop_kbd->value); - + kbd_init(keyboard); #endif @@ -95,12 +95,12 @@ ofw_tree_node_t *aliases; ofw_tree_property_t *prop; - + aliases = ofw_tree_lookup("/aliases"); if (!aliases) panic("Cannot find '/aliases'."); - + /* "def-cn" = "default console" */ prop = ofw_tree_getprop(aliases, "def-cn"); - + if ((!prop) || (!prop->value)) standard_console_init(aliases); Index: kernel/arch/sparc64/src/cpu/sun4u/cpu.c =================================================================== --- kernel/arch/sparc64/src/cpu/sun4u/cpu.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/cpu/sun4u/cpu.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -59,5 +59,5 @@ if ((!prop) || (!prop->value)) prop = ofw_tree_getprop(node, "cpuid"); - + if (prop && prop->value) { mid = *((uint32_t *) prop->value); @@ -69,5 +69,5 @@ } } - + return -1; } @@ -80,7 +80,7 @@ ofw_tree_node_t *node; uint32_t clock_frequency = 0; - + CPU->arch.mid = read_mid(); - + /* * Detect processor frequency. @@ -109,5 +109,5 @@ } } - + CPU->arch.clock_frequency = clock_frequency; tick_init(); @@ -146,5 +146,5 @@ break; } - + switch (CPU->arch.ver.impl) { case IMPL_ULTRASPARCI: Index: kernel/arch/sparc64/src/cpu/sun4v/cpu.c =================================================================== --- kernel/arch/sparc64/src/cpu/sun4v/cpu.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/cpu/sun4v/cpu.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -71,5 +71,5 @@ } } - + tick_init(); Index: kernel/arch/sparc64/src/debug/stacktrace.c =================================================================== --- kernel/arch/sparc64/src/debug/stacktrace.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/debug/stacktrace.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -57,5 +57,5 @@ { uintptr_t kstack; - + #if defined(SUN4U) kstack = read_from_ag_g6(); Index: kernel/arch/sparc64/src/drivers/kbd.c =================================================================== --- kernel/arch/sparc64/src/drivers/kbd.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/drivers/kbd.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -62,8 +62,8 @@ { const char *name = ofw_tree_node_name(node); - + if (str_cmp(name, "su") != 0) return false; - + /* * Read 'interrupts' property. @@ -75,7 +75,7 @@ return false; } - + uint32_t interrupts = *((uint32_t *) prop->value); - + /* * Read 'reg' property. @@ -87,7 +87,7 @@ return false; } - + size_t size = ((ofw_ebus_reg_t *) prop->value)->size; - + uintptr_t pa = 0; // Prevent -Werror=maybe-uninitialized if (!ofw_ebus_apply_ranges(node->parent, @@ -97,5 +97,5 @@ return false; } - + inr_t inr; cir_t cir; @@ -108,5 +108,5 @@ return false; } - + /* * We need to pass aligned address to hw_map(). @@ -117,8 +117,8 @@ uintptr_t aligned_addr = ALIGN_DOWN(pa, PAGE_SIZE); size_t offset = pa - aligned_addr; - + ioport8_t *ns16550 = (ioport8_t *) (km_map(aligned_addr, offset + size, PAGE_WRITE | PAGE_NOT_CACHEABLE) + offset); - + ns16550_instance_t *ns16550_instance = ns16550_init(ns16550, 0, inr, cir, cir_arg, NULL); @@ -131,5 +131,5 @@ } } - + /* * This is the necessary evil until the userspace drivers are @@ -140,5 +140,5 @@ sysinfo_set_item_val("kbd.address.physical", NULL, pa); sysinfo_set_item_val("kbd.type.ns16550", NULL, true); - + return true; } Index: kernel/arch/sparc64/src/drivers/niagara.c =================================================================== --- kernel/arch/sparc64/src/drivers/niagara.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/drivers/niagara.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -126,5 +126,5 @@ * shared buffer to the console. */ - + while (output_buffer.read_ptr != output_buffer.write_ptr) { do_putchar(output_buffer.data[output_buffer.read_ptr]); @@ -132,9 +132,9 @@ ((output_buffer.read_ptr) + 1) % OUTPUT_BUFFER_SIZE; } - + /* * Read character from keyboard. */ - + uint64_t c; if (__hypercall_fast_ret1(0, 0, 0, 0, 0, CONS_GETCHAR, &c) == HV_EOK) { @@ -174,9 +174,9 @@ if (instance) return; - + instance = malloc(sizeof(niagara_instance_t), FRAME_ATOMIC); instance->thread = thread_create(kniagarapoll, NULL, TASK, THREAD_FLAG_UNCOUNTED, "kniagarapoll"); - + if (!instance->thread) { free(instance); @@ -184,12 +184,12 @@ return; } - + instance->srlnin = NULL; - + output_buffer.read_ptr = 0; output_buffer.write_ptr = 0; input_buffer.write_ptr = 0; input_buffer.read_ptr = 0; - + /* * Set sysinfos and pareas so that the userspace counterpart of the @@ -197,8 +197,8 @@ * buffers. */ - + sysinfo_set_item_val("fb", NULL, true); sysinfo_set_item_val("fb.kind", NULL, 5); - + sysinfo_set_item_val("niagara.outbuf.address", NULL, KA2PA(&output_buffer)); @@ -207,5 +207,5 @@ sysinfo_set_item_val("niagara.outbuf.datasize", NULL, OUTPUT_BUFFER_SIZE); - + sysinfo_set_item_val("niagara.inbuf.address", NULL, KA2PA(&input_buffer)); @@ -214,5 +214,5 @@ sysinfo_set_item_val("niagara.inbuf.datasize", NULL, INPUT_BUFFER_SIZE); - + outbuf_parea.pbase = (uintptr_t) (KA2PA(&output_buffer)); outbuf_parea.frames = 1; @@ -220,5 +220,5 @@ outbuf_parea.mapped = false; ddi_parea_register(&outbuf_parea); - + inbuf_parea.pbase = (uintptr_t) (KA2PA(&input_buffer)); inbuf_parea.frames = 1; @@ -226,5 +226,5 @@ inbuf_parea.mapped = false; ddi_parea_register(&inbuf_parea); - + outdev_t *niagara_dev = malloc(sizeof(outdev_t), FRAME_ATOMIC); outdev_initialize("niagara_dev", niagara_dev, &niagara_ops); @@ -238,5 +238,5 @@ { niagara_init(); - + if (instance) { srln_instance_t *srln_instance = srln_init(); @@ -244,10 +244,10 @@ indev_t *sink = stdin_wire(); indev_t *srln = srln_wire(srln_instance, sink); - + instance->srlnin = srln; thread_ready(instance->thread); } } - + return instance; } Index: kernel/arch/sparc64/src/drivers/pci.c =================================================================== --- kernel/arch/sparc64/src/drivers/pci.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/drivers/pci.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -183,5 +183,5 @@ if (!prop || !prop->value) return NULL; - + if (str_cmp(prop->value, "SUNW,sabre") == 0) { /* Index: kernel/arch/sparc64/src/drivers/scr.c =================================================================== --- kernel/arch/sparc64/src/drivers/scr.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/drivers/scr.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -67,7 +67,7 @@ ofw_sbus_reg_t *sbus_reg; const char *name; - + name = ofw_tree_node_name(node); - + if (str_cmp(name, "SUNW,m64B") == 0) scr_type = SCR_ATYFB; @@ -80,10 +80,10 @@ else if (str_cmp(name, "QEMU,VGA") == 0) scr_type = SCR_QEMU_VGA; - + if (scr_type == SCR_UNKNOWN) { log(LF_ARCH, LVL_ERROR, "Unknown screen device."); return; } - + uintptr_t fb_addr; unsigned int fb_offset = 0; @@ -121,7 +121,7 @@ return; } - + pci_reg = &((ofw_pci_reg_t *) prop->value)[1]; - + if (!ofw_pci_reg_absolutize(node, pci_reg, &pci_abs_reg)) { log(LF_ARCH, LVL_ERROR, @@ -129,5 +129,5 @@ return; } - + if (!ofw_pci_apply_ranges(node->parent, &pci_abs_reg, &fb_addr)) { @@ -136,5 +136,5 @@ return; } - + switch (fb_depth) { case 8: @@ -159,5 +159,5 @@ return; } - + break; case SCR_XVR: @@ -167,7 +167,7 @@ return; } - + pci_reg = &((ofw_pci_reg_t *) prop->value)[1]; - + if (!ofw_pci_reg_absolutize(node, pci_reg, &pci_abs_reg)) { log(LF_ARCH, LVL_ERROR, @@ -175,5 +175,5 @@ return; } - + if (!ofw_pci_apply_ranges(node->parent, &pci_abs_reg, &fb_addr)) { @@ -207,5 +207,5 @@ return; } - + break; case SCR_FFB: @@ -231,5 +231,5 @@ return; } - + sbus_reg = &((ofw_sbus_reg_t *) prop->value)[0]; if (!ofw_sbus_apply_ranges(node->parent, sbus_reg, &fb_addr)) { @@ -238,5 +238,5 @@ return; } - + break; @@ -297,5 +297,5 @@ .visual = visual, }; - + outdev_t *fbdev = fb_init(&props); if (fbdev) Index: kernel/arch/sparc64/src/drivers/tick.c =================================================================== --- kernel/arch/sparc64/src/drivers/tick.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/drivers/tick.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -89,10 +89,10 @@ softint.value = softint_read(); - + /* * Make sure we are servicing interrupt_level_14 */ assert(n == TT_INTERRUPT_LEVEL_14); - + /* * Make sure we are servicing TICK_INT. @@ -106,5 +106,5 @@ clear.tick_int = 1; clear_softint_write(clear.value); - + /* * Reprogram the compare register. Index: kernel/arch/sparc64/src/fpu_context.c =================================================================== --- kernel/arch/sparc64/src/fpu_context.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/fpu_context.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -67,5 +67,5 @@ * GCC (4.1.1) can't handle more than 30 operands in one asm statement. */ - + asm volatile ( "std %%f32, %0\n" @@ -90,5 +90,5 @@ "=m" (fctx->d[28]), "=m" (fctx->d[29]), "=m" (fctx->d[30]), "=m" (fctx->d[31]) ); - + asm volatile ("stx %%fsr, %0\n" : "=m" (fctx->fsr)); } @@ -119,10 +119,10 @@ "m" (fctx->d[12]), "m" (fctx->d[13]), "m" (fctx->d[14]), "m" (fctx->d[15]) ); - + /* * We need to split loading of the floating-point registers because * GCC (4.1.1) can't handle more than 30 operands in one asm statement. */ - + asm volatile ( "ldd %0, %%f32\n" @@ -148,5 +148,5 @@ "m" (fctx->d[28]), "m" (fctx->d[29]), "m" (fctx->d[30]), "m" (fctx->d[31]) ); - + asm volatile ("ldx %0, %%fsr\n" : : "m" (fctx->fsr)); } @@ -155,5 +155,5 @@ { pstate_reg_t pstate; - + pstate.value = pstate_read(); pstate.pef = true; @@ -164,5 +164,5 @@ { pstate_reg_t pstate; - + pstate.value = pstate_read(); pstate.pef = false; Index: kernel/arch/sparc64/src/mm/sun4u/as.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4u/as.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/mm/sun4u/as.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -69,9 +69,9 @@ tsb_entry_t *tsb = (tsb_entry_t *) PA2KA(tsb_base); memsetb(tsb, TSB_SIZE, 0); - + as->arch.itsb = tsb; as->arch.dtsb = tsb + ITSB_ENTRY_COUNT; #endif - + return EOK; } @@ -81,5 +81,5 @@ #ifdef CONFIG_TSB frame_free(KA2PA((uintptr_t) as->arch.itsb), TSB_FRAMES); - + return TSB_FRAMES; #else @@ -93,5 +93,5 @@ tsb_invalidate(as, 0, (size_t) -1); #endif - + return 0; } @@ -107,5 +107,5 @@ { tlb_context_reg_t ctx; - + /* * Note that we don't and may not lock the address space. That's ok @@ -115,5 +115,5 @@ * */ - + /* * Write ASID to secondary context register. The primary context @@ -126,13 +126,13 @@ ctx.context = as->asid; mmu_secondary_context_write(ctx.v); - + #ifdef CONFIG_TSB uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); - + assert(as->arch.itsb); assert(as->arch.dtsb); - + uintptr_t tsb = (uintptr_t) as->arch.itsb; - + if (!overlaps(tsb, TSB_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { /* @@ -145,5 +145,5 @@ dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true); } - + /* * Setup TSB Base registers. @@ -151,14 +151,14 @@ */ tsb_base_reg_t tsb_base_reg; - + tsb_base_reg.value = 0; tsb_base_reg.size = TSB_BASE_REG_SIZE; tsb_base_reg.split = 0; - + tsb_base_reg.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH; itsb_base_write(tsb_base_reg.value); tsb_base_reg.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH; dtsb_base_write(tsb_base_reg.value); - + #if defined (US3) /* @@ -198,13 +198,13 @@ * */ - + #ifdef CONFIG_TSB uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); - + assert(as->arch.itsb); assert(as->arch.dtsb); - + uintptr_t tsb = (uintptr_t) as->arch.itsb; - + if (!overlaps(tsb, TSB_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { /* Index: kernel/arch/sparc64/src/mm/sun4u/frame.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4u/frame.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/mm/sun4u/frame.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -48,5 +48,5 @@ { unsigned int i; - + for (i = 0; i < memmap.cnt; i++) { uintptr_t base; @@ -62,8 +62,8 @@ size = ALIGN_DOWN(memmap.zones[i].size - (base - ((uintptr_t) memmap.zones[i].start)), FRAME_SIZE); - + if (!frame_adjust_zone_bounds(low, &base, &size)) continue; - + pfn_t confdata; pfn_t pfn = ADDR2PFN(base); @@ -74,5 +74,5 @@ if (confdata == ADDR2PFN(KA2PA(PFN2ADDR(0)))) confdata = ADDR2PFN(KA2PA(PFN2ADDR(2))); - + zone_create(pfn, count, confdata, ZONE_AVAILABLE | ZONE_LOWMEM); @@ -90,7 +90,7 @@ if (config.cpu_active > 1) return; - + frame_common_arch_init(true); - + /* * On sparc64, physical memory can start on a non-zero address. Index: kernel/arch/sparc64/src/mm/sun4u/tlb.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4u/tlb.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/mm/sun4u/tlb.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -178,7 +178,7 @@ tag.context = t->as->asid; tag.vpn = pg.vpn; - + itlb_tag_access_write(tag.value); - + data.value = 0; data.v = true; @@ -190,5 +190,5 @@ data.w = false; data.g = t->g; - + itlb_data_in_write(data.value); } @@ -353,5 +353,5 @@ tlb_data_t d; tlb_tag_read_reg_t t; - + printf("I-TLB contents:\n"); for (i = 0; i < ITLB_ENTRY_COUNT; i++) { @@ -377,5 +377,5 @@ tlb_data_t d; tlb_tag_read_reg_t t; - + printf("TLB_ISMALL contents:\n"); for (i = 0; i < tlb_ismall_size(); i++) { @@ -384,5 +384,5 @@ print_tlb_entry(i, t, d); } - + printf("TLB_IBIG contents:\n"); for (i = 0; i < tlb_ibig_size(); i++) { @@ -391,5 +391,5 @@ print_tlb_entry(i, t, d); } - + printf("TLB_DSMALL contents:\n"); for (i = 0; i < tlb_dsmall_size(); i++) { @@ -398,5 +398,5 @@ print_tlb_entry(i, t, d); } - + printf("TLB_DBIG_1 contents:\n"); for (i = 0; i < tlb_dbig_size(); i++) { @@ -405,5 +405,5 @@ print_tlb_entry(i, t, d); } - + printf("TLB_DBIG_2 contents:\n"); for (i = 0; i < tlb_dbig_size(); i++) { @@ -423,5 +423,5 @@ sfsr.value = dtlb_sfsr_read(); sfar = dtlb_sfar_read(); - + #if defined (US) printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, " @@ -433,7 +433,7 @@ sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv); #endif - + printf("DTLB SFAR: address=%p\n", (void *) sfar); - + dtlb_sfsr_write(0); } @@ -446,5 +446,5 @@ sfsr.value = dtlb_sfsr_read(); sfar = dtlb_sfar_read(); - + #if defined (US) printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, " @@ -456,7 +456,7 @@ sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv); #endif - + printf("DTLB SFAR: address=%p\n", (void *) sfar); - + dtlb_sfsr_write(0); } @@ -467,5 +467,5 @@ { int i; - + /* * Walk all ITLB and DTLB entries and remove all unlocked mappings. @@ -521,17 +521,17 @@ { tlb_context_reg_t pc_save, ctx; - + /* switch to nucleus because we are mapped by the primary context */ nucleus_enter(); - + ctx.v = pc_save.v = mmu_primary_context_read(); ctx.context = asid; mmu_primary_context_write(ctx.v); - + itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_PRIMARY, 0); - + mmu_primary_context_write(pc_save.v); - + nucleus_leave(); } @@ -548,12 +548,12 @@ unsigned int i; tlb_context_reg_t pc_save, ctx; - + /* switch to nucleus because we are mapped by the primary context */ nucleus_enter(); - + ctx.v = pc_save.v = mmu_primary_context_read(); ctx.context = asid; mmu_primary_context_write(ctx.v); - + for (i = 0; i < cnt * MMU_PAGES_PER_PAGE; i++) { itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, @@ -562,7 +562,7 @@ page + i * MMU_PAGE_SIZE); } - + mmu_primary_context_write(pc_save.v); - + nucleus_leave(); } Index: kernel/arch/sparc64/src/mm/sun4u/tsb.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4u/tsb.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/mm/sun4u/tsb.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -57,8 +57,8 @@ size_t i; size_t cnt; - + assert(as->arch.itsb); assert(as->arch.dtsb); - + i0 = (page >> MMU_PAGE_WIDTH) & ITSB_ENTRY_MASK; @@ -67,5 +67,5 @@ else cnt = pages * 2; - + for (i = 0; i < cnt; i++) { as->arch.itsb[(i0 + i) & ITSB_ENTRY_MASK].tag.invalid = true; @@ -86,5 +86,5 @@ assert(index <= 1); - + as = t->as; entry = ((t->page >> MMU_PAGE_WIDTH) + index) & ITSB_ENTRY_MASK; @@ -112,7 +112,7 @@ tte->data.p = t->k; /* p as privileged, k as kernel */ tte->data.v = t->p; /* v as valid, p as present */ - + write_barrier(); - + tte->tag.invalid = false; /* mark the entry as valid */ } @@ -129,5 +129,5 @@ tsb_entry_t *tte; size_t entry; - + assert(index <= 1); @@ -161,7 +161,7 @@ tte->data.w = ro ? false : t->w; tte->data.v = t->p; - + write_barrier(); - + tte->tag.invalid = false; /* mark the entry as valid */ } Index: kernel/arch/sparc64/src/mm/sun4v/as.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4v/as.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/mm/sun4v/as.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -79,8 +79,8 @@ as->arch.tsb_description.reserved = 0; as->arch.tsb_description.context = 0; - + memsetb(tsb, TSB_SIZE, 0); #endif - + return EOK; } @@ -90,5 +90,5 @@ #ifdef CONFIG_TSB frame_free(as->arch.tsb_description.tsb_base, TSB_FRAMES); - + return TSB_FRAMES; #else @@ -102,5 +102,5 @@ tsb_invalidate(as, 0, (size_t) -1); #endif - + return EOK; } @@ -117,11 +117,11 @@ { mmu_secondary_context_write(as->asid); - + #ifdef CONFIG_TSB uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); - + assert(as->arch.tsb_description.tsb_base); uintptr_t tsb = PA2KA(as->arch.tsb_description.tsb_base); - + if (!overlaps(tsb, TSB_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { /* @@ -134,5 +134,5 @@ dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true); } - + __hypercall_fast2(MMU_TSB_CTXNON0, 1, KA2PA(&as->arch.tsb_description)); #endif @@ -156,12 +156,12 @@ * */ - + #ifdef CONFIG_TSB uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); - + assert(as->arch.tsb_description.tsb_base); - + uintptr_t tsb = PA2KA(as->arch.tsb_description.tsb_base); - + if (!overlaps(tsb, TSB_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { /* Index: kernel/arch/sparc64/src/mm/sun4v/frame.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4v/frame.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/mm/sun4v/frame.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -48,5 +48,5 @@ { unsigned int i; - + for (i = 0; i < memmap.cnt; i++) { uintptr_t base; @@ -62,5 +62,5 @@ size = ALIGN_DOWN(memmap.zones[i].size - (base - ((uintptr_t) memmap.zones[i].start)), FRAME_SIZE); - + if (!frame_adjust_zone_bounds(low, &base, &size)) continue; @@ -74,5 +74,5 @@ if (confdata == ADDR2PFN(KA2PA(PFN2ADDR(0)))) confdata = ADDR2PFN(KA2PA(PFN2ADDR(2))); - + zone_create(pfn, count, confdata, ZONE_AVAILABLE | ZONE_LOWMEM); Index: kernel/arch/sparc64/src/mm/sun4v/tlb.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4v/tlb.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/mm/sun4v/tlb.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -128,5 +128,5 @@ { tte_data_t data; - + data.value = 0; data.v = true; @@ -143,5 +143,5 @@ data.w = true; data.size = pagesize; - + if (locked) { __hypercall_fast4( @@ -163,5 +163,5 @@ { tte_data_t data; - + data.value = 0; data.v = true; @@ -178,5 +178,5 @@ data.w = ro ? false : t->w; data.size = PAGESIZE_8K; - + __hypercall_hyperfast( t->page, t->as->asid, data.value, MMU_FLAG_DTLB, 0, MMU_MAP_ADDR); @@ -190,5 +190,5 @@ { tte_data_t data; - + data.value = 0; data.v = true; @@ -203,5 +203,5 @@ data.w = false; data.size = PAGESIZE_8K; - + __hypercall_hyperfast( t->page, t->as->asid, data.value, MMU_FLAG_ITLB, 0, MMU_MAP_ADDR); @@ -387,5 +387,5 @@ { unsigned int i; - + /* switch to nucleus because we are mapped by the primary context */ nucleus_enter(); Index: kernel/arch/sparc64/src/mm/sun4v/tsb.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4v/tsb.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/mm/sun4v/tsb.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -59,7 +59,7 @@ size_t i0, i; size_t cnt; - + assert(as->arch.tsb_description.tsb_base); - + i0 = (page >> MMU_PAGE_WIDTH) & TSB_ENTRY_MASK; @@ -68,5 +68,5 @@ else cnt = pages; - + tsb = (tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base); for (i = 0; i < cnt; i++) @@ -87,5 +87,5 @@ as = t->as; index = (t->page >> MMU_PAGE_WIDTH) & TSB_ENTRY_MASK; - + tsb = (tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base); tte = &tsb[index]; @@ -114,7 +114,7 @@ tte->data.w = false; tte->data.size = PAGESIZE_8K; - + write_barrier(); - + tte->data.v = t->p; /* v as valid, p as present */ } @@ -162,7 +162,7 @@ tte->data.w = ro ? false : t->w; tte->data.size = PAGESIZE_8K; - + write_barrier(); - + tte->data.v = t->p; /* v as valid, p as present */ } Index: kernel/arch/sparc64/src/proc/sun4v/scheduler.c =================================================================== --- kernel/arch/sparc64/src/proc/sun4v/scheduler.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/proc/sun4v/scheduler.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -71,5 +71,5 @@ THREAD->arch.uspace_window_buffer = (uint8_t *) asi_u64_read(ASI_SCRATCHPAD, SCRATCHPAD_WBUF); - + } } Index: kernel/arch/sparc64/src/smp/sun4u/ipi.c =================================================================== --- kernel/arch/sparc64/src/smp/sun4u/ipi.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/smp/sun4u/ipi.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -97,13 +97,13 @@ * we explicitly disable preemption. */ - + preemption_disable(); - + status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0); if (status & INTR_DISPATCH_STATUS_BUSY) panic("Interrupt Dispatch Status busy bit set\n"); - + assert(!(pstate_read() & PSTATE_IE_BIT)); - + do { set_intr_w_data(func); @@ -111,11 +111,11 @@ (mid << INTR_VEC_DISPATCH_MID_SHIFT) | VA_INTR_W_DISPATCH, 0); - + membar(); - + do { status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0); } while (status & INTR_DISPATCH_STATUS_BUSY); - + done = !(status & INTR_DISPATCH_STATUS_NACK); if (!done) { @@ -128,5 +128,5 @@ } } while (!done); - + preemption_enable(); } @@ -147,7 +147,7 @@ { unsigned int i; - + void (* func)(void); - + switch (ipi) { case IPI_TLB_SHOOTDOWN: @@ -158,5 +158,5 @@ break; } - + /* * As long as we don't support hot-plugging @@ -165,5 +165,5 @@ * without locking. */ - + for (i = 0; i < config.cpu_active; i++) { if (&cpus[i] == CPU) @@ -187,5 +187,5 @@ { assert(&cpus[cpu_id] != CPU); - + if (ipi == IPI_SMP_CALL) { cross_call(cpus[cpu_id].arch.mid, smp_call_ipi_recv); Index: kernel/arch/sparc64/src/smp/sun4u/smp.c =================================================================== --- kernel/arch/sparc64/src/smp/sun4u/smp.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/smp/sun4u/smp.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -62,5 +62,5 @@ ofw_tree_node_t *node; unsigned int cnt = 0; - + if (is_us() || is_us_iii()) { node = ofw_tree_find_child_by_device_type(cpus_parent(), "cpu"); @@ -76,5 +76,5 @@ } } - + config.cpu_count = max(1, cnt); } @@ -89,5 +89,5 @@ uint32_t mid; ofw_tree_property_t *prop; - + /* 'upa-portid' for US, 'portid' for US-III, 'cpuid' for US-IV */ prop = ofw_tree_getprop(node, "upa-portid"); @@ -96,8 +96,8 @@ if ((!prop) || (!prop->value)) prop = ofw_tree_getprop(node, "cpuid"); - + if (!prop || prop->value == NULL) return; - + mid = *((uint32_t *) prop->value); if (CPU->arch.mid == mid) @@ -105,5 +105,5 @@ waking_up_mid = mid; - + if (waitq_sleep_timeout(&ap_completion_wq, 1000000, SYNCH_FLAGS_NONE, NULL) == ETIMEOUT) @@ -117,5 +117,5 @@ ofw_tree_node_t *node; int i; - + if (is_us() || is_us_iii()) { node = ofw_tree_find_child_by_device_type(cpus_parent(), "cpu"); Index: kernel/arch/sparc64/src/smp/sun4v/ipi.c =================================================================== --- kernel/arch/sparc64/src/smp/sun4v/ipi.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/smp/sun4v/ipi.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -96,5 +96,5 @@ { void (* func)(void); - + switch (ipi) { case IPI_TLB_SHOOTDOWN: Index: kernel/arch/sparc64/src/smp/sun4v/smp.c =================================================================== --- kernel/arch/sparc64/src/smp/sun4v/smp.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/smp/sun4v/smp.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -359,5 +359,5 @@ if (__hypercall_fast1(CPU_STOP, cpuid) != EOK) return false; - + /* wait for the CPU to stop */ uint64_t state; @@ -365,5 +365,5 @@ while (state == CPU_STATE_RUNNING) __hypercall_fast_ret1(cpuid, 0, 0, 0, 0, CPU_STATE, &state); - + /* make the CPU run again and execute HelenOS code */ if (__hypercall_fast4(CPU_START, cpuid, @@ -372,10 +372,10 @@ return false; #endif - + if (waitq_sleep_timeout(&ap_completion_wq, 10000000, SYNCH_FLAGS_NONE, NULL) == ETIMEOUT) printf("%s: waiting for processor (cpuid = %" PRIu64 ") timed out\n", __func__, cpuid); - + return true; } Index: kernel/arch/sparc64/src/sparc64.c =================================================================== --- kernel/arch/sparc64/src/sparc64.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/sparc64.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -79,5 +79,5 @@ if (options) { ofw_tree_property_t *prop; - + prop = ofw_tree_getprop(options, "boot-args"); if (prop && prop->value) { Index: kernel/arch/sparc64/src/sun4u/asm.S =================================================================== --- kernel/arch/sparc64/src/sun4u/asm.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/sun4u/asm.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -102,5 +102,5 @@ wrpr %g1, TSTATE_IE_BIT, %tstate wrpr %i0, 0, %tnpc - + /* * Set primary context according to secondary context. @@ -117,5 +117,5 @@ */ wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(1), %wstate - + done ! jump to userspace FUNCTION_END(switch_to_userspace) Index: kernel/arch/sparc64/src/sun4u/sparc64.c =================================================================== --- kernel/arch/sparc64/src/sun4u/sparc64.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/sun4u/sparc64.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -72,5 +72,5 @@ /* Copy init task info. */ init.cnt = min3(bootinfo->taskmap.cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS); - + size_t i; for (i = 0; i < init.cnt; i++) { @@ -80,5 +80,5 @@ bootinfo->taskmap.tasks[i].name); } - + /* Copy physical memory map. */ memmap.total = bootinfo->memmap.total; @@ -88,9 +88,9 @@ memmap.zones[i].size = bootinfo->memmap.zones[i].size; } - + /* Copy boot allocations info. */ ballocs.base = bootinfo->ballocs.base; ballocs.size = bootinfo->ballocs.size; - + ofw_tree_init(bootinfo->ofw_root); } @@ -111,5 +111,5 @@ /* Map OFW information into sysinfo */ ofw_sysinfo_map(); - + /* * We have 2^11 different interrupt vectors. @@ -167,5 +167,5 @@ (ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT) + STACK_BIAS), (uintptr_t) kernel_uarg->uspace_uarg); - + /* Not reached */ while (1); Index: kernel/arch/sparc64/src/sun4u/start.S =================================================================== --- kernel/arch/sparc64/src/sun4u/start.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/sun4u/start.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -85,5 +85,5 @@ ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base. srlx %l6, 13, %l5 - + ! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13] sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5 @@ -101,5 +101,5 @@ wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window ! traps for kernel - + wrpr %g0, 0, %wstate ! use default spill/fill trap @@ -132,5 +132,5 @@ set (TLB_DEMAP_CONTEXT << TLB_DEMAP_TYPE_SHIFT) | (context_id << \ TLB_DEMAP_CONTEXT_SHIFT), %r1 - + ! demap context 0 SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) @@ -161,5 +161,5 @@ sllx %r2, TTE_V_SHIFT, %r2; \ or %r1, %r2, %r1; - + ! write DTLB data and install the kernel mapping SET_TLB_DATA(g1, g2, TTE_L | TTE_W) ! use non-global mapping @@ -182,5 +182,5 @@ stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG membar #Sync - + /* * Now is time to take over the IMMU. Unfortunatelly, it cannot be done @@ -202,7 +202,7 @@ * the taken over DTLB. */ - + set kernel_image_start, %g5 - + ! write ITLB tag of context 1 SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) @@ -215,15 +215,15 @@ stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG flush %g5 - + ! switch to context 1 mov MEM_CONTEXT_TEMP, %g1 stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! flush %g5 - + ! demap context 0 SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) stxa %g0, [%g1] ASI_IMMU_DEMAP flush %g5 - + ! write ITLB tag of context 0 SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) @@ -244,9 +244,9 @@ stxa %g0, [%g1] ASI_IMMU_DEMAP flush %g5 - + ! set context 0 in the primary context register stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! flush %g5 - + ! leave nucleus - using primary context, i.e. context 0 wrpr %g0, 0, %tl @@ -271,9 +271,9 @@ or %l3, %l5, %l3 stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)] - + ! flush the whole D-cache set (DCACHE_SIZE - DCACHE_LINE_SIZE), %g1 stxa %g0, [%g1] ASI_DCACHE_TAG - + 0: membar #Sync @@ -282,5 +282,5 @@ stxa %g0, [%g1] ASI_DCACHE_TAG membar #Sync - + /* * So far, we have not touched the stack. @@ -290,5 +290,5 @@ or %sp, %lo(temporary_boot_stack), %sp sub %sp, STACK_BIAS, %sp - + /* * Call sparc64_pre_main(bootinfo) @@ -296,5 +296,5 @@ call sparc64_pre_main mov %o1, %o0 - + /* * Create the first stack frame. @@ -372,5 +372,5 @@ /* Not reached. */ #endif - + 0: ba,a %xcc, 0b Index: kernel/arch/sparc64/src/sun4v/asm.S =================================================================== --- kernel/arch/sparc64/src/sun4v/asm.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/sun4v/asm.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -58,5 +58,5 @@ wrpr %g1, TSTATE_IE_BIT, %tstate wrpr %i0, 0, %tnpc - + /* * Set primary context according to secondary context. Index: kernel/arch/sparc64/src/sun4v/md.c =================================================================== --- kernel/arch/sparc64/src/sun4v/md.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/sun4v/md.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -244,5 +244,5 @@ char *head; more = str_parse_head(&name, &head); - + while (md_next_child(&node)) { element_idx_t child = md_get_child_node(node); @@ -292,5 +292,5 @@ return true; } - + (*node)++; } while (element->tag != LIST_END); Index: kernel/arch/sparc64/src/sun4v/sparc64.c =================================================================== --- kernel/arch/sparc64/src/sun4v/sparc64.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/sun4v/sparc64.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -74,5 +74,5 @@ /* Copy init task info. */ init.cnt = min3(bootinfo->taskmap.cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS); - + size_t i; for (i = 0; i < init.cnt; i++) { @@ -82,5 +82,5 @@ bootinfo->taskmap.tasks[i].name); } - + /* Copy physical memory map. */ memmap.total = bootinfo->memmap.total; @@ -90,5 +90,5 @@ memmap.zones[i].size = bootinfo->memmap.zones[i].size; } - + md_init(); } @@ -109,5 +109,5 @@ /* Map OFW information into sysinfo */ ofw_sysinfo_map(); - + /* * We have 2^11 different interrupt vectors. @@ -165,5 +165,5 @@ (ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT) + STACK_BIAS), (uintptr_t) kernel_uarg->uspace_uarg); - + /* Not reached */ while (1); Index: kernel/arch/sparc64/src/sun4v/start.S =================================================================== --- kernel/arch/sparc64/src/sun4v/start.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/sun4v/start.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -115,5 +115,5 @@ ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base. srlx %l6, 13, %l5 - + ! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13] sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5 @@ -130,5 +130,5 @@ wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window ! traps for kernel - + wrpr %g0, 0, %wstate ! use default spill/fill trap @@ -252,5 +252,5 @@ call sparc64_pre_main or %l1, %g0, %o0 - + /* * Create the first stack frame. Index: kernel/arch/sparc64/src/trap/exception.c =================================================================== --- kernel/arch/sparc64/src/trap/exception.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/trap/exception.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -48,5 +48,5 @@ const char *tpcs = symtab_fmt_name_lookup(istate->tpc); const char *tnpcs = symtab_fmt_name_lookup(istate->tnpc); - + printf("TSTATE=%#" PRIx64 "\n", istate->tstate); printf("TPC=%#" PRIx64 " (%s)\n", istate->tpc, tpcs); @@ -100,5 +100,5 @@ { fprs_reg_t fprs; - + fprs.value = fprs_read(); if (!fprs.fef) { Index: kernel/arch/sparc64/src/trap/sun4u/interrupt.c =================================================================== --- kernel/arch/sparc64/src/trap/sun4u/interrupt.c (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/trap/sun4u/interrupt.c (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -58,5 +58,5 @@ if (status & (!INTR_DISPATCH_STATUS_BUSY)) panic("Interrupt Dispatch Status busy bit not set\n"); - + uint64_t intrcv = asi_u64_read(ASI_INTR_RECEIVE, 0); #if defined (US) @@ -65,5 +65,5 @@ uint64_t data0 = asi_u64_read(ASI_INTR_R, VA_INTR_R_DATA_0); #endif - + irq_t *irq = irq_dispatch_and_lock(data0); if (irq) { @@ -72,5 +72,5 @@ */ irq->handler(irq); - + /* * See if there is a clear-interrupt-routine and call it. @@ -78,5 +78,5 @@ if (irq->cir) irq->cir(irq->cir_arg, irq->inr); - + irq_spinlock_unlock(&irq->lock, false); } else if (data0 > config.base) { @@ -103,5 +103,5 @@ #endif } - + membar(); asi_u64_write(ASI_INTR_RECEIVE, 0, 0); Index: kernel/arch/sparc64/src/trap/sun4u/trap_table.S =================================================================== --- kernel/arch/sparc64/src/trap/sun4u/trap_table.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/trap/sun4u/trap_table.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -502,5 +502,5 @@ .if NOT(\is_syscall) rdpr %tstate, %g3 - + /* * One of the ways this handler can be invoked is after a nested MMU trap from @@ -576,5 +576,5 @@ */ wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(0), %wstate - + /* * Copy arguments. @@ -605,9 +605,9 @@ */ stx %g4, [%sp + STACK_BIAS + ISTATE_OFFSET_Y] - + wrpr %g0, 0, %tl wrpr %g0, PSTATE_PRIV_BIT | PSTATE_PEF_BIT, %pstate SAVE_GLOBALS - + .if NOT(\is_syscall) /* @@ -629,5 +629,5 @@ wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate wrpr %g0, 1, %tl - + /* * Read TSTATE, TPC and TNPC from saved copy. @@ -742,5 +742,5 @@ rd %pc, %g1 flush %g1 - + rdpr %cwp, %g1 rdpr %otherwin, %g2 @@ -800,5 +800,5 @@ mov NWINDOWS - 2, %g1 ! use dealy slot for both cases sub %g1, %g2, %g1 - + wrpr %g0, 0, %otherwin wrpr %g1, 0, %cansave ! NWINDOWS - 2 - CANRESTORE @@ -845,5 +845,5 @@ and %g1, NWINDOWS - 1, %g1 wrpr %g1, 0, %cwp ! CWP-- - + .if \is_syscall done Index: kernel/arch/sparc64/src/trap/sun4v/trap_table.S =================================================================== --- kernel/arch/sparc64/src/trap/sun4v/trap_table.S (revision 3061bc129a855122d429fbba1e623a521aaa164c) +++ kernel/arch/sparc64/src/trap/sun4v/trap_table.S (revision a35b458e9db1ca95e679799dc7c1b12c83359ca3) @@ -606,5 +606,5 @@ and \tmpreg1, NWINDOWS - 1, \tmpreg1 ! modulo NWINDOWS wrpr \tmpreg1, %cwp - + ! spill to kernel stack stx %l0, [%sp + STACK_BIAS + L0_OFFSET] @@ -766,5 +766,5 @@ ldx [%sp + STACK_BIAS + ISTATE_OFFSET_Y], %g4 wr %g4, %y - + /* If TSTATE.CWP + 1 == CWP, then we do not have to fix CWP. */ and %g1, TSTATE_CWP_MASK, %l0 @@ -871,5 +871,5 @@ and \tmpreg1, NWINDOWS - 1, \tmpreg1 ! modulo NWINDOWS wrpr \tmpreg1, %cwp - + ! spill to userspace window buffer SAVE_TO_USPACE_WBUF \tmpreg3, \tmpreg1 @@ -1028,5 +1028,5 @@ mov NWINDOWS - 2, %g1 ! use dealy slot for both cases sub %g1, %g2, %g1 - + wrpr %g0, 0, %otherwin wrpr %g1, 0, %cansave ! NWINDOWS - 2 - CANRESTORE @@ -1073,5 +1073,5 @@ and %g1, NWINDOWS - 1, %g1 wrpr %g1, 0, %cwp ! CWP-- - + .if \is_syscall done