Index: kernel/arch/ia64/include/arch/asm.h
===================================================================
--- kernel/arch/ia64/include/arch/asm.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/include/arch/asm.h	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -51,5 +51,5 @@
 	return legacyio_virt_base + (((prt >> 2) << 12) | (prt & 0xfff));
 }
-	
+
 NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
 {
@@ -58,5 +58,5 @@
 	else
 		*port = v;
-	
+
 	asm volatile (
 		"mf\n"
@@ -72,5 +72,5 @@
 	else
 		*port = v;
-	
+
 	asm volatile (
 		"mf\n"
@@ -86,5 +86,5 @@
 	else
 		*port = v;
-	
+
 	asm volatile (
 		"mf\n"
@@ -112,5 +112,5 @@
 		::: "memory"
 	);
-	
+
 	return v;
 }
@@ -134,5 +134,5 @@
 		::: "memory"
 	);
-	
+
 	return v;
 }
@@ -141,10 +141,10 @@
 {
 	uint32_t v;
-	
-	asm volatile (
-		"mf\n"
-		::: "memory"
-	);
-	
+
+	asm volatile (
+		"mf\n"
+		::: "memory"
+	);
+
 	if (port < (ioport32_t *) IO_SPACE_BOUNDARY)
 		v = *((ioport32_t *) p2a(port));
@@ -169,10 +169,10 @@
 {
 	uint64_t value;
-	
+
 	asm volatile (
 		"mov %[value] = r12"
 		: [value] "=r" (value)
 	);
-	
+
 	return (value & (~(STACK_SIZE / 2 - 1)));
 }
@@ -186,10 +186,10 @@
 {
 	uint64_t v;
-	
+
 	asm volatile (
 		"mov %[value] = psr\n"
 		: [value] "=r" (v)
 	);
-	
+
 	return v;
 }
@@ -203,10 +203,10 @@
 {
 	uint64_t v;
-	
+
 	asm volatile (
 		"mov %[value] = cr.iva\n"
 		: [value] "=r" (v)
 	);
-	
+
 	return v;
 }
@@ -234,10 +234,10 @@
 {
 	uint64_t v;
-	
+
 	asm volatile (
 		"mov %[value] = cr.ivr\n"
 		: [value] "=r" (v)
 	);
-	
+
 	return v;
 }
@@ -246,10 +246,10 @@
 {
 	uint64_t v;
-	
+
 	asm volatile (
 		"mov %[value] = cr64\n"
 		: [value] "=r" (v)
 	);
-	
+
 	return v;
 }
@@ -276,10 +276,10 @@
 {
 	uint64_t v;
-	
+
 	asm volatile (
 		"mov %[value] = ar.itc\n"
 		: [value] "=r" (v)
 	);
-	
+
 	return v;
 }
@@ -306,10 +306,10 @@
 {
 	uint64_t v;
-	
+
 	asm volatile (
 		"mov %[value] = cr.itm\n"
 		: [value] "=r" (v)
 	);
-	
+
 	return v;
 }
@@ -323,10 +323,10 @@
 {
 	uint64_t v;
-	
+
 	asm volatile (
 		"mov %[value] = cr.itv\n"
 		: [value] "=r" (v)
 	);
-	
+
 	return v;
 }
@@ -366,10 +366,10 @@
 {
 	uint64_t v;
-	
+
 	asm volatile (
 		"mov %[value] = cr.tpr\n"
 		: [value] "=r" (v)
 	);
-	
+
 	return v;
 }
@@ -399,5 +399,5 @@
 {
 	uint64_t v;
-	
+
 	asm volatile (
 		"mov %[value] = psr\n"
@@ -406,5 +406,5 @@
 		: [mask] "i" (PSR_I_MASK)
 	);
-	
+
 	return (ipl_t) v;
 }
@@ -421,5 +421,5 @@
 {
 	uint64_t v;
-	
+
 	asm volatile (
 		"mov %[value] = psr\n"
@@ -430,5 +430,5 @@
 		: [mask] "i" (PSR_I_MASK)
 	);
-	
+
 	return (ipl_t) v;
 }
Index: kernel/arch/ia64/include/arch/atomic.h
===================================================================
--- kernel/arch/ia64/include/arch/atomic.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/include/arch/atomic.h	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -41,5 +41,5 @@
 {
 	atomic_count_t v;
-	
+
 	asm volatile (
 		"movl %[v] = 0x1;;\n"
@@ -48,5 +48,5 @@
 		  [count] "+m" (val->count)
 	);
-	
+
 	return v;
 }
@@ -62,5 +62,5 @@
 {
 	atomic_count_t v;
-	
+
 	asm volatile (
 		"fetchadd8.rel %[v] = %[count], 1\n"
@@ -73,5 +73,5 @@
 {
 	atomic_count_t v;
-	
+
 	asm volatile (
 		"fetchadd8.rel %[v] = %[count], -1\n"
@@ -84,5 +84,5 @@
 {
 	atomic_count_t v;
-	
+
 	asm volatile (
 		"fetchadd8.rel %[v] = %[count], 1\n"
@@ -90,5 +90,5 @@
 		  [count] "+m" (val->count)
 	);
-	
+
 	return (v + 1);
 }
@@ -97,5 +97,5 @@
 {
 	atomic_count_t v;
-	
+
 	asm volatile (
 		"fetchadd8.rel %[v] = %[count], -1\n"
@@ -103,5 +103,5 @@
 		  [count] "+m" (val->count)
 	);
-	
+
 	return (v - 1);
 }
@@ -110,5 +110,5 @@
 {
 	atomic_count_t v;
-	
+
 	asm volatile (
 		"fetchadd8.rel %[v] = %[count], 1\n"
@@ -116,5 +116,5 @@
 		  [count] "+m" (val->count)
 	);
-	
+
 	return v;
 }
@@ -123,5 +123,5 @@
 {
 	atomic_count_t v;
-	
+
 	asm volatile (
 		"fetchadd8.rel %[v] = %[count], -1\n"
@@ -129,5 +129,5 @@
 		  [count] "+m" (val->count)
 	);
-	
+
 	return v;
 }
Index: kernel/arch/ia64/include/arch/bootinfo.h
===================================================================
--- kernel/arch/ia64/include/arch/bootinfo.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/include/arch/bootinfo.h	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -44,5 +44,5 @@
 	char name[BOOTINFO_TASK_NAME_BUFLEN];
 } binit_task_t;
-	
+
 typedef struct {
 	size_t cnt;
@@ -58,8 +58,8 @@
 typedef struct {
 	binit_t taskmap;
-	
+
 	memmap_item_t memmap[MEMMAP_ITEMS];
 	unsigned int memmap_items;
-	
+
 	sysarg_t *sapic;
 	unsigned long sys_freq;
Index: kernel/arch/ia64/include/arch/cpu.h
===================================================================
--- kernel/arch/ia64/include/arch/cpu.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/include/arch/cpu.h	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -66,5 +66,5 @@
 {
 	uint64_t v;
-	
+
 	asm volatile (
 		"mov %[v] = cpuid[%[r]]\n"
@@ -72,5 +72,5 @@
 		: [r] "r" (n)
 	);
-	
+
 	return v;
 }
Index: kernel/arch/ia64/include/arch/istate.h
===================================================================
--- kernel/arch/ia64/include/arch/istate.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/include/arch/istate.h	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -65,5 +65,5 @@
 {
 	/* FIXME */
-	
+
 	return 0;
 }
Index: kernel/arch/ia64/include/arch/mm/page.h
===================================================================
--- kernel/arch/ia64/include/arch/mm/page.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/include/arch/mm/page.h	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -117,5 +117,5 @@
 	unsigned int ed : 1;
 	unsigned int ig1 : 11;
-	
+
 	/* Word 1 */
 	unsigned int : 2;
@@ -123,8 +123,8 @@
 	unsigned int key : 24;
 	unsigned int : 32;
-	
+
 	/* Word 2 */
 	union vhpt_tag tag;
-	
+
 	/* Word 3 */
 	uint64_t ig3 : 64;
@@ -136,13 +136,13 @@
 	unsigned long long ig0 : 52;
 	unsigned int ig1 : 11;
-	
+
 	/* Word 1 */
 	unsigned int : 2;
 	unsigned int ps : 6;
 	unsigned long long ig2 : 56;
-	
+
 	/* Word 2 */
 	union vhpt_tag tag;
-	
+
 	/* Word 3 */
 	uint64_t ig3 : 64;
@@ -194,5 +194,5 @@
 {
 	uint64_t ret;
-	
+
 	asm volatile (
 		"thash %[ret] = %[va]\n"
@@ -200,5 +200,5 @@
 		: [va] "r" (va)
 	);
-	
+
 	return ret;
 }
@@ -216,5 +216,5 @@
 {
 	uint64_t ret;
-	
+
 	asm volatile (
 		"ttag %[ret] = %[va]\n"
@@ -222,5 +222,5 @@
 		: [va] "r" (va)
 	);
-	
+
 	return ret;
 }
@@ -235,7 +235,7 @@
 {
 	uint64_t ret;
-	
+
 	assert(i < REGION_REGISTERS);
-	
+
 	asm volatile (
 		"mov %[ret] = rr[%[index]]\n"
@@ -243,5 +243,5 @@
 		: [index] "r" (i << VRN_SHIFT)
 	);
-	
+
 	return ret;
 }
@@ -255,5 +255,5 @@
 {
 	assert(i < REGION_REGISTERS);
-	
+
 	asm volatile (
 		"mov rr[%[index]] = %[value]\n"
@@ -270,10 +270,10 @@
 {
 	uint64_t ret;
-	
+
 	asm volatile (
 		"mov %[ret] = cr.pta\n"
 		: [ret] "=r" (ret)
 	);
-	
+
 	return ret;
 }
Index: kernel/arch/ia64/include/arch/mm/tlb.h
===================================================================
--- kernel/arch/ia64/include/arch/mm/tlb.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/include/arch/mm/tlb.h	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -63,5 +63,5 @@
 		unsigned int ed : 1;
 		unsigned int ig1 : 11;
-		
+
 		/* Word 1 */
 		unsigned int : 2;
Index: kernel/arch/ia64/include/arch/mm/vhpt.h
===================================================================
--- kernel/arch/ia64/include/arch/mm/vhpt.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/include/arch/mm/vhpt.h	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -32,5 +32,5 @@
 /** @file
 */
-												
+
 #ifndef KERN_ia64_VHPT_H_
 #define KERN_ia64_VHPT_H_
@@ -44,8 +44,8 @@
 {
 	vhpt_entry_t ventry;
-	
+
 	ventry.word[0] = tentry.word[0];
 	ventry.word[1] = tentry.word[1];
-	
+
 	return ventry;
 }
Index: kernel/arch/ia64/src/asm.S
===================================================================
--- kernel/arch/ia64/src/asm.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/src/asm.S	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -46,5 +46,5 @@
 FUNCTION_BEGIN(memcpy_to_uspace)
 	alloc loc0 = ar.pfs, 3, 1, 0, 0
-	
+
 	adds r14 = 7, in1
 	mov r2 = ar.lc
@@ -53,7 +53,7 @@
 	cmp.ne p6, p7 = r14, in1
 	(p7) br.cond.dpnt 3f ;;
-	
+
 	0:
-	
+
 		cmp.ne p6, p7 = 0, in2
 		(p7) br.cond.dpnt 2f ;;
@@ -62,7 +62,7 @@
 		(p6) mov r17 = r0 ;;
 		(p6) mov ar.lc = r14
-	
+
 	1:
-	
+
 		add r14 = r16, in1
 		add r15 = r16, in0
@@ -72,13 +72,13 @@
 		st1 [r15] = r14
 		br.cloop.sptk.few 1b ;;
-	
+
 	2:
-	
+
 		mov ar.lc = r2
 		mov ar.pfs = loc0
 		br.ret.sptk.many rp
-	
+
 	3:
-	
+
 		adds r14 = 7, in0 ;;
 		and r14 = -8, r14 ;;
@@ -92,7 +92,7 @@
 		(p6) mov r17 = r0 ;;
 		(p6) mov ar.lc = r14
-	
+
 	4:
-	
+
 		shladd r14 = r16, 3, r0
 		adds r16 = 1, r17 ;;
@@ -103,7 +103,7 @@
 		st8 [r14] = r15
 		br.cloop.sptk.few 4b
-	
+
 	5:
-	
+
 		and r15 = 7, in2
 		shladd r14 = r18, 3, r0
@@ -116,7 +116,7 @@
 		(p6) br.cond.dpnt 2b ;;
 		mov ar.lc = r15
-	
+
 	6:
-	
+
 		add r14 = r16, r17
 		add r15 = r16, in0
@@ -155,37 +155,37 @@
 FUNCTION_BEGIN(switch_to_userspace)
 	alloc loc0 = ar.pfs, 6, 3, 0, 0
-	
+
 	/* Disable interruption collection and interrupts */
 	rsm (PSR_IC_MASK | PSR_I_MASK)
 	srlz.d ;;
 	srlz.i ;;
-	
+
 	mov cr.ipsr = in4
 	mov cr.iip = in0
 	mov r12 = in1
-	
+
 	xor r1 = r1, r1
-	
+
 	/* r2 is defined to hold pcb_ptr - set it to 0 */
 	xor r2 = r2, r2
-	
+
 	mov loc1 = cr.ifs
 	movl loc2 = PFM_MASK ;;
 	and loc1 = loc2, loc1 ;;
 	mov cr.ifs = loc1 ;;  /* prevent decrementing BSP by rfi */
-	
+
 	invala
-	
+
 	mov loc1 = ar.rsc ;;
 	and loc1 = ~3, loc1 ;;
 	mov ar.rsc = loc1 ;;  /* put RSE into enforced lazy mode */
-	
+
 	flushrs ;;
-	
+
 	mov ar.bspstore = in2 ;;
 	mov ar.rsc = in5 ;;
-	
+
 	mov r8 = in3
-	
+
 	rfi ;;
 FUNCTION_END(switch_to_userspace)
Index: kernel/arch/ia64/src/context.S
===================================================================
--- kernel/arch/ia64/src/context.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/src/context.S	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -45,5 +45,5 @@
 	flushrs
 	mov loc4 = ar.bsp
-	
+
 	/*
 	 * Put RSE to enforced lazy mode.
@@ -117,5 +117,5 @@
 
 	mov loc2 = ar.unat
-	
+
 	/*
 	 * Save application registers
@@ -177,5 +177,5 @@
 
 	mov ar.unat = loc1
-	
+
 	add r8 = r0, r0, 1 	/* context_save returns 1 */
 	br.ret.sptk.many b0
@@ -239,5 +239,5 @@
 	ld8 loc5 = [loc14]	/* load ar.rnat */
 	ld8 loc6 = [loc15]	/* load ar.lc */
-	
+
 	.auto
 
@@ -274,5 +274,5 @@
 	mov ar.unat = loc2 ;;
 	mov ar.lc = loc6
-	
+
 	/*
 	 * Restore general registers including NaT bits
@@ -332,7 +332,7 @@
 	ldf.fill f30 = [loc48]
 	ldf.fill f31 = [loc49]
-	
+
 	mov ar.unat = loc1
-	
+
 	mov r8 = r0			/* context_restore returns 0 */
 	br.ret.sptk.many b0
Index: kernel/arch/ia64/src/cpu/cpu.c
===================================================================
--- kernel/arch/ia64/src/cpu/cpu.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/src/cpu/cpu.c	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -54,9 +54,9 @@
 	const char *family_str;
 	char vendor[2 * sizeof(uint64_t) + 1];
-	
+
 	memcpy(vendor, &CPU->arch.cpuid0, 8);
 	memcpy(vendor + 8, &CPU->arch.cpuid1, 8);
 	vendor[sizeof(vendor) - 1] = 0;
-	
+
 	switch (m->arch.cpuid3.family) {
 	case FAMILY_ITANIUM:
@@ -70,5 +70,5 @@
 		break;
 	}
-	
+
 	printf("cpu%d: %s (%s), archrev=%d, model=%d, revision=%d\n", CPU->id,
 	    family_str, vendor, CPU->arch.cpuid3.archrev,
Index: kernel/arch/ia64/src/ddi/ddi.c
===================================================================
--- kernel/arch/ia64/src/ddi/ddi.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/src/ddi/ddi.c	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -59,17 +59,17 @@
 		if (task->arch.iomap == NULL)
 			return ENOMEM;
-		
+
 		void *store = malloc(bitmap_size(IO_MEMMAP_PAGES), 0);
 		if (store == NULL)
 			return ENOMEM;
-		
+
 		bitmap_initialize(task->arch.iomap, IO_MEMMAP_PAGES, store);
 		bitmap_clear_range(task->arch.iomap, 0, IO_MEMMAP_PAGES);
 	}
-	
+
 	uintptr_t iopage = ioaddr / PORTS_PER_PAGE;
 	size = ALIGN_UP(size + ioaddr - 4 * iopage, PORTS_PER_PAGE);
 	bitmap_set_range(task->arch.iomap, iopage, size / 4);
-	
+
 	return EOK;
 }
@@ -93,5 +93,5 @@
 	size = ALIGN_UP(size + ioaddr - 4 * iopage, PORTS_PER_PAGE);
 	bitmap_clear_range(task->arch.iomap, iopage, size / 4);
-	
+
 	return EOK;
 }
Index: kernel/arch/ia64/src/drivers/it.c
===================================================================
--- kernel/arch/ia64/src/drivers/it.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/src/drivers/it.c	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -68,5 +68,5 @@
 		it_irq.handler = it_interrupt;
 		irq_register(&it_irq);
-		
+
 		uint64_t base_freq;
 		base_freq  = ((bootinfo->freq_scale) & FREQ_NUMERATOR_MASK) >>
@@ -75,22 +75,22 @@
 		base_freq /= ((bootinfo->freq_scale) & FREQ_DENOMINATOR_MASK) >>
 		    FREQ_DENOMINATOR_SHIFT;
-		
+
 		it_delta = base_freq / HZ;
 	}
-	
+
 	/* Initialize Interval Timer external interrupt vector */
 	cr_itv_t itv;
-	
+
 	itv.value = itv_read();
 	itv.vector = INTERRUPT_TIMER;
 	itv.m = 0;
 	itv_write(itv.value);
-	
+
 	/* Set Interval Timer Counter to zero */
 	itc_write(0);
-	
+
 	/* Generate first Interval Timer interrupt in IT_DELTA ticks */
 	itm_write(IT_DELTA);
-	
+
 	/* Propagate changes */
 	srlz_d();
@@ -113,11 +113,11 @@
 {
 	eoi_write(EOI);
-	
+
 	int64_t itm = itm_read();
-	
+
 	while (true) {
 		int64_t itc = itc_read();
 		itc += IT_SERVICE_CLOCKS;
-		
+
 		itm += IT_DELTA;
 		if (itm - itc < 0)
@@ -126,8 +126,8 @@
 			break;
 	}
-	
+
 	itm_write(itm);
 	srlz_d();  /* Propagate changes */
-	
+
 	/*
 	 * We are holding a lock which prevents preemption.
Index: kernel/arch/ia64/src/drivers/ski.c
===================================================================
--- kernel/arch/ia64/src/drivers/ski.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/src/drivers/ski.c	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -49,8 +49,8 @@
 	/** Interval between polling in microseconds */
 	POLL_INTERVAL = 10000,  /* 0.01 s */
-	
+
 	/** Max. number of characters to pull out at a time */
 	POLL_LIMIT = 30,
-	
+
 	SKI_INIT_CONSOLE = 20,
 	SKI_GETCHAR      = 21,
@@ -82,15 +82,15 @@
 {
 	uint64_t ch;
-	
+
 	asm volatile (
 		"mov r15 = %1\n"
 		"break 0x80000;;\n"  /* modifies r8 */
 		"mov %0 = r8;;\n"
-		
+
 		: "=r" (ch)
 		: "i" (SKI_GETCHAR)
 		: "r15", "r8"
 	);
-	
+
 	return (wchar_t) ch;
 }
@@ -103,11 +103,11 @@
 {
 	int count = POLL_LIMIT;
-	
+
 	while (count > 0) {
 		wchar_t ch = ski_getchar();
-		
+
 		if (ch == '\0')
 			break;
-		
+
 		indev_push_character(instance->srlnin, ch);
 		--count;
@@ -119,5 +119,5 @@
 {
 	ski_instance_t *instance = (ski_instance_t *) arg;
-	
+
 	while (true) {
 		// TODO FIXME:
@@ -126,5 +126,5 @@
 		if (console_override)
 			poll_keyboard(instance);
-		
+
 		thread_usleep(POLL_INTERVAL);
 	}
@@ -141,5 +141,5 @@
 	if (instance)
 		return;
-	
+
 	asm volatile (
 		"mov r15 = %0\n"
@@ -149,11 +149,11 @@
 		: "r15", "r8"
 	);
-	
+
 	instance = malloc(sizeof(ski_instance_t), FRAME_ATOMIC);
-	
+
 	if (instance) {
 		instance->thread = thread_create(kskipoll, instance, TASK,
 		    THREAD_FLAG_UNCOUNTED, "kskipoll");
-		
+
 		if (!instance->thread) {
 			free(instance);
@@ -161,5 +161,5 @@
 			return;
 		}
-		
+
 		instance->srlnin = NULL;
 	}
@@ -196,5 +196,5 @@
 			if (ch == '\n')
 				ski_do_putchar('\r');
-			
+
 			ski_do_putchar(ch);
 		} else
@@ -208,12 +208,12 @@
 	if (!instance)
 		return NULL;
-	
+
 	outdev_t *skidev = malloc(sizeof(outdev_t), FRAME_ATOMIC);
 	if (!skidev)
 		return NULL;
-	
+
 	outdev_initialize("skidev", skidev, &skidev_ops);
 	skidev->data = instance;
-	
+
 	if (!fb_exported) {
 		/*
@@ -224,8 +224,8 @@
 		sysinfo_set_item_val("fb", NULL, true);
 		sysinfo_set_item_val("fb.kind", NULL, 6);
-		
+
 		fb_exported = true;
 	}
-	
+
 	return skidev;
 }
@@ -241,8 +241,8 @@
 	assert(instance);
 	assert(srlnin);
-	
+
 	instance->srlnin = srlnin;
 	thread_ready(instance->thread);
-	
+
 	sysinfo_set_item_val("kbd", NULL, true);
 	sysinfo_set_item_val("kbd.type", NULL, KBD_SKI);
Index: kernel/arch/ia64/src/fpu_context.c
===================================================================
--- kernel/arch/ia64/src/fpu_context.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/src/fpu_context.c	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -103,5 +103,5 @@
 		[f61] "=m" (fctx->fr[29])
 	);
-	
+
 	asm volatile (
 		"stf.spill %[f62] = f62\n"
@@ -314,5 +314,5 @@
 		[f61] "m" (fctx->fr[29])
 	);
-	
+
 	asm volatile (
 		"ldf.fill f62 = %[f62]\n"
Index: kernel/arch/ia64/src/ia64.c
===================================================================
--- kernel/arch/ia64/src/ia64.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/src/ia64.c	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -108,7 +108,7 @@
 	    PAGE_WRITE | PAGE_NOT_CACHEABLE);
 	int i;
-	
+
 	int myid, myeid;
-	
+
 	myid = ia64_get_cpu_id();
 	myeid = ia64_get_cpu_eid();
@@ -167,10 +167,10 @@
 		}
 	}
-	
+
 	outdev_t *skidev = skiout_init();
 	if (skidev)
 		stdout_wire(skidev);
 #endif
-	
+
 #ifdef CONFIG_EGA
 	outdev_t *egadev = ega_init(EGA_BASE, EGA_VIDEORAM);
@@ -178,5 +178,5 @@
 		stdout_wire(egadev);
 #endif
-	
+
 #ifdef CONFIG_NS16550
 	ns16550_instance_t *ns16550_instance
@@ -191,5 +191,5 @@
 		}
 	}
-	
+
 	sysinfo_set_item_val("kbd", NULL, true);
 	sysinfo_set_item_val("kbd.inr", NULL, NS16550_IRQ);
@@ -198,5 +198,5 @@
 	    (uintptr_t) NS16550_BASE);
 #endif
-	
+
 #ifdef CONFIG_I8042
 	i8042_instance_t *i8042_instance = i8042_init((i8042_t *) I8042_BASE,
@@ -211,5 +211,5 @@
 	}
 #endif
-	
+
 	sysinfo_set_item_val("ia64_iospace", NULL, true);
 	sysinfo_set_item_val("ia64_iospace.address", NULL, true);
@@ -251,5 +251,5 @@
 	    kernel_uarg->uspace_stack_size / 2,
 	    (uintptr_t) kernel_uarg->uspace_uarg, psr.value, rsc.value);
-	
+
 	while (1);
 }
@@ -274,5 +274,5 @@
 	fptr->fnc = (sysarg_t) addr;
 	fptr->gp = ((sysarg_t *) caller)[1];
-	
+
 	return (void *) fptr;
 }
Index: kernel/arch/ia64/src/interrupt.c
===================================================================
--- kernel/arch/ia64/src/interrupt.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/src/interrupt.c	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -124,5 +124,5 @@
 {
 	assert(n <= VECTOR_MAX);
-	
+
 	if (n >= VECTORS_16_BUNDLE_START)
 		return vector_names_16_bundle[n - VECTORS_16_BUNDLE_START];
@@ -141,5 +141,5 @@
 	printf("cr.isr=%#0" PRIx64 "\tcr.ipsr=%#0" PRIx64 "\n",
 	    istate->cr_isr.value, istate->cr_ipsr.value);
-	
+
 	printf("cr.iip=%#0" PRIxPTR ", #%u\t(%s)\n",
 	    istate->cr_iip, istate->cr_isr.ei,
@@ -154,5 +154,5 @@
 {
 	const char *desc;
-	
+
 	switch (istate->cr_isr.ge_code) {
 	case GE_ILLEGALOP:
@@ -178,5 +178,5 @@
 		break;
 	}
-	
+
 	fault_if_from_uspace(istate, "General Exception (%s).", desc);
 	panic_badtrap(istate, n, "General Exception (%s).", desc);
@@ -209,5 +209,5 @@
 		istate->cr_ipsr.ri++;
 	}
-	
+
 	interrupts_enable();
 	ret = syscall_handler(istate->in0, istate->in1, istate->in2,
@@ -236,10 +236,10 @@
 {
 	cr_ivr_t ivr;
-	
+
 	ivr.value = ivr_read();
 	srlz_d();
-	
+
 	irq_t *irq;
-	
+
 	switch (ivr.vector) {
 	case INTERRUPT_SPURIOUS:
@@ -248,5 +248,5 @@
 #endif
 		break;
-	
+
 #ifdef CONFIG_SMP
 	case VECTOR_TLB_SHOOTDOWN_IPI:
@@ -255,5 +255,5 @@
 		break;
 #endif
-	
+
 	case INTERRUPT_TIMER:
 		irq = irq_dispatch_and_lock(ivr.vector);
Index: kernel/arch/ia64/src/ivt.S
===================================================================
--- kernel/arch/ia64/src/ivt.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/src/ivt.S	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -57,8 +57,8 @@
 	mov r19 = cr.ipsr
 	mov r20 = cr.isr ;;
-	
+
     /* 2. Move IIP to IIPA. */
 	mov cr.iipa = r18
-	
+
     /* 3. Sign extend IIM[20:0], shift left by 4 and add to IIP. */
 	shl r17 = r17, 43 ;;	/* shift bit 20 to bit 63 */
@@ -66,9 +66,9 @@
 	add r18 = r18, r17 ;;
 	mov cr.iip = r18
-	
+
     /* 4. Set IPSR.ri to 0. */
 	dep r19 = 0, r19, PSR_RI_SHIFT, PSR_RI_LEN ;;
 	mov cr.ipsr = r19
-	
+
     /* 5. Check whether IPSR.tb or IPSR.ss is set. */
 
@@ -76,5 +76,5 @@
 	 * Implement this when Taken Branch and Single Step traps can occur.
 	 */
-    
+
     /* 6. Restore predicates and return from interruption. */
 	mov pr = r16 ;;
@@ -104,9 +104,9 @@
 SYMBOL(heavyweight_handler)
     /* 1. copy interrupt registers into bank 0 */
-    
+
 	/*
 	 * Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0.
 	 */
-	
+
 	/* Set up FPU as in interrupted context. */
 	mov r24 = psr
@@ -126,8 +126,8 @@
 	mov r27 = cr.isr
 	mov r28 = cr.ifa
-	
+
     /* 2. preserve predicate register into bank 0 */
 	mov r29 = pr ;;
-	
+
     /* 3. switch to kernel memory stack */
     	mov r30 = cr.ipsr
@@ -149,5 +149,5 @@
 	 */
 (p3)	cmp.eq p3, p4 = VRN_KERNEL, r31 ;;
-	
+
 	/*
 	 * Now, p4 is true iff the stack needs to be switched to kernel stack.
@@ -155,5 +155,5 @@
 	mov r30 = r12
 (p4)	mov r12 = R_KSTACK ;;
-	
+
 	add r12 = -STACK_FRAME_SIZE, r12 ;;
 	add r31 = STACK_SCRATCH_AREA_SIZE + ISTATE_OFFSET_IN6, r12
@@ -166,5 +166,5 @@
 	 */
 	cmp.eq p6, p5 = EXC_BREAK_INSTRUCTION, R_VECTOR ;;
-	
+
 	/*
 	 * From now on, if this is break_instruction handler, p6 is true and p5
@@ -181,7 +181,7 @@
 (p6)	st8 [r31] = r32, -STACK_ITEM_SIZE ;;	/* save in0 */
 (p5)	add r31 = -(7 * STACK_ITEM_SIZE), r31 ;;
-    
+
 	st8 [r31] = r30, -STACK_ITEM_SIZE ;;	/* save old stack pointer */
-	
+
 	st8 [r31] = r29, -STACK_ITEM_SIZE ;;	/* save predicate registers */
 
@@ -197,16 +197,16 @@
 	cover
 	mov r26 = cr.ifs
-	
+
 	st8 [r31] = r24, -STACK_ITEM_SIZE ;;	/* save ar.rsc */
 	st8 [r31] = r25, -STACK_ITEM_SIZE ;;	/* save ar.pfs */
 	st8 [r31] = r26, -STACK_ITEM_SIZE	/* save ar.ifs */
-	
+
 	and r24 = ~(RSC_PL_MASK), r24 ;;
 	and r30 = ~(RSC_MODE_MASK), r24 ;;
 	mov ar.rsc = r30 ;;		/* update RSE state */
-	
+
 	mov r27 = ar.rnat
 	mov r28 = ar.bspstore ;;
-	
+
 	/*
 	 * Inspect BSPSTORE to figure out whether it is necessary to switch to
@@ -215,5 +215,5 @@
 (p1)	shr.u r30 = r28, VRN_SHIFT ;;
 (p1)	cmp.eq p1, p2 = VRN_KERNEL, r30 ;;
-	
+
 	/*
 	 * If BSPSTORE needs to be switched, p1 is false and p2 is true.
@@ -222,14 +222,14 @@
 (p2)	mov r30 = R_KSTACK_BSP ;;
 (p2)	mov ar.bspstore = r30 ;;
-	
+
 	mov r29 = ar.bsp
-	
+
 	st8 [r31] = r27, -STACK_ITEM_SIZE ;;	/* save ar.rnat */
 	st8 [r31] = r30, -STACK_ITEM_SIZE ;;	/* save new value written to ar.bspstore */
 	st8 [r31] = r28, -STACK_ITEM_SIZE ;;	/* save ar.bspstore */
 	st8 [r31] = r29, -STACK_ITEM_SIZE 	/* save ar.bsp */
-	
+
 	mov ar.rsc = r24		/* restore RSE's setting + kernel privileges */
-	
+
     /* steps 6 - 15 are done by heavyweight_handler_inner() */
 	mov R_RET = b0 			/* save b0 belonging to interrupted context */
@@ -292,5 +292,5 @@
 	ld8 r29 = [r31], +STACK_ITEM_SIZE ;;	/* load predicate registers */
 	mov pr = r29
-	
+
     /* 19. return from interruption */
     	ld8 r12 = [r31]				/* load stack pointer */
@@ -303,10 +303,10 @@
 	 */
 	alloc loc0 = ar.pfs, 0, 48, 2, 0 ;;
-	
+
 	/* bank 0 is going to be shadowed, copy essential data from there */
 	mov loc1 = R_RET	/* b0 belonging to interrupted context */
 	mov loc2 = R_HANDLER
 	mov out0 = R_VECTOR
-	
+
 	add out1 = STACK_SCRATCH_AREA_SIZE, r12
 
@@ -315,5 +315,5 @@
 	bsw.1 ;;
 	srlz.d
-	
+
     /* 7. preserve branch and application registers */
     	mov loc3 = ar.unat
@@ -323,5 +323,5 @@
 	mov loc7 = ar.csd
 	mov loc8 = ar.ssd
-	
+
 	mov loc9 = b0
 	mov loc10 = b1
@@ -332,5 +332,5 @@
 	mov loc15 = b6
 	mov loc16 = b7
-	
+
     /* 8. preserve general and floating-point registers */
 	mov loc17 = r1
@@ -374,5 +374,5 @@
 	add r30 = ISTATE_OFFSET_F6 + STACK_SCRATCH_AREA_SIZE, r12
 	add r31 = ISTATE_OFFSET_F7 + STACK_SCRATCH_AREA_SIZE, r12 ;;
-	
+
 	stf.spill [r26] = f2, 8 * FLOAT_ITEM_SIZE
 	stf.spill [r27] = f3, 8 * FLOAT_ITEM_SIZE
@@ -410,5 +410,5 @@
 
 	mov loc47 = ar.fpsr	/* preserve floating point status register */
-    
+
     /* 9. skipped (will not enable interrupts) */
 	/*
@@ -420,5 +420,5 @@
     /* 10. call handler */
     	movl r1 = __gp
-    
+
     	mov b1 = loc2
 	br.call.sptk.many b0 = b1
@@ -426,5 +426,5 @@
     /* 11. return from handler */
 0:
-	
+
     /* 12. skipped (will not disable interrupts) */
 	/*
@@ -477,5 +477,5 @@
 	ldf.fill f30 = [r30]
 	ldf.fill f31 = [r31] ;;
-	
+
 	mov r1 = loc17
 	mov r2 = loc18
@@ -511,5 +511,5 @@
 
 	mov ar.fpsr = loc47	/* restore floating point status register */
-	
+
     /* 14. restore branch and application registers */
     	mov ar.unat = loc3
@@ -519,5 +519,5 @@
 	mov ar.csd = loc7
 	mov ar.ssd = loc8
-	
+
 	mov b0 = loc9
 	mov b1 = loc10
@@ -528,5 +528,5 @@
 	mov b6 = loc15
 	mov b7 = loc16
-	
+
     /* 15. disable PSR.ic and switch to bank 0 */
 	rsm PSR_IC_MASK
@@ -578,5 +578,5 @@
 	HEAVYWEIGHT_HANDLER 0x5e
 	HEAVYWEIGHT_HANDLER 0x5f
-	
+
 	HEAVYWEIGHT_HANDLER 0x60
 	HEAVYWEIGHT_HANDLER 0x61
Index: kernel/arch/ia64/src/mm/as.c
===================================================================
--- kernel/arch/ia64/src/mm/as.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/src/mm/as.c	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -58,7 +58,7 @@
 	region_register_t rr;
 	int i;
-	
+
 	assert(as->asid != ASID_INVALID);
-	
+
 	/*
 	 * Load respective ASID (7 consecutive RIDs) to
@@ -68,5 +68,5 @@
 		if (i == VRN_KERNEL)
 			continue;
-		
+
 		rr.word = rr_read(i);
 		rr.map.ve = false;		/* disable VHPT walker */
Index: kernel/arch/ia64/src/mm/frame.c
===================================================================
--- kernel/arch/ia64/src/mm/frame.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/src/mm/frame.c	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -92,7 +92,7 @@
 	if (config.cpu_active > 1)
 		return;
-	
+
 	frame_common_arch_init(true);
-	
+
 	/*
 	 * Blacklist ROM regions.
@@ -112,5 +112,5 @@
 	if (config.cpu_active > 1)
 		return;
-	
+
 	frame_common_arch_init(false);
 }
Index: kernel/arch/ia64/src/mm/page.c
===================================================================
--- kernel/arch/ia64/src/mm/page.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/src/mm/page.c	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -124,5 +124,5 @@
 	vrn = page >> VRN_SHIFT;
 	rid = ASID2RID(asid, vrn);
-	
+
 	rr_save.word = rr_read(vrn);
 	if (rr_save.map.rid == rid) {
@@ -133,5 +133,5 @@
 		return v;
 	}
-	
+
 	/*
 	 * The RID must be written to some region register.
@@ -171,5 +171,5 @@
 	vrn = page >> VRN_SHIFT;
 	rid = ASID2RID(asid, vrn);
-	
+
 	rr_save.word = rr_read(vrn);
 	if (rr_save.map.rid == rid) {
@@ -179,5 +179,5 @@
 		return ttag(page) == v->present.tag.tag_word;
 	}
-	
+
 	/*
 	 * The RID must be written to some region register.
@@ -218,5 +218,5 @@
 	vrn = page >> VRN_SHIFT;
 	rid = ASID2RID(asid, vrn);
-	
+
 	/*
 	 * Compute ttag.
@@ -231,5 +231,5 @@
 	srlz_i();
 	srlz_d();
-	
+
 	/*
 	 * Clear the entry.
@@ -239,5 +239,5 @@
 	v->word[2] = 0;
 	v->word[3] = 0;
-	
+
 	v->present.p = true;
 	v->present.ma = (flags & PAGE_CACHEABLE) ?
Index: kernel/arch/ia64/src/mm/tlb.c
===================================================================
--- kernel/arch/ia64/src/mm/tlb.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/src/mm/tlb.c	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -61,7 +61,7 @@
 	uintptr_t adr;
 	uint32_t count1, count2, stride1, stride2;
-	
+
 	unsigned int i, j;
-	
+
 	adr = PAL_PTCE_INFO_BASE();
 	count1 = PAL_PTCE_INFO_COUNT1();
@@ -69,7 +69,7 @@
 	stride1 = PAL_PTCE_INFO_STRIDE1();
 	stride2 = PAL_PTCE_INFO_STRIDE2();
-	
+
 	ipl = interrupts_disable();
-	
+
 	for (i = 0; i < count1; i++) {
 		for (j = 0; j < count2; j++) {
@@ -82,10 +82,10 @@
 		adr += stride1;
 	}
-	
+
 	interrupts_restore(ipl);
-	
+
 	srlz_d();
 	srlz_i();
-	
+
 #ifdef CONFIG_VHPT
 	vhpt_invalidate_all();
@@ -110,8 +110,8 @@
 	int b = 0;
 	int c = cnt;
-	
+
 	uintptr_t va;
 	va = page;
-	
+
 	rr.word = rr_read(VA2VRN(page));
 	if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(page))))) {
@@ -121,5 +121,5 @@
 		 */
 		region_register_t rr0;
-		
+
 		rr0 = rr;
 		rr0.map.rid = ASID2RID(asid, VA2VRN(page));
@@ -128,10 +128,10 @@
 		srlz_i();
 	}
-	
+
 	while (c >>= 1)
 		b++;
 	b >>= 1;
 	uint64_t ps;
-	
+
 	switch (b) {
 	case 0: /* cnt 1 - 3 */
@@ -172,5 +172,5 @@
 		break;
 	}
-	
+
 	for (; va < (page + cnt * PAGE_SIZE); va += (1UL << ps))
 		asm volatile (
@@ -179,8 +179,8 @@
 			   [ps] "r" (ps << 2)
 		);
-	
+
 	srlz_d();
 	srlz_i();
-	
+
 	if (restore_rr) {
 		rr_write(VA2VRN(page), rr.word);
@@ -229,5 +229,5 @@
 	region_register_t rr;
 	bool restore_rr = false;
-	
+
 	rr.word = rr_read(VA2VRN(va));
 	if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) {
@@ -237,5 +237,5 @@
 		 */
 		region_register_t rr0;
-		
+
 		rr0 = rr;
 		rr0.map.rid = ASID2RID(asid, VA2VRN(va));
@@ -244,5 +244,5 @@
 		srlz_i();
 	}
-	
+
 	asm volatile (
 		"mov r8 = psr ;;\n"
@@ -264,5 +264,5 @@
 		: "p6", "p7", "r8"
 	);
-	
+
 	if (restore_rr) {
 		rr_write(VA2VRN(va), rr.word);
@@ -316,5 +316,5 @@
 	region_register_t rr;
 	bool restore_rr = false;
-	
+
 	rr.word = rr_read(VA2VRN(va));
 	if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) {
@@ -324,5 +324,5 @@
 		 */
 		region_register_t rr0;
-		
+
 		rr0 = rr;
 		rr0.map.rid = ASID2RID(asid, VA2VRN(va));
@@ -331,5 +331,5 @@
 		srlz_i();
 	}
-	
+
 	asm volatile (
 		"mov r8 = psr ;;\n"
@@ -352,5 +352,5 @@
 		: "p6", "p7", "r8"
 	);
-	
+
 	if (restore_rr) {
 		rr_write(VA2VRN(va), rr.word);
@@ -373,8 +373,8 @@
 {
 	tlb_entry_t entry;
-	
+
 	entry.word[0] = 0;
 	entry.word[1] = 0;
-	
+
 	entry.p = true;           /* present */
 	entry.ma = MA_WRITEBACK;
@@ -385,5 +385,5 @@
 	entry.ppn = frame >> PPN_SHIFT;
 	entry.ps = PAGE_WIDTH;
-	
+
 	if (dtr)
 		dtr_mapping_insert(page, ASID_KERNEL, entry, tr);
@@ -418,8 +418,8 @@
 {
 	tlb_entry_t entry;
-	
+
 	entry.word[0] = 0;
 	entry.word[1] = 0;
-	
+
 	entry.p = t->p;
 	entry.ma = t->c ? MA_WRITEBACK : MA_UNCACHEABLE;
@@ -430,7 +430,7 @@
 	entry.ppn = t->frame >> PPN_SHIFT;
 	entry.ps = PAGE_WIDTH;
-	
+
 	dtc_mapping_insert(t->page, t->as->asid, entry);
-	
+
 #ifdef CONFIG_VHPT
 	vhpt_mapping_insert(t->page, t->as->asid, entry);
@@ -446,10 +446,10 @@
 {
 	tlb_entry_t entry;
-	
+
 	entry.word[0] = 0;
 	entry.word[1] = 0;
-	
+
 	assert(t->x);
-	
+
 	entry.p = t->p;
 	entry.ma = t->c ? MA_WRITEBACK : MA_UNCACHEABLE;
@@ -459,7 +459,7 @@
 	entry.ppn = t->frame >> PPN_SHIFT;
 	entry.ps = PAGE_WIDTH;
-	
+
 	itc_mapping_insert(t->page, t->as->asid, entry);
-	
+
 #ifdef CONFIG_VHPT
 	vhpt_mapping_insert(t->page, t->as->asid, entry);
@@ -486,7 +486,7 @@
 	uintptr_t va;
 	pte_t t;
-	
+
 	va = istate->cr_ifa; /* faulting address */
-	
+
 	assert(!is_kernel_fault(va));
 
@@ -532,18 +532,18 @@
 			uint64_t io_page = (va & ((1 << LEGACYIO_PAGE_WIDTH) - 1)) >>
 			    LEGACYIO_SINGLE_PAGE_WIDTH;
-			
+
 			if (is_io_page_accessible(io_page)) {
 				uint64_t page, frame;
-				
+
 				page = LEGACYIO_USER_BASE +
 				    (1 << LEGACYIO_SINGLE_PAGE_WIDTH) * io_page;
 				frame = LEGACYIO_PHYS_BASE +
 				    (1 << LEGACYIO_SINGLE_PAGE_WIDTH) * io_page;
-				
+
 				tlb_entry_t entry;
-				
+
 				entry.word[0] = 0;
 				entry.word[1] = 0;
-				
+
 				entry.p = true;             /* present */
 				entry.ma = MA_UNCACHEABLE;
@@ -554,5 +554,5 @@
 				entry.ppn = frame >> PPN_SHIFT;
 				entry.ps = LEGACYIO_SINGLE_PAGE_WIDTH;
-				
+
 				dtc_mapping_insert(page, TASK->as->asid, entry);
 				return 1;
@@ -563,5 +563,5 @@
 		}
 	}
-	
+
 	return 0;
 }
@@ -586,8 +586,8 @@
 		return;
 	}
-	
+
 	uintptr_t va = istate->cr_ifa;  /* faulting address */
 	as_t *as = AS;
-	
+
 	if (is_kernel_fault(va)) {
 		if (va < end_of_identity) {
@@ -601,6 +601,6 @@
 		}
 	}
-	
-	
+
+
 	pte_t t;
 	bool found = page_mapping_find(as, va, true, &t);
@@ -616,5 +616,5 @@
 		if (try_memmap_io_insertion(va, istate))
 			return;
-		
+
 		/*
 		 * Forward the page fault to the address space page fault
@@ -649,7 +649,7 @@
 	pte_t t;
 	as_t *as = AS;
-	
+
 	va = istate->cr_ifa;  /* faulting address */
-	
+
 	if (is_kernel_fault(va))
 		as = AS_KERNEL;
@@ -683,9 +683,9 @@
 	uintptr_t va;
 	pte_t t;
-	
+
 	va = istate->cr_ifa;  /* faulting address */
 
 	assert(!is_kernel_fault(va));
-	
+
 	bool found = page_mapping_find(AS, va, true, &t);
 
@@ -717,7 +717,7 @@
 	pte_t t;
 	as_t *as = AS;
-	
+
 	va = istate->cr_ifa;  /* faulting address */
-	
+
 	if (is_kernel_fault(va))
 		as = AS_KERNEL;
@@ -755,9 +755,9 @@
 	uintptr_t va;
 	pte_t t;
-	
+
 	va = istate->cr_ifa;  /* faulting address */
 
 	assert(!is_kernel_fault(va));
-	
+
 	/*
 	 * Assume a write to a read-only page.
@@ -782,7 +782,7 @@
 	uintptr_t va;
 	pte_t t;
-	
+
 	va = istate->cr_ifa;  /* faulting address */
-	
+
 	assert(!is_kernel_fault(va));
 
@@ -790,5 +790,5 @@
 
 	assert(found);
-	
+
 	if (t.p) {
 		/*
Index: kernel/arch/ia64/src/mm/vhpt.c
===================================================================
--- kernel/arch/ia64/src/mm/vhpt.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/src/mm/vhpt.c	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -46,5 +46,5 @@
 	if (!vhpt_frame)
 		panic("Kernel configured with VHPT but no memory for table.");
-	
+
 	vhpt_base = (vhpt_entry_t *) PA2KA(vhpt_frame);
 	vhpt_invalidate_all();
@@ -59,10 +59,10 @@
 	rid_t rid;
 	uint64_t tag;
-	
+
 	vhpt_entry_t *ventry;
-	
+
 	vrn = va >> VRN_SHIFT;
 	rid = ASID2RID(asid, vrn);
-	
+
 	rr_save.word = rr_read(vrn);
 	rr.word = rr_save.word;
@@ -70,5 +70,5 @@
 	rr_write(vrn, rr.word);
 	srlz_i();
-	
+
 	ventry = (vhpt_entry_t *) thash(va);
 	tag = ttag(va);
@@ -76,5 +76,5 @@
 	srlz_i();
 	srlz_d();
-	
+
 	ventry->word[0] = entry.word[0];
 	ventry->word[1] = entry.word[1];
Index: kernel/arch/ia64/src/proc/scheduler.c
===================================================================
--- kernel/arch/ia64/src/proc/scheduler.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/src/proc/scheduler.c	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -54,5 +54,5 @@
 {
 	uintptr_t base;
-	
+
 	base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
 
@@ -63,8 +63,8 @@
 		 * Use DTR[TR_KSTACK1] and DTR[TR_KSTACK2] to map it.
 		 */
-		 
+
 		/* purge DTR[TR_STACK1] and DTR[TR_STACK2] */
 		dtr_purge((uintptr_t) THREAD->kstack, PAGE_WIDTH+1);
-		
+
 		/* insert DTR[TR_STACK1] and DTR[TR_STACK2] */
 		dtlb_kernel_mapping_insert((uintptr_t) THREAD->kstack,
@@ -74,5 +74,5 @@
 		    DTR_KSTACK2);
 	}
-	
+
 	/*
 	 * Record address of kernel backing store to bank 0 r22.
Index: kernel/arch/ia64/src/start.S
===================================================================
--- kernel/arch/ia64/src/start.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/ia64/src/start.S	(revision a35b458e9db1ca95e679799dc7c1b12c83359ca3)
@@ -54,46 +54,46 @@
 SYMBOL(kernel_image_start)
 	.auto
-	
+
 	mov psr.l = r0
 	srlz.i
 	srlz.d
-	
+
 	# Fill TR.i and TR.d using Region Register #VRN_KERNEL
-	
+
 	movl r8 = (VRN_KERNEL << VRN_SHIFT)
 	mov r9 = rr[r8]
-	
+
 	movl r10 = (RR_MASK)
 	and r9 = r10, r9
 	movl r10 = (((RID_KERNEL7) << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT))
 	or r9 = r10, r9
-	
+
 	mov rr[r8] = r9
-	
+
 	movl r8 = (VRN_KERNEL << VRN_SHIFT)
 	mov cr.ifa = r8
-	
+
 	mov r11 = cr.itir
 	movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT)
 	or r10 = r10, r11
 	mov cr.itir = r10
-	
+
 	movl r10 = (KERNEL_TRANSLATION_I)
 	itr.i itr[r0] = r10
 	movl r10 = (KERNEL_TRANSLATION_D)
 	itr.d dtr[r0] = r10
-	
+
 	# Initialize DCR
-	
+
 	movl r10 = (DCR_DP_MASK | DCR_DK_MASK | DCR_DX_MASK | DCR_DR_MASK | DCR_DA_MASK | DCR_DD_MASK | DCR_LC_MASK)
 	mov r9 = cr.dcr
 	or r10 = r10, r9
 	mov cr.dcr = r10
-	
+
 	# Initialize PSR
-	
+
 	movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK)  /* Enable paging */
 	mov r9 = psr
-	
+
 	or r10 = r10, r9
 	mov cr.ipsr = r10
@@ -103,7 +103,7 @@
 	srlz.d
 	srlz.i
-	
+
 	.explicit
-	
+
 	/*
 	 * Return From Interrupt is the only way to
@@ -113,5 +113,5 @@
 
 paging_start:
-	
+
 	/*
 	 * Now we are paging.
@@ -126,8 +126,8 @@
 	srlz.d ;;
 
-	
+
 	# Switch to register bank 1
 	bsw.1
-	
+
 	# Initialize register stack
 	mov ar.rsc = r0
@@ -135,5 +135,5 @@
 	mov ar.bspstore = r8
 	loadrs
-	
+
 	#
 	# Initialize memory stack to some sane value and allocate a scratch area
@@ -142,8 +142,8 @@
 	movl sp = stack0 ;;
 	add sp = -16, sp
-	
+
 	# Initialize gp (Global Pointer) register
 	movl gp = __gp
-	
+
 	#
 	# Initialize bootinfo on BSP.
@@ -153,9 +153,9 @@
 	addl r21 = @gprel(bootinfo), gp ;;
 	st8 [r21] = r20
-	
+
 	ssm (1 << 19) ;; /* Disable f32 - f127 */
 	srlz.i
 	srlz.d ;;
-	
+
 	br.call.sptk.many b0 = ia64_pre_main
 0: