Index: uspace/drv/bus/usb/ehci/Makefile =================================================================== --- uspace/drv/bus/usb/ehci/Makefile (revision f9351b1fb2d918b59c7670c408a32770aa4d4c9b) +++ uspace/drv/bus/usb/ehci/Makefile (revision a24d68251578222a03414d0b81434d7d480c7519) @@ -49,4 +49,5 @@ endpoint_list.c \ hc.c \ + hw_struct/queue_head.c \ main.c \ res.c Index: uspace/drv/bus/usb/ehci/ehci_endpoint.c =================================================================== --- uspace/drv/bus/usb/ehci/ehci_endpoint.c (revision f9351b1fb2d918b59c7670c408a32770aa4d4c9b) +++ uspace/drv/bus/usb/ehci/ehci_endpoint.c (revision a24d68251578222a03414d0b81434d7d480c7519) @@ -85,5 +85,5 @@ } -// qh_init(ehci_ep->qh, ep); + qh_init(ehci_ep->qh, ep); endpoint_set_hc_data( ep, ehci_ep, ehci_ep_toggle_get, ehci_ep_toggle_set); Index: uspace/drv/bus/usb/ehci/hw_struct/queue_head.c =================================================================== --- uspace/drv/bus/usb/ehci/hw_struct/queue_head.c (revision a24d68251578222a03414d0b81434d7d480c7519) +++ uspace/drv/bus/usb/ehci/hw_struct/queue_head.c (revision a24d68251578222a03414d0b81434d7d480c7519) @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2013 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup drvusbehci + * @{ + */ +/** @file + * @brief EHCI driver + */ + +#include +#include +#include +#include + +#include "mem_access.h" + +#include "queue_head.h" + +const uint32_t speed[] = { + [USB_SPEED_LOW] = QH_EP_CHAR_EPS_LS, + [USB_SPEED_FULL] = QH_EP_CHAR_EPS_FS, + [USB_SPEED_HIGH] = QH_EP_CHAR_EPS_HS, +}; + +void qh_init(qh_t *instance, const endpoint_t *ep) +{ + assert(instance); + memset(instance, 0, sizeof(*instance)); + + EHCI_MEM32_WR(instance->horizontal, LINK_POINTER_TERM); + EHCI_MEM32_WR(instance->current, LINK_POINTER_TERM); + EHCI_MEM32_WR(instance->next, LINK_POINTER_TERM); + EHCI_MEM32_WR(instance->alternate, LINK_POINTER_TERM); + if (ep == NULL) { + /* Mark as halted and list head, used by endpoint lists + * as dummy */ + EHCI_MEM32_WR(instance->ep_char, QH_EP_CHAR_H_FLAG); + EHCI_MEM32_WR(instance->status, QH_STATUS_HALTED_FLAG); + return; + } + assert(ep->speed < ARRAY_SIZE(speed)); + EHCI_MEM32_WR(instance->ep_char, + QH_EP_CHAR_ADDR_SET(ep->address) | + QH_EP_CHAR_EP_SET(ep->endpoint) | + speed[ep->speed] | + QH_EP_CHAR_MAX_LENGTH_SET(ep->max_packet_size) + ); + if (ep->transfer_type == USB_TRANSFER_CONTROL) { + if (ep->speed != USB_SPEED_HIGH) + EHCI_MEM32_SET(instance->ep_char, QH_EP_CHAR_C_FLAG); + /* Let BULK and INT use queue head managed toggle, + * CONTROL needs special toggle handling anyway */ + EHCI_MEM32_SET(instance->ep_char, QH_EP_CHAR_DTC_FLAG); + } + + // TODO Fix 'multi' 1 packet should be safe. Probably won't work + // without enabling parking mode in async schedule + // TODO Figure out how to correctly use CMASK and SMASK for LS/FS + // INT transfers. Current values are just guesses + /* Setting TT stuff on HS endpoints is OK, the fields are ignored */ + EHCI_MEM32_WR(instance->ep_cap, + QH_EP_CAP_MULTI_SET(1) | + QH_EP_CAP_TT_PORT_SET(ep->tt.port) | + QH_EP_CAP_TT_ADDR_SET(ep->tt.address) | + QH_EP_CAP_C_MASK_SET(3 << 2) | + QH_EP_CAP_S_MASK_SET(3) + ); + /* The rest of the fields are transfer working area, it should be ok to + * leave it NULL */ +} + +/** + * @} + */ Index: uspace/drv/bus/usb/ehci/hw_struct/queue_head.h =================================================================== --- uspace/drv/bus/usb/ehci/hw_struct/queue_head.h (revision f9351b1fb2d918b59c7670c408a32770aa4d4c9b) +++ uspace/drv/bus/usb/ehci/hw_struct/queue_head.h (revision a24d68251578222a03414d0b81434d7d480c7519) @@ -37,4 +37,5 @@ #include #include +#include #include "link_pointer.h" @@ -48,30 +49,51 @@ #define QH_EP_CHAR_RL_SHIFT 28 #define QH_EP_CHAR_C_FLAG (1 << 27) -#define QH_EP_CHAR_LENGTH_MASK 0x7ff -#define QH_EP_CHAR_LENGTH_SHIFT 16 +#define QH_EP_CHAR_MAX_LENGTH_MASK 0x7ff +#define QH_EP_CHAR_MAX_LENGTH_SHIFT 16 +#define QH_EP_CHAR_MAX_LENGTH_SET(len) \ + (((len) & QH_EP_CHAR_MAX_LENGTH_MASK) << QH_EP_CHAR_MAX_LENGTH_SHIFT) +#define QH_EP_CHAR_MAX_LENGTH_GET(val) \ + (((val) >> QH_EP_CHAR_MAX_LENGTH_SHIFT) & QH_EP_CHAR_MAX_LENGTH_MASK) #define QH_EP_CHAR_H_FLAG (1 << 15) #define QH_EP_CHAR_DTC_FLAG (1 << 14) -#define QH_EP_CHAR_EPS_MASK 0x3 -#define QH_EP_CHAR_EPS_SHIFT 12 -#define QH_EP_CHAR_EPS_FS 0x0 -#define QH_EP_CHAR_EPS_LS 0x1 -#define QH_EP_CHAR_EPS_HS 0x2 +#define QH_EP_CHAR_EPS_FS (0x0 << 12) +#define QH_EP_CHAR_EPS_LS (0x1 << 12) +#define QH_EP_CHAR_EPS_HS (0x2 << 12) +#define QH_EP_CHAR_EPS_MASK (0x3 << 12) #define QH_EP_CHAR_EP_MASK 0xf #define QH_EP_CHAR_EP_SHIFT 8 +#define QH_EP_CHAR_EP_SET(num) \ + (((num) & QH_EP_CHAR_EP_MASK) << QH_EP_CHAR_EP_SHIFT) +#define QH_EP_CHAR_ADDR_GET(val) \ + (((val) >> QH_EP_CHAR_ADDR_SHIFT) & QH_EP_CHAR_ADDR_MASK) #define QH_EP_CHAR_INACT_FLAG (1 << 7) #define QH_EP_CHAR_ADDR_MASK 0x3f #define QH_EP_CHAR_ADDR_SHIFT 0 +#define QH_EP_CHAR_ADDR_SET(addr) \ + (((addr) & QH_EP_CHAR_ADDR_MASK) << QH_EP_CHAR_ADDR_SHIFT) +#define QH_EP_CHAR_ADDR_GET(val) \ + (((val) >> QH_EP_CHAR_ADDR_SHIFT) & QH_EP_CHAR_ADDR_MASK) volatile uint32_t ep_cap; #define QH_EP_CAP_MULTI_MASK 0x3 #define QH_EP_CAP_MULTI_SHIFT 30 +#define QH_EP_CAP_MULTI_SET(count) \ + (((count) & QH_EP_CAP_MULTI_MASK) << QH_EP_CAP_MULTI_SHIFT) #define QH_EP_CAP_PORT_MASK 0x7f #define QH_EP_CAP_PORT_SHIFT 23 +#define QH_EP_CAP_TT_PORT_SET(addr) \ + (((addr) & QH_EP_CAP_HUB_MASK) << QH_EP_CAP_HUB_SHIFT) #define QH_EP_CAP_HUB_MASK 0x7f #define QH_EP_CAP_HUB_SHIFT 16 +#define QH_EP_CAP_TT_ADDR_SET(addr) \ + (((addr) & QH_EP_CAP_HUB_MASK) << QH_EP_CAP_HUB_SHIFT) #define QH_EP_CAP_C_MASK_MASK 0xff #define QH_EP_CAP_C_MASK_SHIFT 8 +#define QH_EP_CAP_C_MASK_SET(val) \ + (((val) & QH_EP_CAP_C_MASK_MASK) << QH_EP_CAP_C_MASK_SHIFT) #define QH_EP_CAP_S_MASK_MASK 0xff -#define QH_EP_CAP_S_MASL_SHIFT 0 +#define QH_EP_CAP_S_MASK_SHIFT 0 +#define QH_EP_CAP_S_MASK_SET(val) \ + (((val) & QH_EP_CAP_S_MASK_MASK) << QH_EP_CAP_S_MASK_SHIFT) link_pointer_t current; @@ -118,5 +140,5 @@ } qh_t; - +void qh_init(qh_t *instance, const endpoint_t *ep); #endif /**