Changeset a1493d9 in mainline for arch/mips/src

Timestamp:

2005-09-10T17:54:53Z (21 years ago)

Author:

Ondrej Palkovsky <ondrap@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

8491c48

Parents:

24241cf

Message:

Fixed bad address loading in simulators.
FPU cooprocessor unusable now checks, if it is FPU that is unusable.

Location:

arch/mips/src

Files:

• exception.c (modified) (3 diffs)
• mips.c (modified) (2 diffs)

arch/mips/src/exception.c

@@ -37 +37 @@
 void exception(struct exception_regdump *pstate)
 {
+        int cause;
         int excno;
         __u32 epc_shift = 0;
@@ -60 +61 @@
                 THREAD->pstate = pstate;
 
+        cause = cp0_cause_read();
+        excno = cp0_cause_excno(cause);
         /* decode exception number and process the exception */
-        switch (excno = (cp0_cause_read() >> 2) & 0x1f) {
+        switch (excno) {
                 case EXC_Int:
                         interrupt();
@@ -71 +74 @@
                 case EXC_CpU:
 #ifdef FPU_LAZY     
-                        scheduler_fpu_lazy_request();
-#else
-                        panic("unhandled Coprocessor Unusable Exception\n");
+                        if (cp0_cause_coperr(cause) == fpu_cop_id)
+                                scheduler_fpu_lazy_request();
+                        else
 #endif
+                                panic("unhandled Coprocessor Unusable Exception\n");
                         break;
                 case EXC_Mod:

arch/mips/src/mips.c

@@ -38 +38 @@
 #include <arch/interrupt.h>
 
+#include <print.h>
+
 /* Size of the code jumping to the exception handler code 
  * - J+NOP 
@@ -47 +49 @@
 #define CACHE_EXC ((char *) 0x80000100)
 
-#include <arch/debug.h>
-
-#include <print.h>
 void arch_pre_mm_init(void)
 {