Changeset a0d74fd in mainline for arch/ia64/include


Ignore:
Timestamp:
2006-03-01T11:07:04Z (20 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
9ad03fe
Parents:
2c49fbbe
Message:

ia64 work.
Provide PA2KA(identity) mapping for kernel data references via Alternate Data TLB Fault handler.
Add before_thread_runs_arch() that maps kstack, if necessary.
Add easy to use dtlb_mapping_insert() for comfortable insertion of kernel data mappings.

Location:
arch/ia64/include/mm
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • arch/ia64/include/mm/asid.h

    r2c49fbbe ra0d74fd  
    3535
    3636typedef __u16 asid_t;
     37typedef __u32 rid_t;
     38
     39#endif  /* __ASM__ */
    3740
    3841/**
    … …  
    4144 * but those extra bits are not used by the kernel.
    4245 */
    43 #endif
    44  
    4546#define RIDS_PER_ASID           7
     47
    4648#define RID_MAX                 262143          /* 2^18 - 1 */
     49#define RID_KERNEL              0
     50#define RID_INVALID             1
    4751
    48 #define ASID2RID(asid, vrn)     (((asid)*RIDS_PER_ASID)+(vrn))
     52#define ASID2RID(asid, vrn)     (((asid)>RIDS_PER_ASID)?(((asid)*RIDS_PER_ASID)+(vrn)):(asid))
    4953#define RID2ASID(rid)           ((rid)/RIDS_PER_ASID)
    50 
    51 #ifndef __ASM__
    52 
    53 
    54 typedef __u32 rid_t;
    55 
    56 #endif
    5754
    5855#define ASID_MAX_ARCH           (RID_MAX/RIDS_PER_ASID)

  • arch/ia64/include/mm/page.h

    r2c49fbbe ra0d74fd  
    3131#define __ia64_PAGE_H__
    3232
     33#define PAGE_SIZE       FRAME_SIZE
     34#define PAGE_WIDTH      FRAME_WIDTH
     35
     36/** Bit width of the TLB-locked portion of kernel address space. */
     37#define KERNEL_PAGE_WIDTH       28      /* 256M */
     38
     39#define SET_PTL0_ADDRESS_ARCH(x)        /**< To be removed as situation permits. */
     40
     41#define PPN_SHIFT                       12
     42
     43#define VRN_SHIFT                       61
     44#define VRN_MASK                        (7LL << VRN_SHIFT)
     45#define VA2VRN(va)                      ((va)>>VRN_SHIFT)
     46
     47#ifdef __ASM__
     48#define VRN_KERNEL                      7
     49#else
     50#define VRN_KERNEL                      7LL
     51#endif
     52
     53#define REGION_REGISTERS                8
     54
     55#define KA2PA(x)        ((__address) (x-(VRN_KERNEL<<VRN_SHIFT)))
     56#define PA2KA(x)        ((__address) (x+(VRN_KERNEL<<VRN_SHIFT)))
     57
     58#define VHPT_WIDTH                      20              /* 1M */
     59#define VHPT_SIZE                       (1 << VHPT_WIDTH)
     60#define VHPT_BASE                       0               /* Must be aligned to VHPT_SIZE */
     61
     62#define PTA_BASE_SHIFT                  15
     63
     64/** Memory Attributes. */
     65#define MA_WRITEBACK    0x0
     66#define MA_UNCACHEABLE  0x4
     67
     68/** Privilege Levels. Only the most and the least privileged ones are ever used. */
     69#define PL_KERNEL       0x0
     70#define PL_USER         0x3
     71
     72/* Access Rigths. Only certain combinations are used by the kernel. */
     73#define AR_READ         0x0
     74#define AR_EXECUTE      0x1
     75#define AR_WRITE        0x2
     76
    3377#ifndef __ASM__
    34 
    3578
    3679#include <arch/mm/frame.h>
    … …  
    4184#include <typedefs.h>
    4285#include <debug.h>
    43 
    44 #endif
    45 
    46 #define PAGE_SIZE       FRAME_SIZE
    47 #define PAGE_WIDTH      FRAME_WIDTH
    48 #define KERNEL_PAGE_WIDTH       28
    49 
    50 
    51 
    52 #define SET_PTL0_ADDRESS_ARCH(x)        /**< To be removed as situation permits. */
    53 
    54 #define PPN_SHIFT                       12
    55 
    56 #define VRN_SHIFT                       61
    57 #define VRN_MASK                        (7LL << VRN_SHIFT)
    58 
    59 #ifdef __ASM__
    60 #define VRN_KERNEL                      7
    61 #else
    62 #define VRN_KERNEL                      7LL
    63 #endif
    64 
    65 #define REGION_REGISTERS                8
    66 
    67 #define KA2PA(x)        ((__address) (x-(VRN_KERNEL<<VRN_SHIFT)))
    68 #define PA2KA(x)        ((__address) (x+(VRN_KERNEL<<VRN_SHIFT)))
    69 
    70 
    71 #define VHPT_WIDTH                      20              /* 1M */
    72 #define VHPT_SIZE                       (1 << VHPT_WIDTH)
    73 #define VHPT_BASE                       0               /* Must be aligned to VHPT_SIZE */
    74 
    75 #define PTA_BASE_SHIFT                  15
    76 
    77 /** Memory Attributes. */
    78 #define MA_WRITEBACK    0x0
    79 #define MA_UNCACHEABLE  0x4
    80 
    81 /** Privilege Levels. Only the most and the least privileged ones are ever used. */
    82 #define PL_KERNEL       0x0
    83 #define PL_USER         0x3
    84 
    85 /* Access Rigths. Only certain combinations are used by the kernel. */
    86 #define AR_READ         0x0
    87 #define AR_EXECUTE      0x1
    88 #define AR_WRITE        0x2
    89 
    90 
    91 #define VA_REGION_INDEX 61
    92 
    93 #define VA_REGION(va) (va>>VA_REGION_INDEX)
    94 
    95 #ifndef __ASM__
    9686
    9787struct vhpt_tag_info {
    … …  
    156146} vhpt_entry_t;
    157147
    158 typedef vhpt_entry_t tlb_entry_t;
    159 
    160148struct region_register_map {
    161149        unsigned ve : 1;
    … …  
    231219        __u64 ret;
    232220        ASSERT(i < REGION_REGISTERS);
    233         i=i<<VRN_SHIFT;
    234         __asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i));
    235        
    236         return ret;
    237 }
    238 
     221        __asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT));
     222        return ret;
     223}
    239224
    240225/** Write Region Register.
    … …  
    246231{
    247232        ASSERT(i < REGION_REGISTERS);
    248         i=i<<VRN_SHIFT;
    249233        __asm__ volatile (
    250         "mov rr[%0] = %1;;\n"
    251         :
    252         : "r" (i), "r" (v));
     234                "mov rr[%0] = %1\n"
     235                :
     236                : "r" (i << VRN_SHIFT), "r" (v)
     237        );
    253238}
    254239 
    … …  
    281266extern void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags);
    282267
    283 
    284 
    285268#endif
    286269
    287270#endif
    288 
    289 

  • arch/ia64/include/mm/tlb.h

    r2c49fbbe ra0d74fd  
    3939#include <typedefs.h>
    4040
    41 extern void tc_mapping_insert(__address va, asid_t asid, vhpt_entry_t entry, bool dtc);
    42 extern void dtc_mapping_insert(__address va, asid_t asid, vhpt_entry_t entry);
    43 extern void itc_mapping_insert(__address va, asid_t asid, vhpt_entry_t entry);
     41/** Data and instruction Translation Register indices. */
     42#define DTR_KERNEL      0
     43#define ITR_KERNEL      0
     44#define DTR_KSTACK      1
     45
     46/** Portion of TLB insertion format data structure. */
     47union tlb_entry {
     48        __u64 word[2];
     49        struct {
     50                /* Word 0 */
     51                unsigned p : 1;                 /**< Present. */
     52                unsigned : 1;
     53                unsigned ma : 3;                /**< Memory attribute. */
     54                unsigned a : 1;                 /**< Accessed. */
     55                unsigned d : 1;                 /**< Dirty. */
     56                unsigned pl : 2;                /**< Privilege level. */
     57                unsigned ar : 3;                /**< Access rights. */
     58                unsigned long long ppn : 38;    /**< Physical Page Number, a.k.a. PFN. */
     59                unsigned : 2;
     60                unsigned ed : 1;
     61                unsigned ig1 : 11;
     62
     63                /* Word 1 */
     64                unsigned : 2;
     65                unsigned ps : 6;                /**< Page size will be 2^ps. */
     66                unsigned key : 24;              /**< Protection key, unused. */
     67                unsigned : 32;
     68        } __attribute__ ((packed));
     69} __attribute__ ((packed));
     70typedef union tlb_entry tlb_entry_t;
     71
     72extern void tc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtc);
     73extern void dtc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry);
     74extern void itc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry);
    4475
    4576extern void tr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr);
    4677extern void dtr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr);
    4778extern void itr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr);
     79
     80extern void dtlb_mapping_insert(__address page, __address frame, bool dtr, index_t tr);
    4881
    4982extern void alternate_instruction_tlb_fault(__u64 vector, struct exception_regdump *pstate);
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