Changeset a016b63 in mainline for arch/mips32/include

Timestamp:

2005-10-10T20:26:02Z (20 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

a783ca4

Parents:

e0cdb7b6

Message:

Small improvement in pte_t type definition.

Location:

arch/mips32/include

Files:

• mm/page.h (modified) (3 diffs)
• mm/tlb.h (modified) (4 diffs)
• types.h (modified) (1 diff)

arch/mips32/include/mm/page.h

@@ -63 +63 @@
 #define SET_PTL0_ADDRESS_ARCH(ptl0)             (PTL0 = (pte_t *)(ptl0))
 
-#define GET_PTL1_ADDRESS_ARCH(ptl0, i)          (((pte_t *)(ptl0))[(i)].pfn<<12)
+#define GET_PTL1_ADDRESS_ARCH(ptl0, i)          (((pte_t *)(ptl0))[(i)].lo.pfn<<12)
 #define GET_PTL2_ADDRESS_ARCH(ptl1, i)          (ptl1)
 #define GET_PTL3_ADDRESS_ARCH(ptl2, i)          (ptl2)
-#define GET_FRAME_ADDRESS_ARCH(ptl3, i)         (((pte_t *)(ptl3))[(i)].pfn<<12)
+#define GET_FRAME_ADDRESS_ARCH(ptl3, i)         (((pte_t *)(ptl3))[(i)].lo.pfn<<12)
 
-#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)       (((pte_t *)(ptl0))[(i)].pfn = (a)>>12)
+#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)       (((pte_t *)(ptl0))[(i)].lo.pfn = (a)>>12)
 #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
 #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
-#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)      (((pte_t *)(ptl3))[(i)].pfn = (a)>>12)
+#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)      (((pte_t *)(ptl3))[(i)].lo.pfn = (a)>>12)
 
 #define GET_PTL1_FLAGS_ARCH(ptl0, i)            get_pt_flags((pte_t *)(ptl0), (index_t)(i))
@@ -95 +95 @@
         
         return (
-                ((p->c>PAGE_UNCACHED)<<PAGE_CACHEABLE_SHIFT) |
-                ((!p->v)<<PAGE_PRESENT_SHIFT) |
+                ((p->lo.c>PAGE_UNCACHED)<<PAGE_CACHEABLE_SHIFT) |
+                ((!p->lo.v)<<PAGE_PRESENT_SHIFT) |
                 (1<<PAGE_USER_SHIFT) |
                 (1<<PAGE_READ_SHIFT) |
@@ -109 +109 @@
         pte_t *p = &pt[i];
         
-        p->c = (flags & PAGE_CACHEABLE) != 0 ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
-        p->v = !(flags & PAGE_NOT_PRESENT);
+        p->lo.c = (flags & PAGE_CACHEABLE) != 0 ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
+        p->lo.v = !(flags & PAGE_NOT_PRESENT);
         p->w = (flags & PAGE_WRITE) != 0;
 }

arch/mips32/include/mm/tlb.h

@@ -31 +31 @@
 
 #include <arch/exception.h>
+#include <typedefs.h>
 
 #define TLB_SIZE        48
@@ -41 +42 @@
 #define PAGE_UNCACHED                   2
 #define PAGE_CACHEABLE_EXC_WRITE        5
+
+typedef union entry_lo entry_lo_t;
+typedef union entry_hi entry_hi_t;
+typedef union page_mask page_mask_t;
+typedef union index tlb_index_t;
 
 union entry_lo {
@@ -54 +60 @@
 };
 
-struct pte {
-        unsigned g : 1;         /* global bit */
-        unsigned v : 1;         /* valid bit */
-        unsigned d : 1;         /* dirty/write-protect bit */
-        unsigned c : 3;         /* cache coherency attribute */
-        unsigned pfn : 24;      /* frame number */
-        unsigned w : 1;         /* writable */
-        unsigned a : 1;         /* accessed */
-} __attribute__ ((packed));
+union pte {
+        entry_lo_t lo;
+        struct {
+                unsigned : 30;
+                unsigned w : 1;         /* writable */
+                unsigned a : 1;         /* accessed */
+        } __attribute__ ((packed));
+};
 
 union entry_hi {
@@ -90 +95 @@
         __u32 value;
 };
-
-typedef union entry_lo entry_lo_t;
-typedef union entry_hi entry_hi_t;
-typedef union page_mask page_mask_t;
-typedef union index tlb_index_t;
 
 /** Probe TLB for Matching Entry

arch/mips32/include/types.h

@@ -50 +50 @@
 typedef __u32 __native;
 
-typedef struct pte pte_t;
+typedef union pte pte_t;
 
 #endif