Index: kernel/arch/ia64/include/arch.h =================================================================== --- kernel/arch/ia64/include/arch.h (revision 0fd9b3513b2c0cfce8b0c99e0acbaf3470c1bc80) +++ kernel/arch/ia64/include/arch.h (revision 9f0fb84554fbd63dc9ce4dc9ce31b209431459f9) @@ -36,6 +36,4 @@ #define KERN_ia64_ARCH_H_ -#include - extern void arch_pre_main(void); Index: kernel/arch/ia64/include/asm.h =================================================================== --- kernel/arch/ia64/include/asm.h (revision 0fd9b3513b2c0cfce8b0c99e0acbaf3470c1bc80) +++ kernel/arch/ia64/include/asm.h (revision 9f0fb84554fbd63dc9ce4dc9ce31b209431459f9) @@ -39,20 +39,23 @@ #include #include +#include #include -#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL - #define IO_SPACE_BOUNDARY ((void *) (64 * 1024)) +/** Map the I/O port address to a legacy I/O address. */ +NO_TRACE static inline uintptr_t p2a(volatile void *p) +{ + uintptr_t prt = (uintptr_t) p; + + return legacyio_virt_base + (((prt >> 2) << 12) | (prt & 0xfff)); +} + NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v) { - if (port < (ioport8_t *) IO_SPACE_BOUNDARY) { - uintptr_t prt = (uintptr_t) port; - - *((ioport8_t *) (IA64_IOSPACE_ADDRESS + - ((prt & 0xfff) | ((prt >> 2) << 12)))) = v; - } else { + if (port < (ioport8_t *) IO_SPACE_BOUNDARY) + *((ioport8_t *) p2a(port)) = v; + else *port = v; - } asm volatile ( @@ -64,12 +67,8 @@ NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v) { - if (port < (ioport16_t *) IO_SPACE_BOUNDARY) { - uintptr_t prt = (uintptr_t) port; - - *((ioport16_t *) (IA64_IOSPACE_ADDRESS + - ((prt & 0xfff) | ((prt >> 2) << 12)))) = v; - } else { + if (port < (ioport16_t *) IO_SPACE_BOUNDARY) + *((ioport16_t *) p2a(port)) = v; + else *port = v; - } asm volatile ( @@ -81,12 +80,8 @@ NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v) { - if (port < (ioport32_t *) IO_SPACE_BOUNDARY) { - uintptr_t prt = (uintptr_t) port; - - *((ioport32_t *) (IA64_IOSPACE_ADDRESS + - ((prt & 0xfff) | ((prt >> 2) << 12)))) = v; - } else { + if (port < (ioport32_t *) IO_SPACE_BOUNDARY) + *((ioport32_t *) p2a(port)) = v; + else *port = v; - } asm volatile ( @@ -105,12 +100,8 @@ ); - if (port < (ioport8_t *) IO_SPACE_BOUNDARY) { - uintptr_t prt = (uintptr_t) port; - - v = *((ioport8_t *) (IA64_IOSPACE_ADDRESS + - ((prt & 0xfff) | ((prt >> 2) << 12)))); - } else { + if (port < (ioport8_t *) IO_SPACE_BOUNDARY) + v = *((ioport8_t *) p2a(port)); + else v = *port; - } return v; @@ -126,12 +117,8 @@ ); - if (port < (ioport16_t *) IO_SPACE_BOUNDARY) { - uintptr_t prt = (uintptr_t) port; - - v = *((ioport16_t *) (IA64_IOSPACE_ADDRESS + - ((prt & 0xfff) | ((prt >> 2) << 12)))); - } else { + if (port < (ioport16_t *) IO_SPACE_BOUNDARY) + v = *((ioport16_t *) p2a(port)); + else v = *port; - } return v; @@ -147,12 +134,8 @@ ); - if (port < (ioport32_t *) IO_SPACE_BOUNDARY) { - uintptr_t prt = (uintptr_t) port; - - v = *((ioport32_t *) (IA64_IOSPACE_ADDRESS + - ((prt & 0xfff) | ((prt >> 2) << 12)))); - } else { + if (port < (ioport32_t *) IO_SPACE_BOUNDARY) + v = *((ioport32_t *) p2a(port)); + else v = *port; - } return v; Index: kernel/arch/ia64/include/legacyio.h =================================================================== --- kernel/arch/ia64/include/legacyio.h (revision 9f0fb84554fbd63dc9ce4dc9ce31b209431459f9) +++ kernel/arch/ia64/include/legacyio.h (revision 9f0fb84554fbd63dc9ce4dc9ce31b209431459f9) @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2011 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup ia64 + * @{ + */ +/** @file + */ + +#ifndef KERN_ia64_LEGACYIO_H_ +#define KERN_ia64_LEGACYIO_H_ + +#include + +#define LEGACYIO_PHYS_BASE 0x00000FFFFC000000ULL + +/* Legacy I/O space - static uspace address, FIXME */ +#define LEGACYIO_USER_BASE 0x0001000000000000ULL + +#define LEGACYIO_PAGE_WIDTH 26 /* 64M */ +#define LEGACYIO_SINGLE_PAGE_WIDTH 12 /* 4K */ + +#define LEGACYIO_SIZE (1ULL << LEGACYIO_PAGE_WIDTH) + +extern uintptr_t legacyio_virt_base; + +#endif + +/** @} + */ Index: kernel/arch/ia64/include/mm/page.h =================================================================== --- kernel/arch/ia64/include/mm/page.h (revision 0fd9b3513b2c0cfce8b0c99e0acbaf3470c1bc80) +++ kernel/arch/ia64/include/mm/page.h (revision 9f0fb84554fbd63dc9ce4dc9ce31b209431459f9) @@ -43,24 +43,5 @@ /** Bit width of the TLB-locked portion of kernel address space. */ -#define KERNEL_PAGE_WIDTH 28 /* 256M */ -#define IO_PAGE_WIDTH 26 /* 64M */ -#define FW_PAGE_WIDTH 28 /* 256M */ - -#define USPACE_IO_PAGE_WIDTH 12 /* 4K */ - - -/* - * Statically mapped IO spaces - offsets to 0xe...00 of virtual addresses - * because of "minimal virtual bits implemented is 51" it is possible to - * have values up to 0x0007000000000000 - */ - -/* Firmware area (bellow 4GB in phys mem) */ -#define FW_OFFSET 0x00000000F0000000 // FIXME: [non-ident] -/* Legacy IO space */ -#define IO_OFFSET 0x0001000000000000 // FIXME: [non-ident] -/* Videoram - now mapped to 0 as VGA text mode vram on 0xb8000 */ -#define VIO_OFFSET 0x0002000000000000 // FIXME: [non-ident] - +#define KERNEL_PAGE_WIDTH 28 /* 256M */ #define PPN_SHIFT 12 Index: kernel/arch/ia64/src/ia64.c =================================================================== --- kernel/arch/ia64/src/ia64.c (revision 0fd9b3513b2c0cfce8b0c99e0acbaf3470c1bc80) +++ kernel/arch/ia64/src/ia64.c (revision 9f0fb84554fbd63dc9ce4dc9ce31b209431459f9) @@ -45,4 +45,5 @@ #include #include +#include #include #include @@ -51,4 +52,9 @@ #include #include +#include + +#ifdef MACHINE_ski +#include +#endif /* NS16550 as a COM 1 */ @@ -58,4 +64,5 @@ static uint64_t iosapic_base = 0xfec00000; +uintptr_t legacyio_virt_base = 0; /** Performs ia64-specific initialization before main_bsp() is called. */ @@ -80,5 +87,5 @@ static void iosapic_init(void) { - uint64_t IOSAPIC = PA2KA((sysarg_t)(iosapic_base)) | FW_OFFSET; + uintptr_t IOSAPIC = hw_map(iosapic_base, PAGE_SIZE); int i; @@ -107,4 +114,7 @@ { if (config.cpu_active == 1) { + /* Map the page with legacy I/O. */ + legacyio_virt_base = hw_map(LEGACYIO_PHYS_BASE, LEGACYIO_SIZE); + iosapic_init(); irq_init(INR_COUNT, INR_COUNT); @@ -113,6 +123,5 @@ } -void arch_post_cpu_init(void) -{ +void arch_post_cpu_init(void){ } @@ -202,5 +211,5 @@ sysinfo_set_item_val("ia64_iospace", NULL, true); sysinfo_set_item_val("ia64_iospace.address", NULL, true); - sysinfo_set_item_val("ia64_iospace.address.virtual", NULL, IO_OFFSET); + sysinfo_set_item_val("ia64_iospace.address.virtual", NULL, LEGACYIO_USER_BASE); } Index: kernel/arch/ia64/src/mm/tlb.c =================================================================== --- kernel/arch/ia64/src/mm/tlb.c (revision 0fd9b3513b2c0cfce8b0c99e0acbaf3470c1bc80) +++ kernel/arch/ia64/src/mm/tlb.c (revision 9f0fb84554fbd63dc9ce4dc9ce31b209431459f9) @@ -52,6 +52,5 @@ #include #include - -#define IO_FRAME_BASE 0xFFFFC000000 +#include /** Invalidate all TLB entries. */ @@ -530,16 +529,16 @@ static int try_memmap_io_insertion(uintptr_t va, istate_t *istate) { - if ((va >= IO_OFFSET ) && (va < IO_OFFSET + (1 << IO_PAGE_WIDTH))) { + if ((va >= LEGACYIO_USER_BASE) && (va < LEGACYIO_USER_BASE + (1 << LEGACYIO_PAGE_WIDTH))) { if (TASK) { - uint64_t io_page = (va & ((1 << IO_PAGE_WIDTH) - 1)) >> - USPACE_IO_PAGE_WIDTH; + uint64_t io_page = (va & ((1 << LEGACYIO_PAGE_WIDTH) - 1)) >> + LEGACYIO_SINGLE_PAGE_WIDTH; if (is_io_page_accessible(io_page)) { uint64_t page, frame; - page = IO_OFFSET + - (1 << USPACE_IO_PAGE_WIDTH) * io_page; - frame = IO_FRAME_BASE + - (1 << USPACE_IO_PAGE_WIDTH) * io_page; + page = LEGACYIO_USER_BASE + + (1 << LEGACYIO_SINGLE_PAGE_WIDTH) * io_page; + frame = LEGACYIO_PHYS_BASE + + (1 << LEGACYIO_SINGLE_PAGE_WIDTH) * io_page; tlb_entry_t entry; @@ -555,5 +554,5 @@ entry.ar = AR_READ | AR_WRITE; entry.ppn = frame >> PPN_SHIFT; - entry.ps = USPACE_IO_PAGE_WIDTH; + entry.ps = LEGACYIO_SINGLE_PAGE_WIDTH; dtc_mapping_insert(page, TASK->as->asid, entry); Index: kernel/arch/ia64/src/start.S =================================================================== --- kernel/arch/ia64/src/start.S (revision 0fd9b3513b2c0cfce8b0c99e0acbaf3470c1bc80) +++ kernel/arch/ia64/src/start.S (revision 9f0fb84554fbd63dc9ce4dc9ce31b209431459f9) @@ -38,7 +38,4 @@ #define KERNEL_TRANSLATION_I 0x0010000000000661 #define KERNEL_TRANSLATION_D 0x0010000000000661 -#define KERNEL_TRANSLATION_VIO 0x0010000000000671 // FIXME: [non-ident] -#define KERNEL_TRANSLATION_IO 0x00100FFFFC000671 // FIXME: [non-ident] -#define KERNEL_TRANSLATION_FW 0x00100000F0000671 // FIXME: [non-ident] .section K_TEXT_START, "ax" @@ -88,39 +85,5 @@ itr.d dtr[r0] = r10 - movl r7 = 1 - movl r8 = (VRN_KERNEL << VRN_SHIFT) | VIO_OFFSET - mov cr.ifa = r8 - movl r10 = (KERNEL_TRANSLATION_VIO) - itr.d dtr[r7] = r10 - - mov r11 = cr.itir - movl r10 = ~0xfc - and r10 = r10, r11 - movl r11 = (IO_PAGE_WIDTH << PS_SHIFT) - or r10 = r10, r11 - mov cr.itir = r10 - - movl r7 = 2 - movl r8 = (VRN_KERNEL << VRN_SHIFT) | IO_OFFSET - mov cr.ifa = r8 - movl r10 = (KERNEL_TRANSLATION_IO) - itr.d dtr[r7] = r10 - - # Setup mapping for firmware area (also SAPIC) - - mov r11 = cr.itir - movl r10 = ~0xfc - and r10 = r10, r11 - movl r11 = (FW_PAGE_WIDTH << PS_SHIFT) - or r10 = r10, r11 - mov cr.itir = r10 - - movl r7 = 3 - movl r8 = (VRN_KERNEL << VRN_SHIFT) | FW_OFFSET - mov cr.ifa = r8 - movl r10 = (KERNEL_TRANSLATION_FW) - itr.d dtr[r7] = r10 - - # Initialize DSR + # Initialize DCR movl r10 = (DCR_DP_MASK | DCR_DK_MASK | DCR_DX_MASK | DCR_DR_MASK | DCR_DA_MASK | DCR_DD_MASK | DCR_LC_MASK)