Index: boot/arch/arm32/loader/asm.h =================================================================== --- boot/arch/arm32/loader/asm.h (revision c03ee1c304c982b593d8043411e6b003dd1c155a) +++ boot/arch/arm32/loader/asm.h (revision 9ec12fd02d7d7194fc06b0096c8add4d566cfe96) @@ -63,11 +63,10 @@ * @param bootinfo_size Size of the bootinfo structure. */ -extern void jump_to_kernel(void *entry, void *bootinfo, unsigned int bootinfo_size) __attribute__((noreturn)); +extern void jump_to_kernel(void *entry, void *bootinfo, + unsigned int bootinfo_size) __attribute__((noreturn)); #endif - /** @} */ - Index: boot/arch/arm32/loader/main.h =================================================================== --- boot/arch/arm32/loader/main.h (revision c03ee1c304c982b593d8043411e6b003dd1c155a) +++ boot/arch/arm32/loader/main.h (revision 9ec12fd02d7d7194fc06b0096c8add4d566cfe96) @@ -69,5 +69,4 @@ - extern void bootstrap(void); Index: boot/arch/arm32/loader/mm.c =================================================================== --- boot/arch/arm32/loader/mm.c (revision c03ee1c304c982b593d8043411e6b003dd1c155a) +++ boot/arch/arm32/loader/mm.c (revision 9ec12fd02d7d7194fc06b0096c8add4d566cfe96) @@ -43,23 +43,24 @@ * Will be readable/writable by kernel with no access from user mode. * Will belong to domain 0. No cache or buffering is enabled. - * - * @param pte Section entry to initialize. - * @param frame First frame in the section (frame number). + * + * @param pte Section entry to initialize. + * @param frame First frame in the section (frame number). * - * @note If frame is not 1MB aligned, first lower 1MB aligned frame will be used. - */ -static void init_pte_level0_section(pte_level0_section_t* pte, unsigned int frame) + * @note If frame is not 1MB aligned, first lower 1MB aligned frame will be + * used. + */ +static void init_pte_level0_section(pte_level0_section_t* pte, + unsigned int frame) { - pte->descriptor_type = PTE_DESCRIPTOR_SECTION; - pte->bufferable = 0; - pte->cacheable = 0; - pte->impl_specific = 0; - pte->domain = 0; + pte->descriptor_type = PTE_DESCRIPTOR_SECTION; + pte->bufferable = 0; + pte->cacheable = 0; + pte->impl_specific = 0; + pte->domain = 0; pte->should_be_zero_1 = 0; - pte->access_permission = PTE_AP_USER_NO_KERNEL_RW; + pte->access_permission = PTE_AP_USER_NO_KERNEL_RW; pte->should_be_zero_2 = 0; pte->section_base_addr = frame; } - /** Initializes page table used while booting the kernel. */ @@ -69,16 +70,17 @@ const unsigned int first_kernel_page = ADDR2PFN(PA2KA(0)); - // create 1:1 virtual-physical mapping (in lower 2GB) + /* Create 1:1 virtual-physical mapping (in lower 2GB). */ for (i = 0; i < first_kernel_page; i++) { init_pte_level0_section(&page_table[i], i); } - // create 1:1 virtual-physical mapping in kernel space (upper 2GB), - // physical addresses start from 0 + /* + * Create 1:1 virtual-physical mapping in kernel space (upper 2GB), + * physical addresses start from 0. + */ for (i = first_kernel_page; i < PTL0_ENTRIES; i++) { init_pte_level0_section(&page_table[i], i - first_kernel_page); } } - /** Starts the MMU - initializes page table and enables paging. */ @@ -89,6 +91,5 @@ } - /** @} */ - + Index: boot/arch/arm32/loader/mm.h =================================================================== --- boot/arch/arm32/loader/mm.h (revision c03ee1c304c982b593d8043411e6b003dd1c155a) +++ boot/arch/arm32/loader/mm.h (revision 9ec12fd02d7d7194fc06b0096c8add4d566cfe96) @@ -1,4 +1,5 @@ /* - * Copyright (c) 2007 Pavel Jancik, Michal Kebrt + * Copyright (c) 2007 Pavel Jancik + * Copyright (c) 2007 Michal Kebrt * All rights reserved. * @@ -34,7 +35,8 @@ * @brief Memory management used while booting the kernel. * - * So called "section" paging is used while booting the kernel. The term "section" - * comes from the ARM architecture specification and stands for the following: - * one-level paging, 1MB sized pages, 4096 entries in the page table. + * So called "section" paging is used while booting the kernel. The term + * "section" comes from the ARM architecture specification and stands for the + * following: one-level paging, 1MB sized pages, 4096 entries in the page + * table. */ @@ -50,38 +52,40 @@ /** Frame width. */ -#define FRAME_WIDTH 20 +#define FRAME_WIDTH 20 /** Frame size. */ -#define FRAME_SIZE (1 << FRAME_WIDTH) +#define FRAME_SIZE (1 << FRAME_WIDTH) -/** Page size in 2-level paging which is switched on later after the kernel initialization. */ -#define KERNEL_PAGE_SIZE (1 << 12) +/** Page size in 2-level paging which is switched on later after the kernel + * initialization. + */ +#define KERNEL_PAGE_SIZE (1 << 12) #ifndef __ASM__ /** Converts kernel address to physical address. */ -# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) +# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) /** Converts physical address to kernel address. */ -# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) +# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) #else -# define KA2PA(x) ((x) - 0x80000000) -# define PA2KA(x) ((x) + 0x80000000) +# define KA2PA(x) ((x) - 0x80000000) +# define PA2KA(x) ((x) + 0x80000000) #endif /** Number of entries in PTL0. */ -#define PTL0_ENTRIES (1<<12) /* 4096 */ +#define PTL0_ENTRIES (1 << 12) /* 4096 */ /** Size of an entry in PTL0. */ -#define PTL0_ENTRY_SIZE 4 +#define PTL0_ENTRY_SIZE 4 /** Returns number of frame the address belongs to. */ -#define ADDR2PFN( addr ) ( ((uintptr_t)(addr)) >> FRAME_WIDTH ) +#define ADDR2PFN(addr) (((uintptr_t) (addr)) >> FRAME_WIDTH) /** Describes "section" page table entry (one-level paging with 1MB sized pages). */ -#define PTE_DESCRIPTOR_SECTION 0x2 +#define PTE_DESCRIPTOR_SECTION 0x2 /** Page table access rights: user - no access, kernel - read/write. */ -#define PTE_AP_USER_NO_KERNEL_RW 0x1 +#define PTE_AP_USER_NO_KERNEL_RW 0x1 @@ -89,21 +93,23 @@ -/** Page table level 0 entry - "section" format is used (one-level paging, 1MB sized - * pages). Used only while booting the kernel. +/** Page table level 0 entry - "section" format is used (one-level paging, 1MB + * sized pages). Used only while booting the kernel. */ typedef struct { - unsigned descriptor_type : 2; - unsigned bufferable : 1; - unsigned cacheable : 1; - unsigned impl_specific : 1; - unsigned domain : 4; - unsigned should_be_zero_1 : 1; - unsigned access_permission : 2; - unsigned should_be_zero_2 : 8; - unsigned section_base_addr : 12; + unsigned descriptor_type : 2; + unsigned bufferable : 1; + unsigned cacheable : 1; + unsigned impl_specific : 1; + unsigned domain : 4; + unsigned should_be_zero_1 : 1; + unsigned access_permission : 2; + unsigned should_be_zero_2 : 8; + unsigned section_base_addr : 12; } __attribute__ ((packed)) pte_level0_section_t; -/** Page table that holds 1:1 virtual to physical mapping used while booting the kernel. */ +/** Page table that holds 1:1 virtual to physical mapping used while booting the + * kernel. + */ extern pte_level0_section_t page_table[PTL0_ENTRIES]; @@ -118,17 +124,17 @@ */ asm volatile ( - // behave as a client of domains - "ldr r0, =0x55555555 \n" - "mcr p15, 0, r0, c3, c0, 0 \n" + /* behave as a client of domains */ + "ldr r0, =0x55555555\n" + "mcr p15, 0, r0, c3, c0, 0\n" - // current settings - "mrc p15, 0, r0, c1, c0, 0 \n" + /* current settings */ + "mrc p15, 0, r0, c1, c0, 0\n" - // mask to enable paging - "ldr r1, =0x00000001 \n" - "orr r0, r0, r1 \n" + /* mask to enable paging */ + "ldr r1, =0x00000001\n" + "orr r0, r0, r1\n" - // store settings - "mcr p15, 0, r0, c1, c0, 0 \n" + /* store settings */ + "mcr p15, 0, r0, c1, c0, 0\n" : : @@ -144,9 +150,9 @@ static inline void set_ptl0_address(pte_level0_section_t* pt) { - asm volatile ( - "mcr p15, 0, %0, c2, c0, 0 \n" + asm volatile ( + "mcr p15, 0, %0, c2, c0, 0\n" : - : "r"(pt) - ); + : "r" (pt) + ); } Index: boot/arch/arm32/loader/print/gxemul.c =================================================================== --- boot/arch/arm32/loader/print/gxemul.c (revision c03ee1c304c982b593d8043411e6b003dd1c155a) +++ boot/arch/arm32/loader/print/gxemul.c (revision 9ec12fd02d7d7194fc06b0096c8add4d566cfe96) @@ -49,5 +49,5 @@ static void putc(char ch) { - *((volatile char *)PUTC_ADDRESS) = ch; + *((volatile char *) PUTC_ADDRESS) = ch; } Index: boot/arch/arm32/loader/types.h =================================================================== --- boot/arch/arm32/loader/types.h (revision c03ee1c304c982b593d8043411e6b003dd1c155a) +++ boot/arch/arm32/loader/types.h (revision 9ec12fd02d7d7194fc06b0096c8add4d566cfe96) @@ -58,3 +58,2 @@ /** @} */ - Index: boot/arch/mips32/loader/asm.h =================================================================== --- boot/arch/mips32/loader/asm.h (revision c03ee1c304c982b593d8043411e6b003dd1c155a) +++ boot/arch/mips32/loader/asm.h (revision 9ec12fd02d7d7194fc06b0096c8add4d566cfe96) @@ -27,11 +27,11 @@ */ -#ifndef __ASM_H__ -#define __ASM_H__ +#ifndef BOOT_mips32_ASM_H_ +#define BOOT_mips32_ASM_H_ #define PAGE_SIZE 16384 #define PAGE_WIDTH 14 -#define memcpy(dst, src, cnt) __builtin_memcpy((dst), (src), (cnt)) +#define memcpy(dst, src, cnt) __builtin_memcpy((dst), (src), (cnt)) void jump_to_kernel(void *entry, void *bootinfo, unsigned int bootinfo_size) __attribute__((noreturn)); Index: boot/arch/mips32/loader/main.h =================================================================== --- boot/arch/mips32/loader/main.h (revision c03ee1c304c982b593d8043411e6b003dd1c155a) +++ boot/arch/mips32/loader/main.h (revision 9ec12fd02d7d7194fc06b0096c8add4d566cfe96) @@ -27,6 +27,6 @@ */ -#ifndef __MAIN_H__ -#define __MAIN_H__ +#ifndef BOOT_mips32_MAIN_H_ +#define BOOT_mips32_MAIN_H_ /** Align to the nearest higher address. Index: boot/arch/mips32/loader/msim.h =================================================================== --- boot/arch/mips32/loader/msim.h (revision c03ee1c304c982b593d8043411e6b003dd1c155a) +++ boot/arch/mips32/loader/msim.h (revision 9ec12fd02d7d7194fc06b0096c8add4d566cfe96) @@ -27,6 +27,6 @@ */ -#ifndef __MSIM_H__ -#define __MSIM_H__ +#ifndef BOOT_mips32_MSIM_H_ +#define BOOT_mips32_MSIM_H_ extern void init(void); Index: boot/arch/mips32/loader/regname.h =================================================================== --- boot/arch/mips32/loader/regname.h (revision c03ee1c304c982b593d8043411e6b003dd1c155a) +++ boot/arch/mips32/loader/regname.h (revision 9ec12fd02d7d7194fc06b0096c8add4d566cfe96) @@ -27,6 +27,6 @@ */ -#ifndef __mips32_REGNAME_H_ -#define __mips32_REGNAME_H_ +#ifndef BOOT_mips32_REGNAME_H_ +#define BOOT_mips32_REGNAME_H_ #define zero 0 @@ -86,4 +86,3 @@ #define eepc 30 - #endif /* _REGNAME_H_ */ Index: boot/arch/mips32/loader/types.h =================================================================== --- boot/arch/mips32/loader/types.h (revision c03ee1c304c982b593d8043411e6b003dd1c155a) +++ boot/arch/mips32/loader/types.h (revision 9ec12fd02d7d7194fc06b0096c8add4d566cfe96) @@ -27,6 +27,6 @@ */ -#ifndef TYPES_H__ -#define TYPES_H__ +#ifndef BOOT_mips32_TYPES_H_ +#define BOOT_mips32_TYPES_H_ #include