Index: uspace/lib/c/arch/arm32/include/libarch/fibril.h
===================================================================
--- uspace/lib/c/arch/arm32/include/libarch/fibril.h	(revision 38d8849c5dae9664aadfb5dfe635e66fd4bcb908)
+++ uspace/lib/c/arch/arm32/include/libarch/fibril.h	(revision 9d8307a94aa6d903e4fcaa8ae5c22e2fa48fddfb)
@@ -62,5 +62,5 @@
 		(c)->pc = (sysarg_t) (_pc); \
 		(c)->sp = ((sysarg_t) (stack)) + (size) - SP_DELTA; \
-		(c)->tls = ((sysarg_t)(ptls)) + sizeof(tcb_t) + ARM_TP_OFFSET; \
+		(c)->tls = ((sysarg_t)(ptls)) + ARCH_TP_OFFSET; \
 		(c)->fp = 0; \
 	} while (0)
Index: uspace/lib/c/arch/arm32/include/libarch/tls.h
===================================================================
--- uspace/lib/c/arch/arm32/include/libarch/tls.h	(revision 38d8849c5dae9664aadfb5dfe635e66fd4bcb908)
+++ uspace/lib/c/arch/arm32/include/libarch/tls.h	(revision 9d8307a94aa6d903e4fcaa8ae5c22e2fa48fddfb)
@@ -42,5 +42,5 @@
 
 /** Offsets for accessing thread-local variables are shifted 8 bytes higher. */
-#define ARM_TP_OFFSET  (-8)
+#define ARCH_TP_OFFSET  (sizeof(tcb_t) - 8)
 
 /** TCB (Thread Control Block) struct.
@@ -53,36 +53,15 @@
 } tcb_t;
 
-
-/** Sets TLS address to the r9 register.
- *
- *  @param tcb		TCB (TLS starts behind)
- */
-static inline void __tcb_set(tcb_t *tcb)
+static inline void *__tcb_raw_get(void)
 {
-	uint8_t *tls = (uint8_t *) tcb;
-	tls += sizeof(tcb_t) + ARM_TP_OFFSET;
-	asm volatile (
-	    "mov r9, %0"
-	    :
-	    : "r" (tls)
-	);
+	uint8_t *ret;
+	asm volatile ("mov %0, r9" : "=r" (ret));
+	return ret;
 }
 
-
-/** Returns TCB address.
- *
- * @return		TCB address (starts before TLS which address is stored
- * 			in r9 register).
- */
-static inline tcb_t *__tcb_get(void)
+static inline void __tcb_raw_set(void *tls)
 {
-	uint8_t *ret;
-	asm volatile (
-	    "mov %0, r9"
-	    : "=r" (ret)
-	);
-	return (tcb_t *) (ret - ARM_TP_OFFSET - sizeof(tcb_t));
+	asm volatile ("mov r9, %0" :: "r" (tls));
 }
-
 
 /** Returns TLS address stored.