Index: kernel/arch/sparc32/include/arch/asm.h
===================================================================
--- kernel/arch/sparc32/include/arch/asm.h	(revision d18ad6103e1a409e3a8a0703b5864b7ddc51f57a)
+++ kernel/arch/sparc32/include/arch/asm.h	(revision 9be30cdf4e3175cfd8137b54849120ce309a35d5)
@@ -161,4 +161,18 @@
 	pil = psr.pil;
 	
+	psr.pil = 0x00;
+	psr_write(psr.value);
+	
+	return pil;
+}
+
+NO_TRACE static inline ipl_t interrupts_disable(void)
+{
+	psr_reg_t psr;
+	psr.value = psr_read();
+	
+	ipl_t pil;
+	pil = psr.pil;
+	
 	psr.pil = 0x0f;
 	psr_write(psr.value);
@@ -167,18 +181,4 @@
 }
 
-NO_TRACE static inline ipl_t interrupts_disable(void)
-{
-	psr_reg_t psr;
-	psr.value = psr_read();
-	
-	ipl_t pil;
-	pil = psr.pil;
-	
-	psr.pil = 0;
-	psr_write(psr.value);
-	
-	return pil;
-}
-
 NO_TRACE static inline void interrupts_restore(ipl_t ipl)
 {
@@ -200,5 +200,5 @@
 	psr_reg_t psr;
 	psr.value = psr_read();
-	return psr.pil == 0;
+	return (psr.pil == 0x0f);
 }
 
Index: kernel/arch/sparc32/include/arch/atomic.h
===================================================================
--- kernel/arch/sparc32/include/arch/atomic.h	(revision d18ad6103e1a409e3a8a0703b5864b7ddc51f57a)
+++ kernel/arch/sparc32/include/arch/atomic.h	(revision 9be30cdf4e3175cfd8137b54849120ce309a35d5)
@@ -37,4 +37,5 @@
 
 #include <typedefs.h>
+#include <arch/asm.h>
 #include <arch/barrier.h>
 #include <preemption.h>
@@ -47,6 +48,8 @@
     REQUIRES(val->count < ATOMIC_COUNT_MAX)
 {
-	// FIXME TODO
+	// FIXME: Isn't there any intrinsic atomic operation?
+	ipl_t ipl = interrupts_disable();
 	val->count++;
+	interrupts_restore(ipl);
 }
 
@@ -56,6 +59,8 @@
     REQUIRES(val->count > ATOMIC_COUNT_MIN)
 {
-	// FIXME TODO
+	// FIXME: Isn't there any intrinsic atomic operation?
+	ipl_t ipl = interrupts_disable();
 	val->count--;
+	interrupts_restore(ipl);
 }
 
@@ -65,9 +70,11 @@
     REQUIRES(val->count < ATOMIC_COUNT_MAX)
 {
-	// FIXME TODO
+	// FIXME: Isn't there any intrinsic atomic operation?
 	
+	ipl_t ipl = interrupts_disable();
 	atomic_count_t prev = val->count;
 	
 	val->count++;
+	interrupts_restore(ipl);
 	return prev;
 }
@@ -78,9 +85,11 @@
     REQUIRES(val->count > ATOMIC_COUNT_MIN)
 {
-	// FIXME TODO
+	// FIXME: Isn't there any intrinsic atomic operation?
 	
+	ipl_t ipl = interrupts_disable();
 	atomic_count_t prev = val->count;
 	
 	val->count--;
+	interrupts_restore(ipl);
 	return prev;
 }
@@ -93,8 +102,14 @@
     REQUIRES_EXTENT_MUTABLE(val)
 {
-	// FIXME TODO
+	atomic_count_t prev;
+	volatile uintptr_t ptr = (uintptr_t) &val->count;
 	
-	atomic_count_t prev = val->count;
-	val->count = 1;
+	asm volatile (
+		"ldstub [%[ptr]] %[prev]\n"
+		: [prev] "=r" (prev)
+		: [ptr] "r" (ptr)
+		: "memory"
+	);
+	
 	return prev;
 }
@@ -104,9 +119,32 @@
     REQUIRES_EXTENT_MUTABLE(val)
 {
-	// FIXME TODO
+	atomic_count_t tmp1 = 0;
 	
-	do {
-		while (val->count);
-	} while (test_and_set(val));
+	volatile uintptr_t ptr = (uintptr_t) &val->count;
+	
+	preemption_disable();
+	
+	asm volatile (
+		"0:\n"
+			"ldstub %0, %1\n"
+			"tst %1\n"
+			"be 2f\n"
+			"nop\n"
+		"1:\n"
+			"ldub %0, %1\n"
+			"tst %1\n"
+			"bne 1b\n"
+			"nop\n"
+			"ba,a 0b\n"
+		"2:\n"
+		: "+m" (*((atomic_count_t *) ptr)),
+		  "+r" (tmp1)
+		: "r" (0)
+	);
+	
+	/*
+	 * Prevent critical section code from bleeding out this way up.
+	 */
+	CS_ENTER_BARRIER();
 }
 
Index: kernel/arch/sparc32/include/arch/barrier.h
===================================================================
--- kernel/arch/sparc32/include/arch/barrier.h	(revision d18ad6103e1a409e3a8a0703b5864b7ddc51f57a)
+++ kernel/arch/sparc32/include/arch/barrier.h	(revision 9be30cdf4e3175cfd8137b54849120ce309a35d5)
@@ -36,12 +36,37 @@
 #define KERN_sparc32_BARRIER_H_
 
-// FIXME TODO
+/*
+ * Provisions are made to prevent compiler from reordering instructions itself.
+ */
 
-#define CS_ENTER_BARRIER()
-#define CS_LEAVE_BARRIER()
+#define CS_ENTER_BARRIER() \
+	asm volatile ( \
+		"stbar\n" \
+		::: "memory" \
+	)
 
-#define memory_barrier()
-#define read_barrier()
-#define write_barrier()
+#define CS_LEAVE_BARRIER() \
+	asm volatile ( \
+		"stbar\n" \
+		::: "memory" \
+	)
+
+#define memory_barrier() \
+	asm volatile ( \
+		"stbar\n" \
+		::: "memory" \
+	)
+
+#define read_barrier() \
+	asm volatile ( \
+		"stbar\n" \
+		::: "memory" \
+	)
+
+#define write_barrier() \
+	asm volatile ( \
+		"stbar\n" \
+		::: "memory" \
+	)
 
 #define smc_coherence(addr)
Index: kernel/arch/sparc32/include/arch/mm/page.h
===================================================================
--- kernel/arch/sparc32/include/arch/mm/page.h	(revision d18ad6103e1a409e3a8a0703b5864b7ddc51f57a)
+++ kernel/arch/sparc32/include/arch/mm/page.h	(revision 9be30cdf4e3175cfd8137b54849120ce309a35d5)
@@ -71,5 +71,5 @@
 /* Page table sizes for each level. */
 #define PTL0_FRAMES_ARCH  1
-#define PTL1_FRAMES_ARCH  0
+#define PTL1_FRAMES_ARCH  1
 #define PTL2_FRAMES_ARCH  1
 #define PTL3_FRAMES_ARCH  1