Index: HelenOS.config
===================================================================
--- HelenOS.config	(revision df64dbcec09ca6420de2c8c0944a17482cc56d6b)
+++ HelenOS.config	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -64,5 +64,6 @@
 @ "gta02" GTA02 / Neo FreeRunner
 @ "integratorcp" Integratorcp
-@ "beagleboardxm" BeogleBoard-xM
+@ "beagleboardxm" BeagleBoard-xM
+@ "beaglebone" BeagleBone
 ! [PLATFORM=arm32] MACHINE (choice)
 
@@ -88,5 +89,5 @@
 % CPU type
 @ "cortex_a8" ARM Cortex A-8
-! [PLATFORM=arm32&MACHINE=beagleboardxm] PROCESSOR (choice)
+! [PLATFORM=arm32&(MACHINE=beagleboardxm|MACHINE=beaglebone)] PROCESSOR (choice)
 
 % CPU type
@@ -441,5 +442,5 @@
 % Output device class
 @ "generic" Monitor or serial line
-! [PLATFORM=arm32&(MACHINE=gta02|MACHINE=integratorcp|MACHINE=beagleboardxm)] CONFIG_HID_OUT (choice)
+! [PLATFORM=arm32&(MACHINE=gta02|MACHINE=integratorcp|MACHINE=beagleboardxm|MACHINE=beaglebone)] CONFIG_HID_OUT (choice)
 
 % Output device class
@@ -488,5 +489,11 @@
 ! [PLATFORM=arm32&MACHINE=gta02] CONFIG_S3C24XX_IRQC (y)
 
-% Support for TI AMDM37X on-chip UART
+% Support for TI AM335x on-chip UART
+! [(CONFIG_HID_OUT=generic|CONFIG_HID_OUT=serial)&PLATFORM=arm32&MACHINE=beaglebone] CONFIG_AM335X_UART (y/n)
+
+% Support for TI AM335x timers support
+! [PLATFORM=arm32&MACHINE=beaglebone] CONFIG_AM335X_TIMERS (y)
+
+% Support for TI AMDM37x on-chip UART
 ! [(CONFIG_HID_OUT=generic|CONFIG_HID_OUT=serial)&PLATFORM=arm32&MACHINE=beagleboardxm] CONFIG_AMDM37X_UART (y/n)
 
@@ -510,5 +517,5 @@
 
 % Serial line input module
-! [CONFIG_DSRLNIN=y|(PLATFORM=arm32&MACHINE=gta02)|(PLATFORM=arm32&MACHINE=integratorcp&CONFIG_ARM926_UART=y)|(PLATFORM=arm32&MACHINE=beagleboardxm&CONFIG_AMDM37X_UART=y)|(PLATFORM=ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y)
+! [CONFIG_DSRLNIN=y|(PLATFORM=arm32&MACHINE=gta02)|(PLATFORM=arm32&MACHINE=integratorcp&CONFIG_ARM926_UART=y)|(PLATFORM=arm32&MACHINE=beaglebone&CONFIG_AM335X_UART=y)|(PLATFORM=arm32&MACHINE=beagleboardxm&CONFIG_AMDM37X_UART=y)|(PLATFORM=ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y)
 
 % EGA support
@@ -623,7 +630,7 @@
 % uImage OS type
 @ "2" NetBSD stage 2 boot loader
-! [PLATFORM=arm32&MACHINE=beagleboardxm] UIMAGE_OS (choice)
+! [PLATFORM=arm32&(MACHINE=beagleboardxm|MACHINE=beaglebone)] UIMAGE_OS (choice)
 
 % uImage OS type
 @ "5" Linux kernel
-! [PLATFORM=arm32&MACHINE!=beagleboardxm] UIMAGE_OS (choice)
+! [PLATFORM=arm32&MACHINE!=beagleboardxm&MACHINE!=beaglebone] UIMAGE_OS (choice)
Index: boot/arch/arm32/Makefile.inc
===================================================================
--- boot/arch/arm32/Makefile.inc	(revision df64dbcec09ca6420de2c8c0944a17482cc56d6b)
+++ boot/arch/arm32/Makefile.inc	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -35,5 +35,5 @@
 endif
 
-ifeq ($(MACHINE), beagleboardxm)
+ifeq ($(MACHINE), $(filter $(MACHINE),beagleboardxm beaglebone))
 	BOOT_OUTPUT = image.boot
 	POST_OUTPUT = $(ROOT_PATH)/uImage.bin
Index: boot/arch/arm32/include/arch.h
===================================================================
--- boot/arch/arm32/include/arch.h	(revision df64dbcec09ca6420de2c8c0944a17482cc56d6b)
+++ boot/arch/arm32/include/arch.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -44,4 +44,6 @@
 #elif defined MACHINE_beagleboardxm
 #define BOOT_BASE	0x80000000
+#elif defined MACHINE_beaglebone
+#define BOOT_BASE       0x80000000
 #else
 #define BOOT_BASE	0x00000000
@@ -51,4 +53,6 @@
 
 #ifdef MACHINE_beagleboardxm
+	#define PA_OFFSET 0
+#elif defined MACHINE_beaglebone
 	#define PA_OFFSET 0
 #else
Index: boot/arch/arm32/include/main.h
===================================================================
--- boot/arch/arm32/include/main.h	(revision df64dbcec09ca6420de2c8c0944a17482cc56d6b)
+++ boot/arch/arm32/include/main.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -51,4 +51,13 @@
 #define BBXM_THR_FULL           0x00000001
 
+/** Beaglebone UART register addresses
+ *
+ * This is UART0 of AM335x CPU
+ */
+#define BBONE_SCONS_THR         0x44E09000
+#define BBONE_SCONS_SSR         0x44E09044
+
+/** Check this bit before writing (tx fifo full) */
+#define BBONE_TXFIFO_FULL       0x00000001
 
 /** GTA02 serial console UART register addresses.
Index: boot/arch/arm32/include/mm.h
===================================================================
--- boot/arch/arm32/include/mm.h	(revision df64dbcec09ca6420de2c8c0944a17482cc56d6b)
+++ boot/arch/arm32/include/mm.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -63,4 +63,9 @@
 #define BBXM_RAM_END   0xc0000000
 
+/** Start of ram memory on AM335x */
+#define AM335x_RAM_START   0x80000000
+/** End of ram memory on AM335x */
+#define AM335x_RAM_END     0xC0000000
+
 
 /* Page table level 0 entry - "section" format is used
@@ -76,5 +81,6 @@
 	unsigned int access_permission_0 : 2;
 	unsigned int tex : 3;
-	unsigned int access_permission_1 : 2;
+	unsigned int access_permission_1 : 1;
+	unsigned int shareable : 1;
 	unsigned int non_global : 1;
 	unsigned int should_be_zero_2 : 1;
Index: boot/arch/arm32/src/mm.c
===================================================================
--- boot/arch/arm32/src/mm.c	(revision df64dbcec09ca6420de2c8c0944a17482cc56d6b)
+++ boot/arch/arm32/src/mm.c	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -38,4 +38,15 @@
 #include <arch/mm.h>
 
+/** Disable the MMU */
+static void disable_paging(void)
+{
+	asm volatile (
+		"mrc p15, 0, r0, c1, c0, 0\n"
+		"bic r0, r0, #1\n"
+		"mcr p15, 0, r0, c1, c0, 0\n"
+		::: "r0"
+	);
+}
+
 /** Check if caching can be enabled for a given memory section.
  *
@@ -59,4 +70,8 @@
 	const unsigned long address = section << PTE_SECTION_SHIFT;
 	if (address >= BBXM_RAM_START && address < BBXM_RAM_END)
+		return 1;
+#elif defined MACHINE_beaglebone
+	const unsigned long address = section << PTE_SECTION_SHIFT;
+	if (address >= AM335x_RAM_START && address < AM335x_RAM_END)
 		return 1;
 #endif
@@ -88,4 +103,5 @@
 	pte->tex = 0;
 	pte->access_permission_1 = 0;
+	pte->shareable = 0;
 	pte->non_global = 0;
 	pte->should_be_zero_2 = 0;
@@ -102,18 +118,4 @@
 	for (page = 0; page < split_page; page++)
 		init_ptl0_section(&boot_pt[page], page);
-	
-	/*
-	 * Create 1:1 virtual-physical mapping in kernel space
-	 * (upper 2 GB), physical addresses start from 0.
-	 */
-	/* BeagleBoard-xM (DM37x) memory starts at 2GB border,
-	 * thus mapping only lower 2GB is not not enough.
-	 * Map entire AS 1:1 instead and hope it works. */
-	for (page = split_page; page < PTL0_ENTRIES; page++)
-#ifndef MACHINE_beagleboardxm
-		init_ptl0_section(&boot_pt[page], page - split_page);
-#else
-		init_ptl0_section(&boot_pt[page], page);
-#endif
 	
 	asm volatile (
@@ -132,5 +134,5 @@
 		"ldr r0, =0x55555555\n"
 		"mcr p15, 0, r0, c3, c0, 0\n"
-		
+
 		/* Current settings */
 		"mrc p15, 0, r0, c1, c0, 0\n"
@@ -143,6 +145,11 @@
 		
 		"orr r0, r0, r1\n"
+
+		/* Invalidate the TLB content before turning on the MMU.
+		 * ARMv7-A Reference manual, B3.10.3
+		 */
+		"mcr p15, 0, r0, c8, c7, 0\n"
 		
-		/* Store settings */
+		/* Store settings, enable the MMU */
 		"mcr p15, 0, r0, c1, c0, 0\n"
 		::: "r0", "r1"
@@ -152,4 +159,5 @@
 /** Start the MMU - initialize page table and enable paging. */
 void mmu_start() {
+	disable_paging();
 	init_boot_pt();
 	enable_paging();
Index: boot/arch/arm32/src/putchar.c
===================================================================
--- boot/arch/arm32/src/putchar.c	(revision df64dbcec09ca6420de2c8c0944a17482cc56d6b)
+++ boot/arch/arm32/src/putchar.c	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -40,4 +40,26 @@
 #include <putchar.h>
 #include <str.h>
+
+#ifdef MACHINE_beaglebone
+
+/** Send a byte to the am335x serial console.
+ *
+ * @param byte		Byte to send.
+ */
+static void scons_sendb_bbone(uint8_t byte)
+{
+	volatile uint32_t *thr =
+		(volatile uint32_t *) BBONE_SCONS_THR;
+	volatile uint32_t *ssr =
+		(volatile uint32_t *) BBONE_SCONS_SSR;
+
+	/* Wait until transmitter is empty */
+	while (*ssr & BBONE_TXFIFO_FULL);
+
+	/* Transmit byte */
+	*thr = (uint32_t) byte;
+}
+
+#endif
 
 #ifdef MACHINE_beagleboardxm
@@ -106,4 +128,7 @@
 static void scons_sendb(uint8_t byte)
 {
+#ifdef MACHINE_beaglebone
+	scons_sendb_bbone(byte);
+#endif
 #ifdef MACHINE_beagleboardxm
 	scons_sendb_bbxm(byte);
Index: defaults/arm32/beaglebone/Makefile.config
===================================================================
--- defaults/arm32/beaglebone/Makefile.config	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
+++ defaults/arm32/beaglebone/Makefile.config	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -0,0 +1,8 @@
+# Machine type
+MACHINE = beaglebone
+
+# RAM disk format
+RDFMT = fat
+
+#framebuffer
+CONFIG_FB = n
Index: kernel/arch/arm32/Makefile.inc
===================================================================
--- kernel/arch/arm32/Makefile.inc	(revision df64dbcec09ca6420de2c8c0944a17482cc56d6b)
+++ kernel/arch/arm32/Makefile.inc	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -85,4 +85,8 @@
 endif
 
+ifeq ($(MACHINE),beaglebone)
+        ARCH_SOURCES += arch/$(KARCH)/src/mach/beaglebone/beaglebone.c
+endif
+
 ifeq ($(CONFIG_PL050),y)
 	ARCH_SOURCES += genarch/src/drivers/pl050/pl050.c
Index: kernel/arch/arm32/_link.ld.in
===================================================================
--- kernel/arch/arm32/_link.ld.in	(revision df64dbcec09ca6420de2c8c0944a17482cc56d6b)
+++ kernel/arch/arm32/_link.ld.in	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -10,4 +10,6 @@
 #define KERNEL_LOAD_ADDRESS 0xb0a08000
 #elif defined MACHINE_beagleboardxm
+#define KERNEL_LOAD_ADDRESS 0x80a00000
+#elif define MACHINE_beaglebone
 #define KERNEL_LOAD_ADDRESS 0x80a00000
 #else
Index: kernel/arch/arm32/include/mach/beaglebone/beaglebone.h
===================================================================
--- kernel/arch/arm32/include/mach/beaglebone/beaglebone.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
+++ kernel/arch/arm32/include/mach/beaglebone/beaglebone.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2012 Matteo Facchinetti
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup arm32beaglebone beaglebone
+ *  @brief BeagleBone platform.
+ *  @ingroup arm32
+ * @{
+ */
+/** @file
+ *  @brief BeagleBone platform driver.
+ */
+
+#ifndef KERN_arm32_beaglebone_H_
+#define KERN_arm32_beaglebone_H_
+
+#include <arch/machine_func.h>
+
+extern struct arm_machine_ops bbone_machine_ops;
+
+#endif
+
+/** @}
+ */
+
Index: kernel/arch/arm32/include/mm/frame.h
===================================================================
--- kernel/arch/arm32/include/mm/frame.h	(revision df64dbcec09ca6420de2c8c0944a17482cc56d6b)
+++ kernel/arch/arm32/include/mm/frame.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -56,4 +56,9 @@
 #define BOOT_PAGE_TABLE_ADDRESS  0x80008000
 
+#elif defined MACHINE_beaglebone
+
+#define PHYSMEM_START_ADDR       0x80000000
+#define BOOT_PAGE_TABLE_ADDRESS  0x80008000
+
 #else
 
@@ -65,5 +70,4 @@
 #define BOOT_PAGE_TABLE_START_FRAME     (BOOT_PAGE_TABLE_ADDRESS >> FRAME_WIDTH)
 #define BOOT_PAGE_TABLE_SIZE_IN_FRAMES  (BOOT_PAGE_TABLE_SIZE >> FRAME_WIDTH)
-
 
 extern void frame_low_arch_init(void);
Index: kernel/arch/arm32/include/mm/page.h
===================================================================
--- kernel/arch/arm32/include/mm/page.h	(revision df64dbcec09ca6420de2c8c0944a17482cc56d6b)
+++ kernel/arch/arm32/include/mm/page.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -46,5 +46,5 @@
 #define PAGE_SIZE	FRAME_SIZE
 
-#ifdef MACHINE_beagleboardxm
+#if (defined MACHINE_beagleboardxm) || (defined MACHINE_beaglebone)
 #ifndef __ASM__
 #	define KA2PA(x)	((uintptr_t) (x))
Index: kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c
===================================================================
--- kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c	(revision df64dbcec09ca6420de2c8c0944a17482cc56d6b)
+++ kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -35,7 +35,7 @@
 #include <arch/exception.h>
 #include <arch/mach/beagleboardxm/beagleboardxm.h>
-#include <genarch/drivers/amdm37x_irc/amdm37x_irc.h>
-#include <genarch/drivers/amdm37x_uart/amdm37x_uart.h>
-#include <genarch/drivers/amdm37x_gpt/amdm37x_gpt.h>
+#include <genarch/drivers/amdm37x/uart.h>
+#include <genarch/drivers/amdm37x/irc.h>
+#include <genarch/drivers/amdm37x/gpt.h>
 #include <genarch/fb/fb.h>
 #include <genarch/srln/srln.h>
Index: kernel/arch/arm32/src/mach/beaglebone/beaglebone.c
===================================================================
--- kernel/arch/arm32/src/mach/beaglebone/beaglebone.c	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
+++ kernel/arch/arm32/src/mach/beaglebone/beaglebone.c	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -0,0 +1,229 @@
+/*
+ * Copyright (c) 2012 Matteo Facchinetti
+ * Copyright (c) 2012 Maurizio Lombardi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup arm32beaglebone
+ * @{
+ */
+/** @file
+ *  @brief BeagleBone platform driver.
+ */
+
+#include <arch/exception.h>
+#include <arch/mach/beaglebone/beaglebone.h>
+#include <genarch/drivers/am335x/irc.h>
+#include <genarch/drivers/am335x/uart.h>
+#include <genarch/drivers/am335x/timer.h>
+#include <genarch/drivers/am335x/cm_per.h>
+#include <genarch/drivers/am335x/cm_dpll.h>
+#include <genarch/drivers/am335x/ctrl_module.h>
+#include <genarch/srln/srln.h>
+#include <interrupt.h>
+#include <ddi/ddi.h>
+#include <ddi/device.h>
+#include <mm/km.h>
+
+#define BBONE_MEMORY_START       0x80000000      /* physical */
+#define BBONE_MEMORY_SIZE        0x10000000      /* 256 MB */
+
+static void bbone_init(void);
+static void bbone_timer_irq_start(void);
+static void bbone_cpu_halt(void);
+static void bbone_get_memory_extents(uintptr_t *start, size_t *size);
+static void bbone_irq_exception(unsigned int exc_no, istate_t *istate);
+static void bbone_frame_init(void);
+static void bbone_output_init(void);
+static void bbone_input_init(void);
+static size_t bbone_get_irq_count(void);
+static const char *bbone_get_platform_name(void);
+
+static struct beaglebone {
+	am335x_irc_regs_t *irc_addr;
+	am335x_cm_per_regs_t *cm_per_addr;
+	am335x_cm_dpll_regs_t *cm_dpll_addr;
+	am335x_ctrl_module_t  *ctrl_module;
+	am335x_timer_t timer;
+	am335x_uart_t uart;
+} bbone;
+
+struct arm_machine_ops bbone_machine_ops = {
+	.machine_init = bbone_init,
+	.machine_timer_irq_start = bbone_timer_irq_start,
+	.machine_cpu_halt = bbone_cpu_halt,
+	.machine_get_memory_extents = bbone_get_memory_extents,
+	.machine_irq_exception = bbone_irq_exception,
+	.machine_frame_init = bbone_frame_init,
+	.machine_output_init = bbone_output_init,
+	.machine_input_init = bbone_input_init,
+	.machine_get_irq_count = bbone_get_irq_count,
+	.machine_get_platform_name = bbone_get_platform_name,
+};
+
+static void bbone_init(void)
+{
+	bbone.irc_addr = (void *) km_map(AM335x_IRC_BASE_ADDRESS,
+	    AM335x_IRC_SIZE, PAGE_NOT_CACHEABLE);
+
+	bbone.cm_per_addr = (void *) km_map(AM335x_CM_PER_BASE_ADDRESS,
+	    AM335x_CM_PER_SIZE, PAGE_NOT_CACHEABLE);
+
+	bbone.cm_dpll_addr = (void *) km_map(AM335x_CM_DPLL_BASE_ADDRESS,
+	    AM335x_CM_DPLL_SIZE, PAGE_NOT_CACHEABLE);
+
+	bbone.ctrl_module = (void *) km_map(AM335x_CTRL_MODULE_BASE_ADDRESS,
+	    AM335x_CTRL_MODULE_SIZE, PAGE_NOT_CACHEABLE);
+
+	ASSERT(bbone.irc_addr != NULL);
+	ASSERT(bbone.cm_per_addr != NULL);
+	ASSERT(bbone.cm_dpll_addr != NULL);
+	ASSERT(bbone.ctrl_module != NULL);
+
+	/* Initialize the interrupt controller */
+	am335x_irc_init(bbone.irc_addr);
+}
+
+static irq_ownership_t bbone_timer_irq_claim(irq_t *irq)
+{
+	return IRQ_ACCEPT;
+}
+
+static void bbone_timer_irq_handler(irq_t *irq)
+{
+	am335x_timer_intr_ack(&bbone.timer);
+	spinlock_unlock(&irq->lock);
+	clock();
+	spinlock_lock(&irq->lock);
+}
+
+static void bbone_timer_irq_start(void)
+{
+	unsigned sysclk_freq;
+	int rc;
+
+	/* Initialize the IRQ */
+	static irq_t timer_irq;
+	irq_initialize(&timer_irq);
+	timer_irq.devno = device_assign_devno();
+	timer_irq.inr = AM335x_DMTIMER2_IRQ;
+	timer_irq.claim = bbone_timer_irq_claim;
+	timer_irq.handler = bbone_timer_irq_handler;
+	irq_register(&timer_irq);
+
+	/* Enable the DMTIMER2 clock module */
+	am335x_clock_module_enable(bbone.cm_per_addr, DMTIMER2);
+	/* Select the SYSCLK as the clock source for the dmtimer2 module */
+	am335x_clock_source_select(bbone.cm_dpll_addr, DMTIMER2,
+	   CLK_SRC_M_OSC);
+	/* Initialize the DMTIMER2 */
+	if (am335x_ctrl_module_clock_freq_get(bbone.ctrl_module,
+	    &sysclk_freq) != EOK) {
+		printf("Cannot get the system clock frequency!\n");
+		return;
+	} else
+		printf("system clock running at %u hz\n", sysclk_freq);
+
+	rc = am335x_timer_init(&bbone.timer, DMTIMER2, HZ, sysclk_freq);
+	if (rc != EOK) {
+		printf("Timer initialization failed\n");
+		return;
+	}
+	/* Enable the interrupt */
+	am335x_irc_enable(bbone.irc_addr, AM335x_DMTIMER2_IRQ);
+	/* Start the timer */
+	am335x_timer_start(&bbone.timer);
+}
+
+static void bbone_cpu_halt(void)
+{
+	while (1);
+}
+
+/** Get extents of available memory.
+ *
+ * @param start		Place to store memory start address (physical).
+ * @param size		Place to store memory size.
+ */
+static void bbone_get_memory_extents(uintptr_t *start, size_t *size)
+{
+	*start = BBONE_MEMORY_START;
+	*size  = BBONE_MEMORY_SIZE;
+}
+
+static void bbone_irq_exception(unsigned int exc_no, istate_t *istate)
+{
+	const unsigned inum = am335x_irc_inum_get(bbone.irc_addr);
+	am335x_irc_irq_ack(bbone.irc_addr);
+
+	irq_t *irq = irq_dispatch_and_lock(inum);
+	if (irq) {
+		/* The IRQ handler was found. */
+		irq->handler(irq);
+		spinlock_unlock(&irq->lock);
+	} else {
+		printf("Spurious interrupt\n");
+	}
+}
+
+static void bbone_frame_init(void)
+{
+}
+
+static void bbone_output_init(void)
+{
+	const bool ok = am335x_uart_init(&bbone.uart,
+	    AM335x_UART0_IRQ, AM335x_UART0_BASE_ADDRESS,
+	    AM335x_UART0_SIZE);
+
+	if (ok)
+		stdout_wire(&bbone.uart.outdev);
+}
+
+static void bbone_input_init(void)
+{
+	srln_instance_t *srln_instance = srln_init();
+	if (srln_instance) {
+		indev_t *sink = stdin_wire();
+		indev_t *srln = srln_wire(srln_instance, sink);
+		am335x_uart_input_wire(&bbone.uart, srln);
+		am335x_irc_enable(bbone.irc_addr, AM335x_UART0_IRQ);
+	}
+}
+
+size_t bbone_get_irq_count(void)
+{
+	return AM335x_IRC_IRQ_COUNT;
+}
+
+const char *bbone_get_platform_name(void)
+{
+	return "beaglebone";
+}
+
+/**
+ * @}
+ */
+
Index: kernel/arch/arm32/src/machine_func.c
===================================================================
--- kernel/arch/arm32/src/machine_func.c	(revision df64dbcec09ca6420de2c8c0944a17482cc56d6b)
+++ kernel/arch/arm32/src/machine_func.c	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -42,4 +42,5 @@
 #include <arch/mach/integratorcp/integratorcp.h>
 #include <arch/mach/beagleboardxm/beagleboardxm.h>
+#include <arch/mach/beaglebone/beaglebone.h>
 
 /** Pointer to machine_ops structure being used. */
@@ -55,4 +56,6 @@
 #elif defined(MACHINE_beagleboardxm)
 	machine_ops = &bbxm_machine_ops;
+#elif defined(MACHINE_beaglebone)
+	machine_ops = &bbone_machine_ops;
 #else
 #error Machine type not defined.
Index: kernel/genarch/Makefile.inc
===================================================================
--- kernel/genarch/Makefile.inc	(revision df64dbcec09ca6420de2c8c0944a17482cc56d6b)
+++ kernel/genarch/Makefile.inc	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -106,7 +106,17 @@
 endif
 
+ifeq ($(CONFIG_AM335X_UART),y)
+	GENARCH_SOURCES += \
+		genarch/src/drivers/am335x/uart.c
+endif
+
+ifeq ($(CONFIG_AM335X_TIMERS),y)
+	GENARCH_SOURCES += \
+		genarch/src/drivers/am335x/timer.c
+endif
+
 ifeq ($(CONFIG_AMDM37X_UART),y)
 	GENARCH_SOURCES += \
-		genarch/src/drivers/amdm37x_uart/amdm37x_uart.c
+		genarch/src/drivers/amdm37x/uart.c
 endif
 
Index: kernel/genarch/include/drivers/am335x/cm_dpll.h
===================================================================
--- kernel/genarch/include/drivers/am335x/cm_dpll.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
+++ kernel/genarch/include/drivers/am335x/cm_dpll.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2013 Maurizio Lombardi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM335x DPLL.
+ */
+
+#ifndef _KERN_AM335X_CM_DPLL_H_
+#define _KERN_AM335X_CM_DPLL_H_
+
+#include "cm_dpll_regs.h"
+#include "timer.h"
+
+#define AM335x_CM_DPLL_BASE_ADDRESS   0x44E00500
+#define AM335x_CM_DPLL_SIZE           256
+
+static ioport32_t *am335x_cm_dpll_timer_reg_get(am335x_cm_dpll_regs_t *cm,
+    am335x_timer_id_t id)
+{
+	switch (id) {
+	default:
+		return NULL;
+	case DMTIMER2:
+		return &cm->clksel_timer2;
+	case DMTIMER3:
+		return &cm->clksel_timer3;
+	case DMTIMER4:
+		return &cm->clksel_timer4;
+	case DMTIMER5:
+		return &cm->clksel_timer5;
+	case DMTIMER6:
+		return &cm->clksel_timer6;
+	case DMTIMER7:
+		return &cm->clksel_timer7;
+	}
+}
+
+static void am335x_clock_source_select(am335x_cm_dpll_regs_t *cm,
+    am335x_timer_id_t id, am335x_clk_src_t src)
+{
+	ioport32_t *reg = am335x_cm_dpll_timer_reg_get(cm, id);
+	if (!reg)
+		return;
+
+	*reg = (*reg & ~0x03) | src;
+}
+
+#endif
+
+/**
+ * @}
+ */
+
Index: kernel/genarch/include/drivers/am335x/cm_dpll_regs.h
===================================================================
--- kernel/genarch/include/drivers/am335x/cm_dpll_regs.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
+++ kernel/genarch/include/drivers/am335x/cm_dpll_regs.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2013 Maurizio Lombardi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM335x DPLL registers.
+ */
+
+#ifndef _KERN_AM335X_CM_DPLL_REGS_H_
+#define _KERN_AM335X_CM_DPLL_REGS_H_
+
+typedef enum {
+	CLK_SRC_TCLKIN = 0x00,
+	CLK_SRC_M_OSC,
+	CLK_SRC_32_KHZ
+} am335x_clk_src_t;
+
+typedef struct am335x_cm_dpll_regs {
+
+	ioport32_t const pad0;
+
+	ioport32_t clksel_timer7;
+	ioport32_t clksel_timer2;
+	ioport32_t clksel_timer3;
+	ioport32_t clksel_timer4;
+
+	ioport32_t clksel_mac;
+#define AM335x_CM_CLKSEL_MII_FLAG (1 << 2)
+
+	ioport32_t clksel_timer5;
+	ioport32_t clksel_timer6;
+
+	ioport32_t clksel_cpts_rft;
+
+	ioport32_t const pad1;
+
+	ioport32_t clksel_timer1ms;
+#define AM335x_CM_CLKSEL_TIMER1MS_CLKMOSC      0x00
+#define AM335x_CM_CLKSEL_TIMER1MS_CLK32KHZ     0x01
+#define AM335x_CM_CLKSEL_TIMER1MS_TCLKIN       0x02
+#define AM335x_CM_CLKSEL_TIMER1MS_CLKRC32KHZ   0x03
+#define AM335x_CM_CLKSEL_TIMER1MS_32KHZCRYSTAL 0x04
+
+	ioport32_t clksel_gfx_fclk;
+#define AM335x_CM_CLKSEL_GFX_FCLK_CLKDIV_FLAG  (1 << 0)
+#define AM335x_CM_CLKSEL_GFX_FCLK_CLKSEL_FLAG  (1 << 1)
+
+	ioport32_t clksel_pru_icss_ocp;
+	ioport32_t clksel_lcdc_pixel;
+	ioport32_t clksel_wdt1;
+	ioport32_t clksel_gpio0_db;
+
+} am335x_cm_dpll_regs_t;
+
+#endif
+
+/**
+ * @}
+ */
Index: kernel/genarch/include/drivers/am335x/cm_per.h
===================================================================
--- kernel/genarch/include/drivers/am335x/cm_per.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
+++ kernel/genarch/include/drivers/am335x/cm_per.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2013 Maurizio Lombardi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM335x clock module.
+ */
+
+#ifndef _KERN_AM335X_CM_PER_H_
+#define _KERN_AM335X_CM_PER_H_
+
+#include <typedefs.h>
+#include "cm_per_regs.h"
+#include "timer.h"
+
+#define AM335x_CM_PER_BASE_ADDRESS   0x44E00000
+#define AM335x_CM_PER_SIZE           1024
+
+static ioport32_t *am335x_clock_clkctrl_reg_get(am335x_cm_per_regs_t *cm,
+    am335x_timer_id_t id)
+{
+	switch (id) {
+	default:
+		return NULL;
+	case DMTIMER2:
+		return &cm->timer2_clkctrl;
+	case DMTIMER3:
+		return &cm->timer3_clkctrl;
+	case DMTIMER4:
+		return &cm->timer4_clkctrl;
+	case DMTIMER5:
+		return &cm->timer5_clkctrl;
+	case DMTIMER6:
+		return &cm->timer6_clkctrl;
+	case DMTIMER7:
+		return &cm->timer7_clkctrl;
+	}
+
+}
+
+static void am335x_clock_module_enable(am335x_cm_per_regs_t *cm,
+    am335x_timer_id_t timer_id)
+{
+	ioport32_t *tmr_reg = am335x_clock_clkctrl_reg_get(cm, timer_id);
+	if (tmr_reg == NULL)
+		return;
+
+	/* Enable the clock module */
+	*tmr_reg = (*tmr_reg & ~0x03) | 0x02;
+
+	/* Wait for completion */
+	while ((*tmr_reg & 0x03) != 0x02);
+}
+
+#endif
+
+/**
+ * @}
+ */
+
Index: kernel/genarch/include/drivers/am335x/cm_per_regs.h
===================================================================
--- kernel/genarch/include/drivers/am335x/cm_per_regs.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
+++ kernel/genarch/include/drivers/am335x/cm_per_regs.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2013 Maurizio Lombardi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM335x clock module registers.
+ */
+
+#ifndef _KERN_AM335X_CM_PER_REGS_H_
+#define _KERN_AM335X_CM_PER_REGS_H_
+
+#include <typedefs.h>
+
+typedef struct am335x_cm_per_regs {
+
+	ioport32_t l4ls_clkstctrl;
+	ioport32_t l3ls_clkstctrl;
+	ioport32_t l4fw_clkstctrl;
+	ioport32_t l3_clkstctrl;
+
+	ioport32_t const pad0;
+
+	ioport32_t cpgmac0_clkctrl;
+	ioport32_t lcdc_clkctrl;
+	ioport32_t usb0_clkctrl;
+
+	ioport32_t const pad1;
+
+	ioport32_t tptc0_clkctrl;
+	ioport32_t emif_clkctrl;
+	ioport32_t ocmcram_clkctrl;
+	ioport32_t gpmc_clkctrl;
+	ioport32_t mcasp0_clkctrl;
+	ioport32_t uart5_clkctrl;
+	ioport32_t mmc0_clkctrl;
+	ioport32_t elm_clkctrl;
+	ioport32_t i2c2_clkctrl;
+	ioport32_t i2c1_clkctrl;
+	ioport32_t spi0_clkctrl;
+	ioport32_t spi1_clkctrl;
+
+	ioport32_t const pad2[3];
+
+	ioport32_t l4ls_clkctrl;
+	ioport32_t l4fw_clkctrl;
+	ioport32_t mcasp1_clkctrl;
+	ioport32_t uart1_clkctrl;
+	ioport32_t uart2_clkctrl;
+	ioport32_t uart3_clkctrl;
+	ioport32_t uart4_clkctrl;
+	ioport32_t timer7_clkctrl;
+	ioport32_t timer2_clkctrl;
+	ioport32_t timer3_clkctrl;
+	ioport32_t timer4_clkctrl;
+
+	ioport32_t const pad3[8];
+
+	ioport32_t gpio1_clkctrl;
+	ioport32_t gpio2_clkctrl;
+	ioport32_t gpio3_clkctrl;
+
+	ioport32_t const pad4;
+
+	ioport32_t tpcc_clkctrl;
+	ioport32_t dcan0_clkctrl;
+	ioport32_t dcan1_clkctrl;
+	ioport32_t epwmss1_clkctrl;
+	ioport32_t emiffw_clkctrl;
+	ioport32_t epwmss0_clkctrl;
+	ioport32_t epwmss2_clkctrl;
+	ioport32_t l3instr_clkctrl;
+	ioport32_t l3_clkctrl;
+	ioport32_t ieee5000_clkctrl;
+	ioport32_t pruicss_clkctrl;
+	ioport32_t timer5_clkctrl;
+	ioport32_t timer6_clkctrl;
+	ioport32_t mmc1_clkctrl;
+	ioport32_t mmc2_clkctrl;
+	ioport32_t tptc1_clkctrl;
+	ioport32_t tptc2_clkctrl;
+
+	ioport32_t const pad5[2];
+
+	ioport32_t spinlock_clkctrl;
+	ioport32_t mailbox0_clkctrl;
+
+	ioport32_t const pad6[2];
+
+	ioport32_t l4hs_clkstctrl;
+	ioport32_t l4hs_clkctrl;
+
+	ioport32_t const pad7[2];
+
+	ioport32_t ocpwp_l3_clkstctrl;
+	ioport32_t ocpwp_clkctrl;
+
+	ioport32_t const pad8[3];
+
+	ioport32_t pruicss_clkstctrl;
+	ioport32_t cpsw_clkstctrl;
+	ioport32_t lcdc_clkstctrl;
+	ioport32_t clkdiv32_clkctrl;
+	ioport32_t clk24mhz_clkstctrl;
+} am335x_cm_per_regs_t;
+
+#endif
+
+/**
+ * @}
+ */
Index: kernel/genarch/include/drivers/am335x/ctrl_module.h
===================================================================
--- kernel/genarch/include/drivers/am335x/ctrl_module.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
+++ kernel/genarch/include/drivers/am335x/ctrl_module.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2013 Maurizio Lombardi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM335x control module.
+ */
+
+#ifndef _KERN_AM335X_CTRL_MODULE_H_
+#define _KERN_AM335X_CTRL_MODULE_H_
+
+#include <errno.h>
+#include <typedefs.h>
+#include "ctrl_module_regs.h"
+
+#define AM335x_CTRL_MODULE_BASE_ADDRESS  0x44E10000
+#define AM335x_CTRL_MODULE_SIZE          131072 /* 128 Kb */
+
+typedef ioport32_t am335x_ctrl_module_t;
+
+static int
+am335x_ctrl_module_clock_freq_get(am335x_ctrl_module_t *base, unsigned *freq)
+{
+	unsigned const control_status = AM335x_CTRL_MODULE_REG_VALUE(base,
+	    CONTROL_STATUS);
+
+	/* Get the sysboot1 field at control_status[22,23] */
+	unsigned const sysboot1 = (control_status >> 22) & 0x03;
+
+	switch (sysboot1) {
+	default:
+		return EINVAL;
+	case 0:
+		*freq = 19200000; /* 19.2 Mhz */
+		break;
+	case 1:
+		*freq = 24000000; /* 24 Mhz */
+		break;
+	case 2:
+		*freq = 25000000; /* 25 Mhz */
+		break;
+	case 3:
+		*freq = 26000000; /* 26 Mhz */
+		break;
+	}
+
+	return EOK;
+}
+
+#endif
+
+/**
+ * @}
+ */
Index: kernel/genarch/include/drivers/am335x/ctrl_module_regs.h
===================================================================
--- kernel/genarch/include/drivers/am335x/ctrl_module_regs.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
+++ kernel/genarch/include/drivers/am335x/ctrl_module_regs.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -0,0 +1,280 @@
+/*
+ * Copyright (c) 2013 Maurizio Lombardi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM335x control module registers.
+ */
+
+#ifndef _KERN_AM335X_CTRL_MODULE_REGS_H_
+#define _KERN_AM335X_CTRL_MODULE_REGS_H_
+
+#include <typedefs.h>
+
+#define AM335x_CTRL_MODULE_REG_VALUE(base, name) \
+	    (*((ioport32_t *)(AM335x_CTRL_MODULE_##name##_OFFSET + \
+	    ((ioport8_t *) base))))
+
+#define AM335x_CTRL_MODULE_CONTROL_REVISION_OFFSET          0x00
+#define AM335x_CTRL_MODULE_CONTROL_HWINFO_OFFSET            0x04
+#define AM335x_CTRL_MODULE_CONTROL_SYSCONFIG_OFFSET         0x10
+#define AM335x_CTRL_MODULE_CONTROL_STATUS_OFFSET            0x40
+#define AM335x_CTRL_MODULE_CONTROL_EMIF_SDRAM_CONFIG_OFFSET 0x110
+#define AM335x_CTRL_MODULE_CORTEX_VBBLDO_CTRL_OFFSET        0x41C
+#define AM335x_CTRL_MODULE_CORE_SLDO_CTRL_OFFSET            0x428
+#define AM335x_CTRL_MODULE_MPU_SLDO_CTRL_OFFSET             0x42C
+#define AM335x_CTRL_MODULE_CLK32KDIVRATIO_CTRL_OFFSET       0x444
+#define AM335x_CTRL_MODULE_BANDGAP_CTRL_OFFSET              0x448
+#define AM335x_CTRL_MODULE_BANDGAP_TRIM_OFFSET              0x44C
+#define AM335x_CTRL_MODULE_PLL_CLKINPULOW_CTRL_OFFSET       0x458
+#define AM335x_CTRL_MODULE_MOSC_CTRL_OFFSET                 0x468
+#define AM335x_CTRL_MODULE_ROSC_CTRL_OFFSET                 0x46C
+#define AM335x_CTRL_MODULE_DEEPSLEEP_CTRL_OFFSET            0x470
+#define AM335x_CTRL_MODULE_DEVICE_ID_OFFSET                 0x600
+#define AM335x_CTRL_MODULE_DEV_FEATURE_OFFSET               0x604
+#define AM335x_CTRL_MODULE_INIT_PRIORITY_0_OFFSET           0x608
+#define AM335x_CTRL_MODULE_INIT_PRIORITY_1_OFFSET           0x60C
+#define AM335x_CTRL_MODULE_MMU_CFG_OFFSET                   0x610
+#define AM335x_CTRL_MODULE_TPTC_CFG_OFFSET                  0x614
+#define AM335x_CTRL_MODULE_USB_CTRL0_OFFSET                 0x620
+#define AM335x_CTRL_MODULE_USB_STS0_OFFSET                  0x624
+#define AM335x_CTRL_MODULE_USB_CTRL1_OFFSET                 0x628
+#define AM335x_CTRL_MODULE_USB_STS1_OFFSET                  0x62C
+#define AM335x_CTRL_MODULE_MAC_ID0_LO_OFFSET                0x630
+#define AM335x_CTRL_MODULE_MAC_ID0_HI_OFFSET                0x634
+#define AM335x_CTRL_MODULE_MAC_ID1_LO_OFFSET                0x638
+#define AM335x_CTRL_MODULE_MAC_ID1_HI_OFFSET                0x63C
+#define AM335x_CTRL_MODULE_DCAN_RAMINIT_OFFSET              0x644
+#define AM335x_CTRL_MODULE_USB_WKUP_CTRL_OFFSET             0x648
+#define AM335x_CTRL_MODULE_GMII_SEL_OFFSET                  0x650
+#define AM335x_CTRL_MODULE_PWMSS_CTRL_OFFSET                0x664
+#define AM335x_CTRL_MODULE_MREQPRIO_0_OFFSET                0x670
+#define AM335x_CTRL_MODULE_MREQPRIO_1_OFFSET                0x674
+#define AM335x_CTRL_MODULE_HW_EVENT_SEL_GRP1_OFFSET         0x690
+#define AM335x_CTRL_MODULE_HW_EVENT_SEL_GRP2_OFFSET         0x694
+#define AM335x_CTRL_MODULE_HW_EVENT_SEL_GRP3_OFFSET         0x698
+#define AM335x_CTRL_MODULE_HW_EVENT_SEL_GRP4_OFFSET         0x69C
+#define AM335x_CTRL_MODULE_SMRT_CTRL_OFFSET                 0x6A0
+#define AM335x_CTRL_MODULE_MPUSS_HW_DEBUG_SEL_OFFSET        0x6A4
+#define AM335x_CTRL_MODULE_MPUSS_HW_DBG_INFO_OFFSET         0x6A8
+#define AM335x_CTRL_MODULE_VDD_MPU_OPP_050_OFFSET           0x770
+#define AM335x_CTRL_MODULE_VDD_MPU_OPP_100_OFFSET           0x774
+#define AM335x_CTRL_MODULE_VDD_MPU_OPP_120_OFFSET           0x778
+#define AM335x_CTRL_MODULE_VDD_MPU_OPP_TURBO_OFFSET         0x77C
+#define AM335x_CTRL_MODULE_VDD_CORE_OPP_050_OFFSET          0x7B8
+#define AM335x_CTRL_MODULE_VDD_CORE_OPP_100_OFFSET          0x7BC
+#define AM335x_CTRL_MODULE_BB_SCALE_OFFSET                  0x7D0
+#define AM335x_CTRL_MODULE_USB_VID_PID_OFFSET               0x7F4
+#define AM335x_CTRL_MODULE_CONF_GPMC_AD0_OFFSET             0x800
+#define AM335x_CTRL_MODULE_CONF_GPMC_AD1_OFFSET             0x804
+#define AM335x_CTRL_MODULE_CONF_GPMC_AD2_OFFSET             0x808
+#define AM335x_CTRL_MODULE_CONF_GPMC_AD3_OFFSET             0x80C
+#define AM335x_CTRL_MODULE_CONF_GPMC_AD4_OFFSET             0x810
+#define AM335x_CTRL_MODULE_CONF_GPMC_AD5_OFFSET             0x814
+#define AM335x_CTRL_MODULE_CONF_GPMC_AD6_OFFSET             0x818
+#define AM335x_CTRL_MODULE_CONF_GPMC_AD7_OFFSET             0x81C
+#define AM335x_CTRL_MODULE_CONF_GPMC_AD8_OFFSET             0x820
+#define AM335x_CTRL_MODULE_CONF_GPMC_AD9_OFFSET             0x824
+#define AM335x_CTRL_MODULE_CONF_GPMC_AD10_OFFSET            0x828
+#define AM335x_CTRL_MODULE_CONF_GPMC_AD11_OFFSET            0x82C
+#define AM335x_CTRL_MODULE_CONF_GPMC_AD12_OFFSET            0x830
+#define AM335x_CTRL_MODULE_CONF_GPMC_AD13_OFFSET            0x834
+#define AM335x_CTRL_MODULE_CONF_GPMC_AD14_OFFSET            0x838
+#define AM335x_CTRL_MODULE_CONF_GPMC_AD15_OFFSET            0x83C
+#define AM335x_CTRL_MODULE_CONF_GPMC_A0_OFFSET              0x840
+#define AM335x_CTRL_MODULE_CONF_GPMC_A1_OFFSET              0x844
+#define AM335x_CTRL_MODULE_CONF_GPMC_A2_OFFSET              0x848
+#define AM335x_CTRL_MODULE_CONF_GPMC_A3_OFFSET              0x84C
+#define AM335x_CTRL_MODULE_CONF_GPMC_A4_OFFSET              0x850
+#define AM335x_CTRL_MODULE_CONF_GPMC_A5_OFFSET              0x854
+#define AM335x_CTRL_MODULE_CONF_GPMC_A6_OFFSET              0x858
+#define AM335x_CTRL_MODULE_CONF_GPMC_A7_OFFSET              0x85C
+#define AM335x_CTRL_MODULE_CONF_GPMC_A8_OFFSET              0x860
+#define AM335x_CTRL_MODULE_CONF_GPMC_A9_OFFSET              0x864
+#define AM335x_CTRL_MODULE_CONF_GPMC_A10_OFFSET             0x868
+#define AM335x_CTRL_MODULE_CONF_GPMC_A11_OFFSET             0x86C
+#define AM335x_CTRL_MODULE_CONF_GPMC_WAIT0_OFFSET           0x870
+#define AM335x_CTRL_MODULE_CONF_GPMC_WPN_OFFSET             0x874
+#define AM335x_CTRL_MODULE_CONF_GPMC_BEN1_OFFSET            0x878
+#define AM335x_CTRL_MODULE_CONF_GPMC_CSN0_OFFSET            0x87C
+#define AM335x_CTRL_MODULE_CONF_GPMC_CSN1_OFFSET            0x880
+#define AM335x_CTRL_MODULE_CONF_GPMC_CSN2_OFFSET            0x884
+#define AM335x_CTRL_MODULE_CONF_GPMC_CSN3_OFFSET            0x888
+#define AM335x_CTRL_MODULE_CONF_GPMC_CLK_OFFSET             0x88C
+#define AM335x_CTRL_MODULE_CONF_GPMC_ADVN_ALE_OFFSET        0x890
+#define AM335x_CTRL_MODULE_CONF_GPMC_OEN_REN_OFFSET         0x894
+#define AM335x_CTRL_MODULE_CONF_GPMC_WEN_OFFSET             0x898
+#define AM335x_CTRL_MODULE_CONF_GPMC_BEN0_CLE_OFFSET        0x89C
+#define AM335x_CTRL_MODULE_CONF_LCD_DATA0_OFFSET            0x8A0
+#define AM335x_CTRL_MODULE_CONF_LCD_DATA1_OFFSET            0x8A4
+#define AM335x_CTRL_MODULE_CONF_LCD_DATA2_OFFSET            0x8A8
+#define AM335x_CTRL_MODULE_CONF_LCD_DATA3_OFFSET            0x8AC
+#define AM335x_CTRL_MODULE_CONF_LCD_DATA4_OFFSET            0x8B0
+#define AM335x_CTRL_MODULE_CONF_LCD_DATA5_OFFSET            0x8B4
+#define AM335x_CTRL_MODULE_CONF_LCD_DATA6_OFFSET            0x8B8
+#define AM335x_CTRL_MODULE_CONF_LCD_DATA7_OFFSET            0x8BC
+#define AM335x_CTRL_MODULE_CONF_LCD_DATA8_OFFSET            0x8C0
+#define AM335x_CTRL_MODULE_CONF_LCD_DATA9_OFFSET            0x8C4
+#define AM335x_CTRL_MODULE_CONF_LCD_DATA10_OFFSET           0x8C8
+#define AM335x_CTRL_MODULE_CONF_LCD_DATA11_OFFSET           0x8CC
+#define AM335x_CTRL_MODULE_CONF_LCD_DATA12_OFFSET           0x8D0
+#define AM335x_CTRL_MODULE_CONF_LCD_DATA13_OFFSET           0x8D4
+#define AM335x_CTRL_MODULE_CONF_LCD_DATA14_OFFSET           0x8D8
+#define AM335x_CTRL_MODULE_CONF_LCD_DATA15_OFFSET           0x8DC
+#define AM335x_CTRL_MODULE_CONF_LCD_VSYNC_OFFSET            0x8E0
+#define AM335x_CTRL_MODULE_CONF_LCD_HSYNC_OFFSET            0x8E4
+#define AM335x_CTRL_MODULE_CONF_LCD_PCLK_OFFSET             0x8E8
+#define AM335x_CTRL_MODULE_CONF_LCD_AC_BIAS_EN_OFFSET       0x8EC
+#define AM335x_CTRL_MODULE_CONF_MMC0_DAT3_OFFSET            0x8F0
+#define AM335x_CTRL_MODULE_CONF_MMC0_DAT2_OFFSET            0x8F4
+#define AM335x_CTRL_MODULE_CONF_MMC0_DAT1_OFFSET            0x8F8
+#define AM335x_CTRL_MODULE_CONF_MMC0_DAT0_OFFSET            0x8FC
+#define AM335x_CTRL_MODULE_CONF_MMC0_CLK_OFFSET             0x900
+#define AM335x_CTRL_MODULE_CONF_MMC0_CMD_OFFSET             0x904
+#define AM335x_CTRL_MODULE_CONF_MII1_COL_OFFSET             0x908
+#define AM335x_CTRL_MODULE_CONF_MII1_CRS_OFFSET             0x90C
+#define AM335x_CTRL_MODULE_CONF_MII1_RX_ER_OFFSET           0x910
+#define AM335x_CTRL_MODULE_CONF_MII1_TX_EN_OFFSET           0x914
+#define AM335x_CTRL_MODULE_CONF_MII1_RX_DV_OFFSET           0x918
+#define AM335x_CTRL_MODULE_CONF_MII1_TXD3_OFFSET            0x91C
+#define AM335x_CTRL_MODULE_CONF_MII1_TXD2_OFFSET            0x920
+#define AM335x_CTRL_MODULE_CONF_MII1_TXD1_OFFSET            0x924
+#define AM335x_CTRL_MODULE_CONF_MII1_TXD0_OFFSET            0x928
+#define AM335x_CTRL_MODULE_CONF_MII1_TX_CLK_OFFSET          0x92C
+#define AM335x_CTRL_MODULE_CONF_MII1_RX_CLK_OFFSET          0x930
+#define AM335x_CTRL_MODULE_CONF_MII1_RXD3_OFFSET            0x934
+#define AM335x_CTRL_MODULE_CONF_MII1_RXD2_OFFSET            0x938
+#define AM335x_CTRL_MODULE_CONF_MII1_RXD1_OFFSET            0x93C
+#define AM335x_CTRL_MODULE_CONF_MII1_RXD0_OFFSET            0x940
+#define AM335x_CTRL_MODULE_CONF_RMII1_REF_CLK_OFFSET        0x944
+#define AM335x_CTRL_MODULE_CONF_MDIO_OFFSET                 0x948
+#define AM335x_CTRL_MODULE_CONF_MDC_OFFSET                  0x94C
+#define AM335x_CTRL_MODULE_CONF_SPI0_SCLK_OFFSET            0x950
+#define AM335x_CTRL_MODULE_CONF_SPI0_D0_OFFSET              0x954
+#define AM335x_CTRL_MODULE_CONF_SPI0_D1_OFFSET              0x958
+#define AM335x_CTRL_MODULE_CONF_SPI0_CS0_OFFSET             0x95C
+#define AM335x_CTRL_MODULE_CONF_SPI0_CS1_OFFSET             0x960
+#define AM335x_CTRL_MODULE_CONF_ECAP0_IN_PWM0_OUT_OFFSET    0x964
+#define AM335x_CTRL_MODULE_CONF_UART0_CTSN_OFFSET           0x968
+#define AM335x_CTRL_MODULE_CONF_UART0_RTSN_OFFSET           0x96C
+#define AM335x_CTRL_MODULE_CONF_UART0_RXD_OFFSET            0x970
+#define AM335x_CTRL_MODULE_CONF_UART0_TXD_OFFSET            0x974
+#define AM335x_CTRL_MODULE_CONF_UART1_CTSN_OFFSET           0x978
+#define AM335x_CTRL_MODULE_CONF_UART1_RTSN_OFFSET           0x97C
+#define AM335x_CTRL_MODULE_CONF_UART1_RXD_OFFSET            0x980
+#define AM335x_CTRL_MODULE_CONF_UART1_TXD_OFFSET            0x984
+#define AM335x_CTRL_MODULE_CONF_I2C0_SDA_OFFSET             0x988
+#define AM335x_CTRL_MODULE_CONF_I2C0_SCL_OFFSET             0x98C
+#define AM335x_CTRL_MODULE_CONF_MCASP0_ACLKX_OFFSET         0x990
+#define AM335x_CTRL_MODULE_CONF_MCASP0_FSX_OFFSET           0x994
+#define AM335x_CTRL_MODULE_CONF_MCASP0_AXR0_OFFSET          0x998
+#define AM335x_CTRL_MODULE_CONF_MCASP0_AHCLKR_OFFSET        0x99C
+#define AM335x_CTRL_MODULE_CONF_MCASP0_ACLKR_OFFSET         0x9A0
+#define AM335x_CTRL_MODULE_CONF_MCASP0_FSR_OFFSET           0x9A4
+#define AM335x_CTRL_MODULE_CONF_MCASP0_AXR1_OFFSET          0x9A8
+#define AM335x_CTRL_MODULE_CONF_MCASP0_AHCLKX_OFFSET        0x9AC
+#define AM335x_CTRL_MODULE_CONF_XDMA_EVENT_INTR0_OFFSET     0x9B0
+#define AM335x_CTRL_MODULE_CONF_XDMA_EVENT_INTR1_OFFSET     0x9B4
+#define AM335x_CTRL_MODULE_CONF_WARMRSTN_OFFSET             0x9B8
+#define AM335x_CTRL_MODULE_CONF_PWRONRSTN_OFFSET            0x9BC
+#define AM335x_CTRL_MODULE_CONF_NNMI_OFFSET                 0x9C0
+#define AM335x_CTRL_MODULE_CONF_XTALIN_OFFSET               0x9C4
+#define AM335x_CTRL_MODULE_CONF_XTALOUT_OFFSET              0x9C8
+#define AM335x_CTRL_MODULE_CONF_TMS_OFFSET                  0x9D0
+#define AM335x_CTRL_MODULE_CONF_TDI_OFFSET                  0x9D4
+#define AM335x_CTRL_MODULE_CONF_TDO_OFFSET                  0x9D8
+#define AM335x_CTRL_MODULE_CONF_TCK_OFFSET                  0x9DC
+#define AM335x_CTRL_MODULE_CONF_TRSTN_OFFSET                0x9E0
+#define AM335x_CTRL_MODULE_CONF_EMU0_OFFSET                 0x9E4
+#define AM335x_CTRL_MODULE_CONF_EMU1_OFFSET                 0x9E8
+#define AM335x_CTRL_MODULE_CONF_RTC_XTALIN_OFFSET           0x9EC
+#define AM335x_CTRL_MODULE_CONF_RTC_XTALOUT_OFFSET          0x9F0
+#define AM335x_CTRL_MODULE_CONF_RTC_PWRONRSTN_OFFSET        0x9F8
+#define AM335x_CTRL_MODULE_CONF_PMIC_POWER_EN_OFFSET        0x9FC
+#define AM335x_CTRL_MODULE_CONF_EXT_WAKEUP_OFFSET           0xA00
+#define AM335x_CTRL_MODULE_CONF_RTC_KALDO_ENN_OFFSET        0xA04
+#define AM335x_CTRL_MODULE_CONF_USB0_DM_OFFSET              0xA08
+#define AM335x_CTRL_MODULE_CONF_USB0_DP_OFFSET              0xA0C
+#define AM335x_CTRL_MODULE_CONF_USB0_CE_OFFSET              0xA10
+#define AM335x_CTRL_MODULE_CONF_USB0_ID_OFFSET              0xA14
+#define AM335x_CTRL_MODULE_CONF_USB0_VBUS_OFFSET            0xA18
+#define AM335x_CTRL_MODULE_CONF_USB0_DRVVBUS_OFFSET         0xA1C
+#define AM335x_CTRL_MODULE_CONF_USB1_DM_OFFSET              0xA20
+#define AM335x_CTRL_MODULE_CONF_USB1_DP_OFFSET              0xA24
+#define AM335x_CTRL_MODULE_CONF_USB1_CE_OFFSET              0xA28
+#define AM335x_CTRL_MODULE_CONF_USB1_ID_OFFSET              0xA2C
+#define AM335x_CTRL_MODULE_CONF_USB1_VBUS_OFFSET            0xA30
+#define AM335x_CTRL_MODULE_CONF_USB1_DRVVBUS_OFFSET         0xA34
+#define AM335x_CTRL_MODULE_CQDETECT_STATUS_OFFSET           0xE00
+#define AM335x_CTRL_MODULE_DDR_IO_CTRL_OFFSET               0xE04
+#define AM335x_CTRL_MODULE_VTP_CTRL_OFFSET                  0xE0C
+#define AM335x_CTRL_MODULE_VREF_CTRL_OFFSET                 0xE14
+#define AM335x_CTRL_MODULE_TPCC_EVT_MUX_0_3_OFFSET          0xF90
+#define AM335x_CTRL_MODULE_TPCC_EVT_MUX_4_7_OFFSET          0xF94
+#define AM335x_CTRL_MODULE_TPCC_EVT_MUX_8_11_OFFSET         0xF98
+#define AM335x_CTRL_MODULE_TPCC_EVT_MUX_12_15_OFFSET        0xF9C
+#define AM335x_CTRL_MODULE_TPCC_EVT_MUX_16_19_OFFSET        0xFA0
+#define AM335x_CTRL_MODULE_TPCC_EVT_MUX_20_23_OFFSET        0xFA4
+#define AM335x_CTRL_MODULE_TPCC_EVT_MUX_24_27_OFFSET        0xFA8
+#define AM335x_CTRL_MODULE_TPCC_EVT_MUX_28_31_OFFSET        0xFAC
+#define AM335x_CTRL_MODULE_TPCC_EVT_MUX_32_35_OFFSET        0xFB0
+#define AM335x_CTRL_MODULE_TPCC_EVT_MUX_36_39_OFFSET        0xFB4
+#define AM335x_CTRL_MODULE_TPCC_EVT_MUX_40_43_OFFSET        0xFB8
+#define AM335x_CTRL_MODULE_TPCC_EVT_MUX_44_47_OFFSET        0xFBC
+#define AM335x_CTRL_MODULE_TPCC_EVT_MUX_48_51_OFFSET        0xFC0
+#define AM335x_CTRL_MODULE_TPCC_EVT_MUX_52_55_OFFSET        0xFC4
+#define AM335x_CTRL_MODULE_TPCC_EVT_MUX_56_59_OFFSET        0xFC8
+#define AM335x_CTRL_MODULE_TPCC_EVT_MUX_60_63_OFFSET        0xFCC
+#define AM335x_CTRL_MODULE_TIMER_EVT_CAPT_OFFSET            0xFD0
+#define AM335x_CTRL_MODULE_ECAP_EVT_CAPT_OFFSET             0xFD4
+#define AM335x_CTRL_MODULE_ADC_EVT_CAPT_OFFSET              0xFD8
+#define AM335x_CTRL_MODULE_RESET_ISO_OFFSET                 0x1000
+#define AM335x_CTRL_MODULE_DDR_CKE_CTRL_OFFSET              0x131C
+#define AM335x_CTRL_MODULE_SMA2_OFFSET                      0x1320
+#define AM335x_CTRL_MODULE_M3_TXEV_EOI_OFFSET               0x1324
+#define AM335x_CTRL_MODULE_IPC_MSG_REG0_OFFSET              0x1328
+#define AM335x_CTRL_MODULE_IPC_MSG_REG1_OFFSET              0x132C
+#define AM335x_CTRL_MODULE_IPC_MSG_REG2_OFFSET              0x1330
+#define AM335x_CTRL_MODULE_IPC_MSG_REG3_OFFSET              0x1334
+#define AM335x_CTRL_MODULE_IPC_MSG_REG4_OFFSET              0x1338
+#define AM335x_CTRL_MODULE_IPC_MSG_REG5_OFFSET              0x133C
+#define AM335x_CTRL_MODULE_IPC_MSG_REG6_OFFSET              0x1340
+#define AM335x_CTRL_MODULE_IPC_MSG_REG7_OFFSET              0x1344
+#define AM335x_CTRL_MODULE_DDR_CMD0_IOCTRL_OFFSET           0x1404
+#define AM335x_CTRL_MODULE_DDR_CMD1_IOCTRL_OFFSET           0x1408
+#define AM335x_CTRL_MODULE_DDR_CMD2_IOCTRL_OFFSET           0x140C
+#define AM335x_CTRL_MODULE_DDR_DATA0_IOCTRL_OFFSET          0x1440
+#define AM335x_CTRL_MODULE_DDR_DATA1_IOCTRL_OFFSET          0x1444
+
+#endif
+
+/**
+ * @}
+ */
Index: kernel/genarch/include/drivers/am335x/iomux.h
===================================================================
--- kernel/genarch/include/drivers/am335x/iomux.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
+++ kernel/genarch/include/drivers/am335x/iomux.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -0,0 +1,268 @@
+/*
+ * Copyright (c) 2012 Matteo Facchinetti
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM335x CONTROL_MODULE: I/O multiplexing.
+ */
+
+#ifndef KERN_AM335X_IOMUX_H_
+#define KERN_AM335X_IOMUX_H_
+
+#include <typedefs.h>
+
+/* Pad Control Register for each configurable pin p. 876 */
+#define AM335X_IOMUX_SLEWRATE_SLOW_FLAG  (1 << 6)
+#define AM335X_IOMUX_RX_ENABLE_FLAG  (1 << 5)
+#define AM335X_IOMUX_PULLUP_FLAG  (1 << 4)
+#define AM335X_IOMUX_PULLUPDOWN_ENABLE_FLAG  (1 << 3)
+#define AM335X_IOMUX_MODE0  0
+#define AM335X_IOMUX_MODE1  1
+#define AM335X_IOMUX_MODE2  2
+#define AM335X_IOMUX_MODE3  3
+#define AM335X_IOMUX_MODE4  4
+#define AM335X_IOMUX_MODE5  5
+#define AM335X_IOMUX_MODE6  6
+#define AM335X_IOMUX_MODE7  7
+
+/* AM335X CONTROL_MODULE configurable I/O pin. Table 9-10 at p. 886 */
+#define AM335X_IOMUX_CONF_BASE_ADDRESS 0x44E10800
+
+typedef struct {
+	ioport32_t gpmc_ad1;
+	ioport32_t gpmc_ad2;
+	ioport32_t gpmc_ad3;
+	ioport32_t gpmc_ad4;
+	ioport32_t gpmc_ad5;
+	ioport32_t gpmc_ad6;
+	ioport32_t gpmc_ad7;
+	ioport32_t gpmc_ad8;
+	ioport32_t gpmc_ad9;
+	ioport32_t gpmc_ad10;
+	ioport32_t gpmc_ad11;
+	ioport32_t gpmc_ad12;
+	ioport32_t gpmc_ad13;
+	ioport32_t gpmc_ad14;
+	ioport32_t gpmc_ad15;
+	ioport32_t gpmc_a0;
+	ioport32_t gpmc_a1;
+	ioport32_t gpmc_a2;
+	ioport32_t gpmc_a3;
+	ioport32_t gpmc_a4;
+	ioport32_t gpmc_a5;
+	ioport32_t gpmc_a6;
+	ioport32_t gpmc_a7;
+	ioport32_t gpmc_a8;
+	ioport32_t gpmc_a9;
+	ioport32_t gpmc_a10;
+	ioport32_t gpmc_a11;
+	ioport32_t gpmc_wait0;
+	ioport32_t gpmc_wpn;
+	ioport32_t gpmc_be1n;
+	ioport32_t gpmc_csn0;
+	ioport32_t gpmc_csn1;
+	ioport32_t gpmc_csn2;
+	ioport32_t gpmc_csn3;
+	ioport32_t gpmc_clk;
+	ioport32_t gpmc_advn_ale;
+	ioport32_t gpmc_oen_ren;
+	ioport32_t gpmc_wen;
+	ioport32_t gpmc_be0n_cle;
+	ioport32_t lcd_data0;
+	ioport32_t lcd_data1;
+	ioport32_t lcd_data2;
+	ioport32_t lcd_data3;
+	ioport32_t lcd_data4;
+	ioport32_t lcd_data5;
+	ioport32_t lcd_data6;
+	ioport32_t lcd_data7;
+	ioport32_t lcd_data8;
+	ioport32_t lcd_data9;
+	ioport32_t lcd_data10;
+	ioport32_t lcd_data11;
+	ioport32_t lcd_data12;
+	ioport32_t lcd_data13;
+	ioport32_t lcd_data14;
+	ioport32_t lcd_data15;
+	ioport32_t lcd_vsync;
+	ioport32_t lcd_hsync;
+	ioport32_t lcd_pclk;
+	ioport32_t lcd_ac_bias_en;
+	ioport32_t mmc0_dat3;
+	ioport32_t mmc0_dat2;
+	ioport32_t mmc0_dat1;
+	ioport32_t mmc0_dat0;
+	ioport32_t mmc0_clk;
+	ioport32_t mmc0_cmd;
+	ioport32_t mii1_col;
+	ioport32_t mii1_crs;
+	ioport32_t mii1_rxerr;
+	ioport32_t mii1_txen;
+	ioport32_t mii1_rxdv;
+	ioport32_t mii1_txd3;
+	ioport32_t mii1_txd2;
+	ioport32_t mii1_txd1;
+	ioport32_t mii1_txd0;
+	ioport32_t mii1_txclk;
+	ioport32_t mii1_rxclk;
+	ioport32_t mii1_rxd3;
+	ioport32_t mii1_rxd2;
+	ioport32_t mii1_rxd1;
+	ioport32_t mii1_rxd0;
+	ioport32_t rmii1_refclk;
+	ioport32_t mdio_data;
+	ioport32_t mdio_clk;
+	ioport32_t spi0_sclk;
+	ioport32_t spi0_d0;
+	ioport32_t spi0_d1;
+	ioport32_t spi0_cs0;
+	ioport32_t spi0_cs1;
+	ioport32_t ecap0_in_pwm0_out;
+	ioport32_t uart0_ctsn;
+	ioport32_t uart0_rtsn;
+	ioport32_t uart0_rxd;
+	ioport32_t uart0_txd;
+	ioport32_t uart1_ctsn;
+	ioport32_t uart1_rtsn;
+	ioport32_t uart1_rxd;
+	ioport32_t uart1_txd;
+	ioport32_t i2c0_sda;
+	ioport32_t i2c0_scl;
+	ioport32_t mcasp0_aclkx;
+	ioport32_t mcasp0_fsx;
+	ioport32_t mcasp0_axr0;
+	ioport32_t mcasp0_ahclkr;
+	ioport32_t mcasp0_aclkr;
+	ioport32_t mcasp0_fsr;
+	ioport32_t mcasp0_axr1;
+	ioport32_t mcasp0_ahclkx;
+	ioport32_t xdma_event_intr0;
+	ioport32_t xdma_event_intr1;
+	ioport32_t nresetin_out;
+	ioport32_t porz;
+	ioport32_t nnmi;
+	ioport32_t osc0_in;
+	ioport32_t osc0_out;
+	ioport32_t osc0_vss;
+	ioport32_t tms;
+	ioport32_t tdi;
+	ioport32_t tdo;
+	ioport32_t tck;
+	ioport32_t ntrst;
+	ioport32_t emu0;
+	ioport32_t emu1;
+	ioport32_t osc1_in;
+	ioport32_t osc1_out;
+	ioport32_t osc1_vss;
+	ioport32_t rtc_porz;
+	ioport32_t pmic_power_en;
+	ioport32_t ext_wakeup;
+	ioport32_t enz_kaldo_1p8v;
+	ioport32_t usb0_dm;
+	ioport32_t usb0_dp;
+	ioport32_t usb0_ce;
+	ioport32_t usb0_id;
+	ioport32_t usb0_vbus;
+	ioport32_t usb0_drvvbus;
+	ioport32_t usb1_dm;
+	ioport32_t usb1_dp;
+	ioport32_t usb1_ce;
+	ioport32_t usb1_id;
+	ioport32_t usb1_vbus;
+	ioport32_t usb1_drvvbus;
+	ioport32_t ddr_resetn;
+	ioport32_t ddr_csn0;
+	ioport32_t ddr_cke;
+	ioport32_t ddr_ck;
+	ioport32_t ddr_nck;
+	ioport32_t ddr_casn;
+	ioport32_t ddr_rasn;
+	ioport32_t ddr_wen;
+	ioport32_t ddr_ba0;
+	ioport32_t ddr_ba1;
+	ioport32_t ddr_ba2;
+	ioport32_t ddr_a0;
+	ioport32_t ddr_a1;
+	ioport32_t ddr_a2;
+	ioport32_t ddr_a3;
+	ioport32_t ddr_a4;
+	ioport32_t ddr_a5;
+	ioport32_t ddr_a6;
+	ioport32_t ddr_a7;
+	ioport32_t ddr_a8;
+	ioport32_t ddr_a9;
+	ioport32_t ddr_a10;
+	ioport32_t ddr_a11;
+	ioport32_t ddr_a12;
+	ioport32_t ddr_a13;
+	ioport32_t ddr_a14;
+	ioport32_t ddr_a15;
+	ioport32_t ddr_odt;
+	ioport32_t ddr_d0;
+	ioport32_t ddr_d1;
+	ioport32_t ddr_d2;
+	ioport32_t ddr_d3;
+	ioport32_t ddr_d4;
+	ioport32_t ddr_d5;
+	ioport32_t ddr_d6;
+	ioport32_t ddr_d7;
+	ioport32_t ddr_d8;
+	ioport32_t ddr_d9;
+	ioport32_t ddr_d10;
+	ioport32_t ddr_d11;
+	ioport32_t ddr_d12;
+	ioport32_t ddr_d13;
+	ioport32_t ddr_d14;
+	ioport32_t ddr_d15;
+	ioport32_t ddr_dqm0;
+	ioport32_t ddr_dqm1;
+	ioport32_t ddr_dqs0;
+	ioport32_t ddr_dqsn0;
+	ioport32_t ddr_dqs1;
+	ioport32_t ddr_dqsn1;
+	ioport32_t ddr_vref;
+	ioport32_t ddr_vtp;
+	ioport32_t ain7;
+	ioport32_t ain6;
+	ioport32_t ain5;
+	ioport32_t ain4;
+	ioport32_t ain3;
+	ioport32_t ain2;
+	ioport32_t ain1;
+	ioport32_t ain0;
+	ioport32_t vrefp;
+	ioport32_t vrefn;
+	ioport32_t avdd;
+	ioport32_t avss;
+	ioport32_t iforce;
+	ioport32_t vsense;
+	ioport32_t testout;
+} am335x_iomux_conf_regs_t;
+#endif /* KERN_AM335X_IOMUX_H_ */
Index: kernel/genarch/include/drivers/am335x/irc.h
===================================================================
--- kernel/genarch/include/drivers/am335x/irc.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
+++ kernel/genarch/include/drivers/am335x/irc.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -0,0 +1,255 @@
+/*
+ * Copyright (c) 2012 Maurizio Lombardi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+
+/**
+ * @file
+ * @brief Texas Instruments AM335x MPU on-chip interrupt controller driver.
+ */
+
+#ifndef KERN_AM335x_IRQC_H_
+#define KERN_AM335x_IRQC_H_
+
+#define AM335x_IRC_BASE_ADDRESS 0x48200000
+#define AM335x_IRC_SIZE         4096
+
+#define AM335x_IRC_IRQ_COUNT    128
+
+#include <typedefs.h>
+
+typedef struct {
+	const ioport32_t revision;
+#define AM335x_IRC_REV_MASK 0xFF
+
+	const uint8_t padd0[12];
+
+	/* This register controls the various parameters
+	 * of the OCP interface.
+	 */
+	ioport32_t sysconfig;
+#define AM335x_IRC_SYSCONFIG_AUTOIDLE_FLAG   (1 << 0)
+#define AM335x_IRC_SYSCONFIG_SOFTRESET_FLAG  (1 << 1)
+
+	/* This register provides status information about the module */
+	const ioport32_t sysstatus;
+#define AM335x_IRC_SYSSTATUS_RESET_DONE_FLAG (1 << 0)
+
+	const uint8_t padd1[40];
+
+	/* This register supplies the currently active IRQ interrupt number */
+	ioport32_t sir_irq;
+#define AM335x_IRC_SIR_IRQ_ACTIVEIRQ_MASK       0x7F
+#define AM335x_IRC_SIR_IRQ_SPURIOUSIRQFLAG_MASK 0xFFFFFFF8
+
+	/* This register supplies the currently active FIQ interrupt number */
+	const ioport32_t sir_fiq;
+#define AM335x_IRC_FIQ_IRQ_ACTIVEFIQ_MASK       0x7F
+#define AM335x_IRC_FIQ_IRQ_SPURIOUSFIQFLAG_MASK 0xFFFFFFF8
+
+	/* This register contains the new interrupt agreement bits */
+	ioport32_t control;
+#define AM335x_IRC_CONTROL_NEWIRQAGR_FLAG       (1 << 0)
+#define AM335x_IRC_CONTROL_NEWFIQAGR_FLAG       (1 << 1)
+
+	/* This register controls protection of the other registers.
+	 * This register can only be accessed in priviledged mode, regardless
+	 * of the current value of the protection bit.
+	 */
+	ioport32_t protection;
+#define AM335x_IRC_PROTECTION_FLAG              (1 << 0)
+
+	/* This register controls the clock auto-idle for the functional
+	 * clock and the input synchronizers.
+	 */
+	ioport32_t idle;
+#define AM335x_IRC_IDLE_FUNCIDLE_FLAG           (1 << 0)
+#define AM335x_IRC_IDLE_TURBO_FLAG              (1 << 1)
+
+	const uint8_t padd2[12];
+
+	/* This register supplies the currently active IRQ priority level */
+	const ioport32_t irq_priority;
+#define AM335x_IRC_IRQ_PRIORITY_IRQPRIORITY_MASK     0x7F
+#define AM335x_IRC_IRQ_PRIORITY_SPURIOUSIRQFLAG_MASK 0xFFFFFFF8
+
+	/* This register supplies the currently active FIQ priority level */
+	const ioport32_t fiq_priority;
+#define AM335x_IRC_FIQ_PRIORITY_FIQPRIORITY_MASK     0x7F
+#define AM335x_IRC_FIQ_PRIORITY_SPURIOUSIRQFLAG_MASK 0xFFFFFFF8
+
+	/* This register sets the priority threshold */
+	ioport32_t threshold;
+#define AM335x_IRC_THRESHOLD_PRIORITYTHRESHOLD_MASK     0xFF
+#define AM335x_IRC_THRESHOLD_PRIORITYTHRESHOLD_ENABLED  0x00
+#define AM335x_IRC_THRESHOLD_PRIORITYTHRESHOLD_DISABLED 0xFF
+
+	const uint8_t padd[20];
+
+	struct {
+		/* Raw interrupt input status before masking */
+		const ioport32_t itr;
+
+		/* Interrupt mask */
+		ioport32_t mir;
+
+		/* This register is used to clear the interrupt mask bits,
+		 * Write 1 clears the mask bit to 0.
+		 */
+		ioport32_t mir_clear;
+
+		/* This register is used to set the interrupt mask bits,
+		 * Write 1 sets the mask bit to 1.
+		 */
+		ioport32_t mir_set;
+
+		/* This register is used to set the software interrupt bits,
+		 * it is also used to read the current active software
+		 * interrupts.
+		 * Write 1 sets the software interrups bits to 1.
+		 */
+		ioport32_t isr_set;
+
+		/* This register is used to clear the software interrups bits.
+		 * Write 1 clears the software interrupt bits to 0.
+		 */
+		ioport32_t isr_clear;
+
+		/* This register contains the IRQ status after masking. */
+		const ioport32_t pending_irq;
+
+		/* This register contains the FIQ status after masking. */
+		const ioport32_t pending_fiq;
+	} interrupts[4];
+
+	/* These registers contain the priority for the interrups and
+	 * the FIQ/IRQ steering.
+	 */
+	ioport32_t ilr[AM335x_IRC_IRQ_COUNT];
+/* 0 = Interrupt routed to IRQ, 1 = interrupt routed to FIQ */
+#define AM335x_IRC_ILR_FIQNIRQ_FLAG    (1 << 0)
+#define AM335x_IRC_ILR_PRIORITY_MASK   0x3F
+#define AM335x_IRC_ILR_PRIORITY_SHIFT  2
+
+} am335x_irc_regs_t;
+
+static inline void am335x_irc_init(am335x_irc_regs_t *regs)
+{
+	int i;
+
+	/* Initialization sequence */
+
+	/* 1 - Program the SYSCONFIG register: if necessary, enable the
+	 *     autogating by setting the AUTOIDLE bit.
+	 */
+	regs->sysconfig &= ~AM335x_IRC_SYSCONFIG_AUTOIDLE_FLAG;
+
+	/* 2 - Program the IDLE register: if necessary, disable functional
+	 *     clock autogating or enable synchronizer autogating by setting
+	 *     the FUNCIDLE bit or the TURBO bit accordingly.
+	 */
+	regs->idle &= ~AM335x_IRC_IDLE_FUNCIDLE_FLAG;
+	regs->idle &= ~AM335x_IRC_IDLE_TURBO_FLAG;
+
+	/* 3 - Program ILRm register for each interrupt line: Assign a
+	 *     priority level and set the FIQNIRQ bit for an FIQ interrupt
+	 *     (by default, interrupts are mapped to IRQ and
+	 *     priority is 0 (highest).
+	 */
+
+	for (i = 0; i < AM335x_IRC_IRQ_COUNT; ++i)
+		regs->ilr[i] = 0;
+
+	/* 4 - Program the MIRn register: Enable interrupts (by default,
+	 *     all interrupt lines are masked).
+	 */
+	for (i = 0; i < 4; ++i)
+		regs->interrupts[i].mir_set = 0xFFFFFFFF;
+}
+
+/** Get the currently active IRQ interrupt number
+ *
+ * @param regs     Pointer to the irc memory mapped registers
+ *
+ * @return         The active IRQ interrupt number
+ */
+static inline unsigned am335x_irc_inum_get(am335x_irc_regs_t *regs)
+{
+	return regs->sir_irq & AM335x_IRC_SIR_IRQ_ACTIVEIRQ_MASK;
+}
+
+/** Reset IRQ output and enable new IRQ generation
+ *
+ * @param regs    Pointer to the irc memory mapped registers
+ */
+static inline void am335x_irc_irq_ack(am335x_irc_regs_t *regs)
+{
+	regs->control = AM335x_IRC_CONTROL_NEWIRQAGR_FLAG;
+}
+
+/** Reset FIQ output and enable new FIQ generation
+ *
+ * @param regs    Pointer to the irc memory mapped registers
+ */
+static inline void am335x_irc_fiq_ack(am335x_irc_regs_t *regs)
+{
+	regs->control = AM335x_IRC_CONTROL_NEWFIQAGR_FLAG;
+}
+
+/** Clear an interrupt mask bit
+ *
+ * @param regs    Pointer to the irc memory mapped registers
+ * @param inum    The interrupt to be enabled
+ */
+static inline void am335x_irc_enable(am335x_irc_regs_t *regs, unsigned inum)
+{
+	ASSERT(inum < AM335x_IRC_IRQ_COUNT);
+	const unsigned set = inum / 32;
+	const unsigned pos = inum % 32;
+	regs->interrupts[set].mir_clear = (1 << pos);
+}
+
+/** Set an interrupt mask bit
+ *
+ * @param regs    Pointer to the irc memory mapped registers
+ * @param inum    The interrupt to be disabled
+ */
+static inline void am335x_irc_disable(am335x_irc_regs_t *regs, unsigned inum)
+{
+	ASSERT(inum < AM335x_IRC_IRQ_COUNT);
+	const unsigned set = inum / 32;
+	const unsigned pos = inum % 32;
+	regs->interrupts[set].mir_set = (1 << pos);
+}
+
+#endif
+
+/**
+ * @}
+ */
Index: kernel/genarch/include/drivers/am335x/timer.h
===================================================================
--- kernel/genarch/include/drivers/am335x/timer.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
+++ kernel/genarch/include/drivers/am335x/timer.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2012 Maurizio Lombardi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM335x timer driver.
+ */
+
+#ifndef _KERN_AM335X_TIMER_H_
+#define _KERN_AM335X_TIMER_H_
+
+#include <genarch/drivers/am335x/timer_regs.h>
+
+#define AM335x_DMTIMER0_BASE_ADDRESS    0x44E05000
+#define AM335x_DMTIMER0_SIZE            4096
+#define AM335x_DMTIMER0_IRQ             66
+
+#define AM335x_DMTIMER2_BASE_ADDRESS    0x48040000
+#define AM335x_DMTIMER2_SIZE            4096
+#define AM335x_DMTIMER2_IRQ             68
+
+#define AM335x_DMTIMER3_BASE_ADDRESS    0x48042000
+#define AM335x_DMTIMER3_SIZE            4096
+#define AM335x_DMTIMER3_IRQ             69
+
+#define AM335x_DMTIMER4_BASE_ADDRESS    0x48044000
+#define AM335x_DMTIMER4_SIZE            4096
+#define AM335x_DMTIMER4_IRQ             92
+
+#define AM335x_DMTIMER5_BASE_ADDRESS    0x48046000
+#define AM335x_DMTIMER5_SIZE            4096
+#define AM335x_DMTIMER5_IRQ             93
+
+#define AM335x_DMTIMER6_BASE_ADDRESS    0x48048000
+#define AM335x_DMTIMER6_SIZE            4096
+#define AM335x_DMTIMER6_IRQ             94
+
+#define AM335x_DMTIMER7_BASE_ADDRESS    0x4804A000
+#define AM335x_DMTIMER7_SIZE            4096
+#define AM335x_DMTIMER7_IRQ             95
+
+typedef enum {
+	DMTIMER0 = 0,
+	DMTIMER1_1MS,
+	DMTIMER2,
+	DMTIMER3,
+	DMTIMER4,
+	DMTIMER5,
+	DMTIMER6,
+	DMTIMER7,
+
+	TIMERS_MAX
+} am335x_timer_id_t;
+
+typedef struct am335x_timer {
+	am335x_timer_regs_t *regs;
+	am335x_timer_id_t id;
+} am335x_timer_t;
+
+extern int am335x_timer_init(am335x_timer_t *timer, am335x_timer_id_t id,
+    unsigned hz, unsigned srcclk_hz);
+extern void am335x_timer_intr_ack(am335x_timer_t *timer);
+extern void am335x_timer_reset(am335x_timer_t *timer);
+extern void am335x_timer_start(am335x_timer_t *timer);
+extern void am335x_timer_stop(am335x_timer_t *timer);
+
+
+#endif
+
+/**
+ * @}
+ */
+
Index: kernel/genarch/include/drivers/am335x/timer_regs.h
===================================================================
--- kernel/genarch/include/drivers/am335x/timer_regs.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
+++ kernel/genarch/include/drivers/am335x/timer_regs.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2012 Maurizio Lombardi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM335x DMTIMER memory mapped registers.
+ */
+
+#ifndef _KERN_AM335X_TIMER_REGS_H_
+#define _KERN_AM335X_TIMER_REGS_H_
+
+#include <typedefs.h>
+
+typedef struct am335x_timer_regs {
+
+	/* This read only register contains the
+	 * revision number of the module
+	 */
+	ioport32_t const tidr;
+#define AM335x_TIMER_TIDR_MINOR_MASK     0x3F
+#define AM335x_TIMER_TIDR_MINOR_SHIFT    0
+#define AM335x_TIMER_TIDR_CUSTOM_MASK    0x03
+#define AM335x_TIMER_TIDR_CUSTOM_SHIFT   6
+#define AM335x_TIMER_TIDR_MAJOR_MASK     0x07
+#define AM335x_TIMER_TIDR_MAJOR_SHIFT    8
+#define AM335x_TIMER_TIDR_RTL_MASK       0x1F
+#define AM335x_TIMER_TIDR_RTL_SHIFT      11
+#define AM335x_TIMER_TIDR_FUNC_MASK      0xFFF
+#define AM335x_TIMER_TIDR_FUNC_SHIFT     16
+#define AM335x_TIMER_TIDR_SCHEME_MASK    0x03
+#define AM335x_TIMER_TIDR_SCHEME_SHIFT   30
+
+	ioport32_t const pad1[3];
+
+	/* This register allows controlling various
+	 * parameters of the OCP interface.
+	 */
+	ioport32_t tiocp_cfg;
+#define AM335x_TIMER_TIOCPCFG_SOFTRESET_FLAG    (1 << 0)
+#define AM335x_TIMER_TIOCPCFG_EMUFREE_FLAG      (1 << 1)
+
+#define AM335x_TIMER_TIOCPCFG_IDLEMODE_MASK            0x02
+#define AM335x_TIMER_TIOCPCFG_IDLEMODE_SHIFT           2
+#  define AM335x_TIMER_TIOCCPCFG_IDLEMODE_FORCE        0x00
+#  define AM335x_TIMER_TIOCCPCFG_IDLEMODE_DISABLED     0x01
+#  define AM335x_TIMER_TIOCCPCFG_IDLEMODE_SMART        0x02
+#  define AM335x_TIMER_TIOCCPCFG_IDLEMODE_SMART_WAKEUP 0x03
+
+	ioport32_t const pad2[4];
+
+	ioport32_t irqstatus_raw;
+#define AM335x_TIMER_IRQSTATUS_RAW_MAT_FLAG     (1 << 0)
+#define AM335x_TIMER_IRQSTATUS_RAW_OVF_FLAG     (1 << 1)
+#define AM335x_TIMER_IRQSTATUS_RAW_TCAR_FLAG    (1 << 2)
+
+	ioport32_t irqstatus;
+#define AM335x_TIMER_IRQSTATUS_MAT_FLAG     (1 << 0)
+#define AM335x_TIMER_IRQSTATUS_OVF_FLAG     (1 << 1)
+#define AM335x_TIMER_IRQSTATUS_TCAR_FLAG    (1 << 2)
+
+	ioport32_t irqenable_set;
+#define AM335x_TIMER_IRQENABLE_SET_MAT_FLAG (1 << 0)
+#define AM335x_TIMER_IRQENABLE_SET_OVF_FLAG (1 << 1)
+#define AM335x_TIMER_IRQENABLE_SET_TCAR_FLAG (1 << 2)
+
+	ioport32_t irqenable_clr;
+#define AM335x_TIMER_IRQENABLE_CLR_MAT_FLAG (1 << 0)
+#define AM335x_TIMER_IRQENABLE_CLR_OVF_FLAG (1 << 1)
+#define AM335x_TIMER_IRQENABLE_CLR_TCAR_FLAG (1 << 2)
+
+	/* Timer IRQ wakeup enable register */
+	ioport32_t irqwakeen;
+#define AM335x_TIMER_IRQWAKEEN_MAT_FLAG     (1 << 0)
+#define AM335x_TIMER_IRQWAKEEN_OVF_FLAG     (1 << 1)
+#define AM335x_TIMER_IRQWAKEEN_TCAR_FLAG    (1 << 2)
+
+	/* Timer control register */
+	ioport32_t tclr;
+#define AM335x_TIMER_TCLR_ST_FLAG           (1 << 0)
+#define AM335x_TIMER_TCLR_AR_FLAG           (1 << 1)
+#define AM335x_TIMER_TCLR_PTV_MASK          0x07
+#define AM335x_TIMER_TCLR_PTV_SHIFT         2
+#define AM335x_TIMER_TCLR_PRE_FLAG          (1 << 5)
+#define AM335x_TIMER_TCLR_CE_FLAG           (1 << 6)
+#define AM335x_TIMER_TCLR_SCPWM_FLAG        (1 << 7)
+#define AM335x_TIMER_TCLR_TCM_MASK          0x03
+#define AM335x_TIMER_TCLR_TCM_SHIFT         8
+#define AM335x_TIMER_TCLR_TGR_MASK          0x03
+#define AM335x_TIMER_TCLR_TGR_SHIFT         10
+#define AM335x_TIMER_TCLR_PT_FLAG           (1 << 12)
+#define AM335x_TIMER_TCLR_CAPT_MODE_FLAG    (1 << 13)
+#define AM335x_TIMER_TCLR_GPO_CFG_FLAG      (1 << 14)
+
+	/* Timer counter register */
+	ioport32_t tcrr;
+
+	/* Timer load register */
+	ioport32_t tldr;
+
+	/* Timer trigger register */
+	ioport32_t const ttgr;
+
+	/* Timer write posted status register */
+	ioport32_t twps;
+#define AM335x_TIMER_TWPS_PEND_TCLR         (1 << 0)
+#define AM335x_TIMER_TWPS_PEND_TCRR         (1 << 1)
+#define AM335x_TIMER_TWPS_PEND_TLDR         (1 << 2)
+#define AM335x_TIMER_TWPS_PEND_TTGR         (1 << 3)
+#define AM335x_TIMER_TWPS_PEND_TMAR         (1 << 4)
+
+	/* Timer match register */
+	ioport32_t tmar;
+
+	/* Timer capture register */
+	ioport32_t tcar1;
+
+	/* Timer synchronous interface control register */
+	ioport32_t tsicr;
+#define AM335x_TIMER_TSICR_SFT_FLAG         (1 << 1)
+#define AM335x_TIMER_TSICR_POSTED_FLAG      (1 << 2)
+
+	/* Timer capture register */
+	ioport32_t tcar2;
+
+} am335x_timer_regs_t;
+
+#endif
+
+/**
+ * @}
+ */
+
Index: kernel/genarch/include/drivers/am335x/uart.h
===================================================================
--- kernel/genarch/include/drivers/am335x/uart.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
+++ kernel/genarch/include/drivers/am335x/uart.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) Maurizio Lombardi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM335x UART driver.
+ */
+
+#ifndef _KERN_AM335X_UART_H_
+#define _KERN_AM335X_UART_H_
+
+#include "uart_regs.h"
+
+#define AM335x_UART0_BASE_ADDRESS    0x44E09000
+#define AM335x_UART0_SIZE            4096
+#define AM335x_UART0_IRQ             72
+
+#define AM335x_UART1_BASE_ADDRESS    0x48022000
+#define AM335x_UART1_SIZE            4096
+#define AM335x_UART1_IRQ             73
+
+#define AM335x_UART2_BASE_ADDRESS    0x48024000
+#define AM335x_UART2_SIZE            4096
+#define AM335x_UART2_IRQ             74
+
+#define AM335x_UART3_BASE_ADDRESS    0x481A6000
+#define AM335x_UART3_SIZE            4096
+#define AM335x_UART3_IRQ             44
+
+#define AM335x_UART4_BASE_ADDRESS    0x481A8000
+#define AM335x_UART4_SIZE            4096
+#define AM335x_UART4_IRQ             45
+
+#define AM335x_UART5_BASE_ADDRESS    0x481AA000
+#define AM335x_UART5_SIZE            4096
+#define AM335x_UART5_IRQ             46
+
+typedef struct {
+	am335x_uart_regs_t *regs;
+	indev_t *indev;
+	outdev_t outdev;
+	irq_t irq;
+} am335x_uart_t;
+
+#ifdef CONFIG_AM335X_UART
+extern bool am335x_uart_init(am335x_uart_t *uart, inr_t interrupt,
+    uintptr_t addr, size_t size);
+
+extern void am335x_uart_input_wire(am335x_uart_t *uart, indev_t *indev);
+#else
+static bool am335x_uart_init(am335x_uart_t *uart, inr_t interrupt,
+    uintptr_t addr, size_t size)
+{ return true; }
+
+static void am335x_uart_input_wire(am335x_uart_t *uart, indev_t *indev) {}
+#endif
+
+#endif
+
+/**
+ * @}
+ */
+
Index: kernel/genarch/include/drivers/am335x/uart_regs.h
===================================================================
--- kernel/genarch/include/drivers/am335x/uart_regs.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
+++ kernel/genarch/include/drivers/am335x/uart_regs.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -0,0 +1,431 @@
+/*
+ * Copyright (c) 2012 Jan Vesely
+ * Copyright (c) 2012 Maurizio Lombardi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM335x UART memory mapped registers.
+ */
+
+#ifndef _KERN_AM335X_UART_REGS_H_
+#define _KERN_AM335X_UART_REGS_H_
+
+#include <typedefs.h>
+#include <console/chardev.h>
+#include <ddi/irq.h>
+
+typedef struct {
+	union {
+		/** Stores lower part of the 14-bit baud divisor */
+		ioport32_t dll;
+#define AM335x_UART_DLL_MASK   (0xff)
+
+		/** Receive holding register */
+		const ioport32_t rhr;
+#define AM335x_UART_RHR_MASK   (0xff)
+
+		/** Transmit holding register */
+		ioport32_t thr;
+#define AM335x_UART_THR_MASK   (0xff)
+	};
+
+	union {
+		/** Stores higher part of the 14-bit baud divisor */
+		ioport32_t dlh;
+#define AM335x_UART_DLH_MASK   (0x1f)
+
+		/** Interrupt enable registers */
+		ioport32_t ier;
+#define AM335x_UART_IER_RHR_IRQ_FLAG   (1 << 0)
+#define AM335x_UART_IER_THR_IRQ_FLAG   (1 << 1)
+#define AM335x_UART_IER_LINE_STS_IRQ_FLAG   (1 << 2)
+#define AM335x_UART_IER_MODEM_STS_IRQ_FLAG   (1 << 3)
+#define AM335x_UART_IER_SLEEP_MODE_FLAG   (1 << 4)
+#define AM335x_UART_IER_XOFF_IRQ_FLAG   (1 << 5)
+#define AM335x_UART_IER_RTS_IRQ_FLAG   (1 << 6)
+#define AM335x_UART_IER_CTS_IRQ_FLAG   (1 << 7)
+
+#define AM335x_CIR_IER_RHR_IRQ_FLAG   (1 << 0)
+#define AM335x_CIR_IER_THR_IRQ_FLAG   (1 << 1)
+#define AM335x_CIR_IER_RX_STOP_IRQ_FLAG   (1 << 2)
+#define AM335x_CIR_IER_RX_OVERRUN_IRQ_FLAG   (1 << 3)
+#define AM335x_CIR_IER_TX_STS_IRQ_FLAG   (1 << 5)
+
+#define AM335x_IRDA_IER_RHR_IRQ_FLAG   (1 << 0)
+#define AM335x_IRDA_IER_THR_IRQ_FLAG   (1 << 1)
+#define AM335x_IRDA_IER_LAST_RX_BYTE_IRQ_FLAG   (1 << 2)
+#define AM335x_IRDA_IER_RX_OVERRUN_IRQ_FLAG   (1 << 3)
+#define AM335x_IRDA_IER_STS_FIFO_TRIG_IRQ_FLAG   (1 << 4)
+#define AM335x_IRDA_IER_TX_STS_IRQ_FLAG   (1 << 5)
+#define AM335x_IRDA_IER_LINE_STS_IRQ_FLAG   (1 << 6)
+#define AM335x_IRDA_IER_EOF_IRQ_FLAG   (1 << 7)
+	};
+
+	union {
+		/** Interrupt identification register */
+		const ioport32_t iir;
+#define AM335x_UART_IIR_IRQ_PENDING_FLAG   (1 << 0)
+#define AM335x_UART_IIR_TYPE_MASK   (0x1f)
+#define AM335x_UART_IIR_TYPE_SHIFT   (1)
+#define AM335x_UART_IIR_FCR_MASK   (0x3)
+#define AM335x_UART_IIR_FCR_SHIFT   (6)
+
+#define AM335x_CIR_IIR_RHR_IRQ_FLAG   (1 << 0)
+#define AM335x_CIR_IIR_THR_IRQ_FLAG   (1 << 1)
+#define AM335x_CIR_IIR_RX_STOP_IRQ_FLAG   (1 << 2)
+#define AM335x_CIR_IIR_RX_OE_IRQ_FLAG   (1 << 3)
+#define AM335x_CIR_IIR_TX_STS_IRQ_FLAG   (1 << 5)
+
+#define AM335x_IRDA_IIR_RHR_IRQ_FLAG   (1 << 0)
+#define AM335x_IRDA_IIR_THR_IRQ_FLAG   (1 << 1)
+#define AM335x_IRDA_IIR_RX_FIFO_LB_IRQ_FLAG   (1 << 2)
+#define AM335x_IRDA_IIR_RX_OE_IRQ_FLAG   (1 << 3)
+#define AM335x_IRDA_IIR_STS_FIFO_IRQ_FLAG   (1 << 4)
+#define AM335x_IRDA_IIR_TX_STS_IRQ_FLAG   (1 << 5)
+#define AM335x_IRDA_IIR_LINE_STS_IRQ_FLAG   (1 << 6)
+#define AM335x_IRDA_IIR_EOF_IRQ_FLAG   (1 << 7)
+
+		/** FIFO control register */
+		ioport32_t fcr;
+#define AM335x_UART_FCR_FIFO_EN_FLAG   (1 << 0)
+#define AM335x_UART_FCR_RX_FIFO_CLR_FLAG   (1 << 1)
+#define AM335x_UART_FCR_TX_FIFO_CLR_FLAG   (1 << 3)
+#define AM335x_UART_FCR_DMA_MODE_FLAG   (1 << 4)
+
+#define AM335x_UART_FCR_TX_FIFO_TRIG_MASK   (0x3)
+#define AM335x_UART_FCR_TX_FIFO_TRIG_SHIFT   (4)
+
+#define AM335x_UART_FCR_RX_FIFO_TRIG_MASK   (0x3)
+#define AM335x_UART_FCR_RX_FIFO_TRIG_SHIFT   (6)
+
+		/** Enhanced feature register */
+		ioport32_t efr;
+#define AM335x_UART_EFR_SW_FLOW_CTRL_RX_MASK   (0x3)
+#define AM335x_UART_EFR_SW_FLOW_CTRL_RX_SHIFT   (0)
+#define AM335x_UART_EFR_SW_FLOW_CTRL_TX_MASK   (0x3)
+#define AM335x_UART_EFR_SW_FLOW_CTRL_TX_SHIFT   (2)
+
+#define AM335x_UART_EFR_SW_FLOW_CTRL_NONE   (0x0)
+#define AM335x_UART_EFR_SW_FLOW_CTRL_X2   (0x1)
+#define AM335x_UART_EFR_SW_FLOW_CTRL_X1   (0x2)
+#define AM335x_UART_EFR_SW_FLOW_CTRL_XBOTH   (0x3)
+
+#define AM335x_UART_EFR_ENH_FLAG   (1 << 4)
+#define AM335x_UART_EFR_SPEC_CHAR_FLAG   (1 << 5)
+#define AM335x_UART_EFR_AUTO_RTS_EN_FLAG   (1 << 6)
+#define AM335x_UART_EFR_AUTO_CTS_EN_FLAG   (1 << 7)
+	};
+
+	/** Line control register */
+	ioport32_t lcr;
+#define AM335x_UART_LCR_CHAR_LENGTH_MASK   (0x3)
+#define AM335x_UART_LCR_CHAR_LENGTH_SHIFT   (0)
+#define AM335x_UART_LCR_CHAR_LENGTH_5BITS   (0x0)
+#define AM335x_UART_LCR_CHAR_LENGTH_6BITS   (0x1)
+#define AM335x_UART_LCR_CHAR_LENGTH_7BITS   (0x2)
+#define AM335x_UART_LCR_CHAR_LENGTH_8BITS   (0x3)
+#define AM335x_UART_LCR_NB_STOP_FLAG   (1 << 2)
+#define AM335x_UART_LCR_PARITY_EN_FLAG   (1 << 3)
+#define AM335x_UART_LCR_PARITY_TYPE1_FLAG   (1 << 4)
+#define AM335x_UART_LCR_PARITY_TYPE2_FLAG   (1 << 5)
+#define AM335x_UART_LCR_BREAK_EN_FLAG   (1 << 6)
+#define AM335x_UART_LCR_DIV_EN_FLAG   (1 << 7)
+
+
+	union {
+		/** Modem control register */
+		ioport32_t mcr;
+#define AM335x_UART_MCR_DTR_FLAG   (1 << 0)
+#define AM335x_UART_MCR_RTS_FLAG   (1 << 1)
+#define AM335x_UART_MCR_RI_STS_CH_FLAG   (1 << 2)
+#define AM335x_UART_MCR_CD_STS_CH_FLAG   (1 << 3)
+#define AM335x_UART_MCR_LOOPBACK_EN_FLAG   (1 << 4)
+#define AM335x_UART_MCR_XON_EN_FLAG   (1 << 5)
+#define AM335x_UART_MCR_TCR_TLR_FLAG   (1 << 6)
+
+		/** UART: XON1 char, IRDA: ADDR1 address */
+		ioport32_t xon1_addr1;
+#define AM335x_UART_XON1_ADDR1_MASK   (0xff)
+	};
+
+	union {
+		/** Line status register */
+		const ioport32_t lsr;
+#define AM335x_UART_LSR_RX_FIFO_E_FLAG   (1 << 0)
+#define AM335x_UART_LSR_RX_OE_FLAG   (1 << 1)
+#define AM335x_UART_LSR_RX_PE_FLAG   (1 << 2)
+#define AM335x_UART_LSR_RX_FE_FLAG   (1 << 3)
+#define AM335x_UART_LSR_RX_BI_FLAG   (1 << 4)
+#define AM335x_UART_LSR_TX_FIFO_E_FLAG   (1 << 5)
+#define AM335x_UART_LSR_TX_SR_E_FLAG   (1 << 6)
+#define AM335x_UART_LSR_RX_FIFO_STS_FLAG   (1 << 7)
+
+#define AM335x_CIR_LSR_RX_FIFO_E_FLAG   (1 << 0)
+#define AM335x_CIR_LSR_RX_STOP_FLAG   (1 << 5)
+#define AM335x_CIR_LSR_THR_EMPTY_FLAG   (1 << 7)
+
+#define AM335x_IRDA_LSR_RX_FIFO_E_FLAG   (1 << 0)
+#define AM335x_IRDA_LSR_STS_FIFO_E_FLAG   (1 << 1)
+#define AM335x_IRDA_LSR_CRC_FLAG   (1 << 2)
+#define AM335x_IRDA_LSR_ABORT_FLAG   (1 << 3)
+#define AM335x_IRDA_LSR_FTL_FLAG   (1 << 4)
+#define AM335x_IRDA_LSR_RX_LAST_FLAG   (1 << 5)
+#define AM335x_IRDA_LSR_STS_FIFO_FULL_FLAG   (1 << 6)
+#define AM335x_IRDA_LSR_THR_EMPTY_FLAG   (1 << 7)
+
+		/** UART: XON2 char, IRDA: ADDR2 address */
+		ioport32_t xon2_addr2;
+	};
+
+	union {
+		/** Modem status register */
+		const ioport32_t msr;
+#define AM335x_UART_MSR_CTS_STS_FLAG   (1 << 0)
+#define AM335x_UART_MSR_DSR_STS_FLAG   (1 << 1)
+#define AM335x_UART_MSR_RI_STS_FLAG   (1 << 2)
+#define AM335x_UART_MSR_DCD_STS_FLAG   (1 << 3)
+#define AM335x_UART_MSR_NCTS_STS_FLAG   (1 << 4)
+#define AM335x_UART_MSR_NDSR_STS_FLAG   (1 << 5)
+#define AM335x_UART_MSR_NRI_STS_FLAG   (1 << 6)
+#define AM335x_UART_MSR_NCD_STS_FLAG   (1 << 7)
+
+		/** Transmission control register */
+		ioport32_t tcr;
+#define AM335x_UART_TCR_FIFO_TRIG_MASK   (0xf)
+#define AM335x_UART_TCR_FIFO_TRIG_HALT_SHIFT   (0)
+#define AM335x_UART_TCR_FIFO_TRIG_START_SHIFT   (4)
+
+		/** UART: XOFF1 char */
+		ioport32_t xoff1;
+#define AM335x_UART_XOFF1_MASK   (0xff)
+	};
+
+	union {
+		/* Scratchpad register, does nothing */
+		ioport32_t spr;
+#define AM335x_UART_SPR_MASK   (0xff)
+
+		/* Trigger level register */
+		ioport32_t tlr;
+#define AM335x_UART_TLR_LEVEL_MASK   (0xf)
+#define AM335x_UART_TLR_TX_FIFO_TRIG_SHIFT   (0)
+#define AM335x_UART_TLR_RX_FIFO_TRIG_SHIFT   (4)
+
+		/** UART: XOFF2 char */
+		ioport32_t xoff2;
+#define AM335x_UART_XOFF2_MASK   (0xff)
+	};
+
+	/** Mode definition register. */
+	ioport32_t mdr1;
+#define AM335x_UART_MDR_MS_MASK   (0x7)
+#define AM335x_UART_MDR_MS_SHIFT   (0)
+#define AM335x_UART_MDR_MS_UART16   (0x0)
+#define AM335x_UART_MDR_MS_SIR   (0x1)
+#define AM335x_UART_MDR_MS_UART16_AUTO   (0x2)
+#define AM335x_UART_MDR_MS_UART13   (0x3)
+#define AM335x_UART_MDR_MS_MIR   (0x4)
+#define AM335x_UART_MDR_MS_FIR   (0x5)
+#define AM335x_UART_MDR_MS_CIR   (0x6)
+#define AM335x_UART_MDR_MS_DISABLE   (0x7)
+
+#define AM335x_UART_MDR_IR_SLEEP_FLAG   (1 << 3)
+#define AM335x_UART_MDR_SET_TXIR_FLAG   (1 << 4)
+#define AM335x_UART_MDR_SCT_FLAG   (1 << 5)
+#define AM335x_UART_MDR_SIP_FLAG   (1 << 6)
+#define AM335x_UART_MDR_FRAME_END_MODE_FLAG   (1 << 7)
+
+	/** Mode definition register */
+	ioport32_t mdr2;
+#define AM335x_UART_MDR_IRTX_UNDERRUN_FLAG   (1 << 0)
+#define AM335x_UART_MDR_STS_FIFO_TRIG_MASK   (0x3)
+#define AM335x_UART_MDR_STS_FIFO_TRIG_SHIFT   (1)
+#define AM335x_UART_MDR_PULSE_SHAPING_FLAG   (1 << 3)
+#define AM335x_UART_MDR_CIR_PULSE_MODE_MASK   (0x3)
+#define AM335x_UART_MDR_CIR_PULSE_MODE_SHIFT   (4)
+#define AM335x_UART_MDR_IRRXINVERT_FLAG   (1 << 6)
+
+	union {
+		/** Status FIFO line status register (IrDA only) */
+		const ioport32_t sflsr;
+#define AM335x_IRDA_SFLSR_CRC_ERROR_FLAG   (1 << 1)
+#define AM335x_IRDA_SFLSR_ABORT_FLAG   (1 << 2)
+#define AM335x_IRDA_SFLSR_FTL_FLAG   (1 << 3)
+#define AM335x_IRDA_SFLSR_OE_FLAG   (1 << 4)
+
+		/** Transmit frame length low (IrDA only) */
+		ioport32_t txfll;
+#define AM335x_UART_TXFLL_MASK   (0xff)
+	};
+
+	union {
+		/** Dummy register to restart TX or RX (IrDA only) */
+		const ioport32_t resume;
+		/** Transmit frame length high (IrDA only) */
+		ioport32_t txflh;
+#define AM335x_UART_TXFLH_MASK   (0xff)
+	};
+
+	union {
+		/** Status FIFO register low (IrDA only) */
+		const ioport32_t sfregl;
+#define AM335x_UART_SFREGL_MASK   (0xff)
+		/** Received frame length low (IrDA only) */
+		ioport32_t rxfll;
+#define AM335x_UART_RXFLL_MASK   (0xff)
+	};
+
+	union {
+		/** Status FIFO register high (IrDA only) */
+		const ioport32_t sfregh;
+#define AM335x_UART_SFREGH_MASK   (0xf)
+		/** Received frame length high (IrDA only) */
+		ioport32_t rxflh;
+#define AM335x_UART_RXFLH_MASK   (0xf)
+	};
+
+	union {
+		/** UART autobauding status register */
+		const ioport32_t uasr;
+#define AM335x_UART_UASR_SPEED_MASK   (0x1f)
+#define AM335x_UART_UASR_SPEED_SHIFT   (0)
+#define AM335x_UART_UASR_8BIT_CHAR_FLAG   (1 << 5)
+#define AM335x_UART_UASR_PARITY_MASK   (0x3)
+#define AM335x_UART_UASR_PARITY_SHIFT   (6)
+
+		/** BOF control register (IrDA only) */
+		ioport32_t blr;
+#define AM335x_IRDA_BLR_XBOF_TYPE_FLAG   (1 << 6)
+#define AM335x_IRDA_BLR_STS_FIFO_RESET   (1 << 7)
+	};
+
+	/** Auxiliary control register (IrDA only) */
+	ioport32_t acreg;
+#define AM335x_IRDA_ACREG_EOT_EN_FLAG   (1 << 0)
+#define AM335x_IRDA_ACREG_ABORT_EN_FLAG   (1 << 1)
+#define AM335x_IRDA_ACREG_SCTX_EN_FLAG   (1 << 2)
+#define AM335x_IRDA_ACREG_SEND_SIP_FLAG   (1 << 3)
+#define AM335x_IRDA_ACREG_DIS_TX_UNDERRUN_FLAG   (1 << 4)
+#define AM335x_IRDA_ACREG_DIS_IR_RX_FLAG   (1 << 5)
+#define AM335x_IRDA_ACREG_SD_MOD_FLAG   (1 << 6)
+#define AM335x_IRDA_ACREG_PULSE_TYPE_FLAG   (1 << 7)
+
+	/** Supplementary control register */
+	ioport32_t scr;
+#define AM335x_UART_SCR_DMA_MODE_CTL_FLAG   (1 << 0)
+#define AM335x_UART_SCR_DMA_MODE_MASK   (0x3)
+#define AM335x_UART_SCR_DMA_MODE_SHIFT   (1)
+#define AM335x_UART_SCR_TX_EMPTY_CTL_IRQ_FLAG   (1 << 3)
+#define AM335x_UART_SCR_RX_CTS_WU_EN_FLAG   (1 << 4)
+#define AM335x_UART_SCR_TX_TRIG_GRANU1_FLAG   (1 << 6)
+#define AM335x_UART_SCR_RX_TRIG_GRANU1_FLAG   (1 << 7)
+
+	/** Supplementary status register */
+	const ioport32_t ssr;
+#define AM335x_UART_SSR_TX_FIFO_FULL_FLAG   (1 << 0)
+#define AM335x_UART_SSR_RX_CTS_WU_STS_FLAG   (1 << 1)
+#define AM335x_UART_SSR_DMA_COUNTER_RESET_FLAG   (1 << 2)
+
+	/** BOF Length register (IrDA only)*/
+	ioport32_t eblr;
+#define AM335x_IRDA_EBLR_DISABLED   (0x00)
+#define AM335x_IRDA_EBLR_RX_STOP_BITS(bits)   (bits & 0xff)
+
+	uint32_t padd0_;
+
+	/** Module version register */
+	const ioport32_t mvr;
+#define AM335x_UART_MVR_MINOR_MASK   (0xf)
+#define AM335x_UART_MVR_MINOR_SHIFT   (0)
+#define AM335x_UART_MVR_MAJOR_MASK   (0xf)
+#define AM335x_UART_MVR_MAJOR_SHIFT   (4)
+
+	/** System configuration register */
+	ioport32_t sysc;
+#define AM335x_UART_SYSC_AUTOIDLE_FLAG   (1 << 0)
+#define AM335x_UART_SYSC_SOFTRESET_FLAG   (1 << 1)
+#define AM335x_UART_SYSC_ENWAKEUP_FLAG   (1 << 2)
+#define AM335x_UART_SYSC_IDLE_MODE_MASK   (0x3)
+#define AM335x_UART_SYSC_IDLE_MODE_SHIFT   (3)
+#define AM335x_UART_SYSC_IDLE_MODE_FORCE   (0x0)
+#define AM335x_UART_SYSC_IDLE_MODE_NO   (0x1)
+#define AM335x_UART_SYSC_IDLE_MODE_SMART   (0x2)
+
+	/** System status register */
+	const ioport32_t syss;
+#define AM335x_UART_SYSS_RESETDONE_FLAG   (1 << 0)
+
+	/** Wake-up enable register */
+	ioport32_t wer;
+#define AM335x_UART_WER_CTS_ACTIVITY_FLAG  (1 << 0)
+#define AM335x_UART_WER_RI_ACTIVITY_FLAG  (1 << 2)
+#define AM335x_UART_WER_RX_ACTIVITY_FLAG  (1 << 4)
+#define AM335x_UART_WER_RHR_IRQ_FLAG  (1 << 5)
+#define AM335x_UART_WER_RLS_IRQ_FLAG  (1 << 6)
+#define AM335x_UART_WER_TX_WAKEUP_EN_FLAG  (1 << 7)
+
+	/** Carrier frequency prescaler */
+	ioport32_t cfps;
+#define AM335x_UART_CFPS_MASK   (0xff)
+
+	/** Number of bytes in RX fifo */
+	const ioport32_t rx_fifo_lvl;
+#define AM335x_UART_RX_FIFO_LVL_MASK   (0xff)
+
+	/** Number of bytes in TX fifo */
+	const ioport32_t tx_fifo_lvl;
+#define AM335x_UART_TX_FIFO_LVL_MASK   (0xff)
+
+	/** RX/TX empty interrupts */
+	ioport32_t ier2;
+#define AM335x_UART_IER2_RX_FIFO_EMPTY_IRQ_EN_FLAG  (1 << 0)
+#define AM335x_UART_IER2_TX_FIFO_EMPTY_IRQ_EN_FLAG  (1 << 1)
+
+	/** RX/TX empty status */
+	ioport32_t isr2;
+#define AM335x_UART_ISR2_RX_FIFO_EMPTY_FLAG  (1 << 0)
+#define AM335x_UART_ISR2_TX_FIFO_EMPTY_FLAG  (1 << 1)
+
+	/** Set the sample per bit if non default frequency is used */
+	ioport32_t freq_sel;
+#define AM335x_UART_FREQ_SEL_MASK  (0x000000FF)
+
+	uint32_t padd2_[2];
+
+	/** Mode definition register 3 */
+	ioport32_t mdr3;
+#define AM335x_UART_MDR3_DIS_CIR_RX_DEMOD_FLAG   (1 << 0)
+} am335x_uart_regs_t;
+
+#endif
+
+/**
+ * @}
+ */
Index: kernel/genarch/include/drivers/amdm37x/gpt.h
===================================================================
--- kernel/genarch/include/drivers/amdm37x/gpt.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
+++ kernel/genarch/include/drivers/amdm37x/gpt.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -0,0 +1,255 @@
+/*
+ * Copyright (c) 2012 Jan Vesely
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM/DM37x MPU general purpose timer driver.
+ */
+
+#ifndef KERN_AMDM37x_GPT_H_
+#define KERN_AMDM37x_GPT_H_
+
+#include <typedefs.h>
+#include <mm/km.h>
+
+/* AMDM37x TRM p. 2740 */
+#define AMDM37x_GPT1_BASE_ADDRESS  0x48318000
+#define AMDM37x_GPT1_SIZE  4096
+#define AMDM37x_GPT1_IRQ  37
+#define AMDM37x_GPT2_BASE_ADDRESS  0x49032000
+#define AMDM37x_GPT2_SIZE  4096
+#define AMDM37x_GPT2_IRQ  38
+#define AMDM37x_GPT3_BASE_ADDRESS  0x49034000
+#define AMDM37x_GPT3_SIZE  4096
+#define AMDM37x_GPT3_IRQ  39
+#define AMDM37x_GPT4_BASE_ADDRESS  0x49036000
+#define AMDM37x_GPT4_SIZE  4096
+#define AMDM37x_GPT4_IRQ  40
+#define AMDM37x_GPT5_BASE_ADDRESS  0x49038000
+#define AMDM37x_GPT5_SIZE  4096
+#define AMDM37x_GPT5_IRQ  41
+#define AMDM37x_GPT6_BASE_ADDRESS  0x4903a000
+#define AMDM37x_GPT6_SIZE  4096
+#define AMDM37x_GPT6_IRQ  42
+#define AMDM37x_GPT7_BASE_ADDRESS  0x4903c000
+#define AMDM37x_GPT7_SIZE  4096
+#define AMDM37x_GPT7_IRQ  43
+#define AMDM37x_GPT8_BASE_ADDRESS  0x4903e000
+#define AMDM37x_GPT8_SIZE  4096
+#define AMDM37x_GPT8_IRQ  44
+#define AMDM37x_GPT9_BASE_ADDRESS  0x49040000
+#define AMDM37x_GPT9_SIZE  4096
+#define AMDM37x_GPT9_IRQ  45
+#define AMDM37x_GPT10_BASE_ADDRESS  0x48086000
+#define AMDM37x_GPT10_SIZE  4096
+#define AMDM37x_GPT10_IRQ  46
+#define AMDM37x_GPT11_BASE_ADDRESS  0x48088000
+#define AMDM37x_GPT11_SIZE  4096
+#define AMDM37x_GPT11_IRQ  47
+
+
+/** GPT register map AMDM37x TRM p. 2740 */
+typedef struct {
+	/** IP revision */
+	const ioport32_t tidr;
+#define AMDM37x_GPT_TIDR_MINOR_MASK  (0xf)
+#define AMDM37x_GPT_TIDR_MINOR_SHIFT  (0)
+#define AMDM37x_GPT_TIDR_MAJOR_MASK  (0xf)
+#define AMDM37x_GPT_TIDR_MAJOR_SHIFT  (4)
+	uint32_t padd0_[3];
+
+	/** L4 Interface parameters */
+	ioport32_t tiocp_cfg;
+#define AMDM37x_GPT_TIOCP_CFG_AUTOIDLE_FLAG  (1 << 0)
+#define AMDM37x_GPT_TIOCP_CFG_SOFTRESET_FLAG  (1 << 1)
+#define AMDM37x_GPT_TIOCP_CFG_ENWAKEUP_FLAG  (1 << 2)
+#define AMDM37x_GPT_TIOCP_CFG_IDLEMODE_MASK  (0x3)
+#define AMDM37x_GPT_TIOCP_CFG_IDLEMODE_SHIFT  (3)
+#define AMDM37x_GPT_TIOCP_CFG_EMUFREE_FlAG  (1 << 5)
+#define AMDM37x_GPT_TIOCP_CFG_CLOCKACTIVITY_MASK  (0x3)
+#define AMDM37x_GPT_TIOCP_CFG_CLOCKACTIVITY_SHIFT (8)
+
+	/** Module status information, excluding irq */
+	const ioport32_t tistat;
+#define AMDM37x_GPT_TISTAT_RESET_DONE_FLAG  (1 << 0)
+
+	/** Interrupt status register */
+	ioport32_t tisr;
+#define AMDM37x_GPT_TISR_MAT_IRQ_FLAG  (1 << 0)
+#define AMDM37x_GPT_TISR_OVF_IRQ_FLAG  (1 << 1)
+#define AMDM37x_GPT_TISR_TCAR_IRQ_FLAG  (1 << 2)
+
+	/* Interrupt enable register */
+	ioport32_t tier;
+#define AMDM37x_GPT_TIER_MAT_IRQ_FLAG  (1 << 0)
+#define AMDM37x_GPT_TIER_OVF_IRQ_FLAG  (1 << 1)
+#define AMDM37x_GPT_TIER_TCAR_IRQ_FLAG  (1 << 2)
+
+	/** Wakeup enable register */
+	ioport32_t twer;
+#define AMDM37x_GPT_TWER_MAT_IRQ_FLAG  (1 << 0)
+#define AMDM37x_GPT_TWER_OVF_IRQ_FLAG  (1 << 1)
+#define AMDM37x_GPT_TWER_TCAR_IRQ_FLAG  (1 << 2)
+
+	/** Optional features control register */
+	ioport32_t tclr;
+#define AMDM37x_GPT_TCLR_ST_FLAG  (1 << 0)
+#define AMDM37x_GPT_TCLR_AR_FLAG  (1 << 1)
+#define AMDM37x_GPT_TCLR_PTV_MASK  (0x7)
+#define AMDM37x_GPT_TCLR_PTV_SHIFT  (2)
+#define AMDM37x_GPT_TCLR_PRE_FLAG  (1 << 5)
+#define AMDM37x_GPT_TCLR_CE_FLAG  (1 << 6)
+#define AMDM37x_GPT_TCLR_SCPWM  (1 << 7)
+#define AMDM37x_GPT_TCLR_TCM_MASK  (0x3)
+#define AMDM37x_GPT_TCLR_TCM_SHIFT  (8)
+#define AMDM37x_GPT_TCLR_TRG_MASK  (0x3)
+#define AMDM37x_GPT_TCLR_TRG_SHIFT (10)
+#define AMDM37x_GPT_TCLR_PT_FLAG  (1 << 12)
+#define AMDM37x_GPT_TCLR_CAPT_MODE_FLAG  (1 << 13)
+#define AMDM37x_GPT_TCLR_GPO_CFG_FLAG  (1 << 14)
+
+	/** Value of timer counter */
+	ioport32_t tccr;
+
+	/** Timer load register */
+	ioport32_t tldr;
+
+	/** Timer trigger register */
+	ioport32_t ttgr;
+
+	/** Write-posted pending register */
+	const ioport32_t twps;
+#define AMDM37x_GPT_TWPS_TCLR_FLAG  (1 << 0)
+#define AMDM37x_GPT_TWPS_TCRR_FLAG  (1 << 1)
+#define AMDM37x_GPT_TWPS_TLDR_FLAG  (1 << 2)
+#define AMDM37x_GPT_TWPS_TTGR_FLAG  (1 << 3)
+#define AMDM37x_GPT_TWPS_TMAR_FLAG  (1 << 4)
+#define AMDM37x_GPT_TWPS_TPIR_FLAG  (1 << 5)
+#define AMDM37x_GPT_TWPS_TNIR_FLAG  (1 << 6)
+#define AMDM37x_GPT_TWPS_TCVR_FLAG  (1 << 7)
+#define AMDM37x_GPT_TWPS_TOCR_FLAG  (1 << 8)
+#define AMDM37x_GPT_TWPS_TOWR_FLAG  (1 << 9)
+
+	/** Timer match register */
+	ioport32_t tmar;
+
+	/** Capture value 1 register */
+	const ioport32_t tcar1;
+
+	/** Software interface control register */
+	ioport32_t tsicr;
+#define AMDM37x_GPT_TSICR_SFT_FLAG  (1 << 1)
+#define AMDM37x_GPT_TSICR_POSTED_FLAG  (1 << 2)
+
+	/** Capture value 2 register */
+	const ioport32_t tcar2;
+
+	/* GPT1,2,10 only (used for 1ms time period generation)*/
+
+	/** Positive increment register */
+	ioport32_t tpir;
+
+	/** Negative increment register */
+	ioport32_t tnir;
+
+	/** Counter value register */
+	ioport32_t tcvr;
+
+	/** Mask the tick interrupt for selected number of ticks */
+	ioport32_t tocr;
+
+	/** Number of masked overflow interrupts */
+	ioport32_t towr;
+} amdm37x_gpt_regs_t;
+
+typedef struct {
+	amdm37x_gpt_regs_t *regs;
+	bool special_available;
+} amdm37x_gpt_t;
+
+static inline void amdm37x_gpt_timer_ticks_init(
+    amdm37x_gpt_t* timer, uintptr_t ioregs, size_t iosize, unsigned hz)
+{
+	/* Set 32768 Hz clock as source */
+	// TODO find a nicer way to setup 32kHz clock source for timer1
+	// reg 0x48004C40 is CM_CLKSEL_WKUP see page 485 of the manual
+	ioport32_t *clksel = (void*) km_map(0x48004C40, 4, PAGE_NOT_CACHEABLE);
+	*clksel &= ~1;
+	km_unmap((uintptr_t)clksel, 4);
+
+	ASSERT(timer);
+	/* Map control register */
+	timer->regs = (void*) km_map(ioregs, iosize, PAGE_NOT_CACHEABLE);
+
+	/* Set autoreload */
+	timer->regs->tclr = AMDM37x_GPT_TCLR_AR_FLAG;
+
+	timer->special_available = (
+	    (ioregs == AMDM37x_GPT1_BASE_ADDRESS) ||
+	    (ioregs == AMDM37x_GPT2_BASE_ADDRESS) ||
+	    (ioregs == AMDM37x_GPT10_BASE_ADDRESS));
+	timer->regs->tldr = 0xffffffff - (32768 / hz) + 1;
+	timer->regs->tccr = 0xffffffff - (32768 / hz) + 1;
+	if (timer->special_available) {
+		/* Set values for according to formula (manual p. 2733) */
+		/* Use temporary variables for easier debugging */
+		const uint32_t tpir =
+		    ((32768 / hz + 1) * 1000000) - (32768000L * (1000 / hz));
+		const uint32_t tnir =
+		    ((32768 / hz) * 1000000) - (32768000 * (1000 / hz));
+		timer->regs->tpir = tpir;
+		timer->regs->tnir = tnir;
+	}
+
+}
+
+static inline void amdm37x_gpt_timer_ticks_start(amdm37x_gpt_t* timer)
+{
+	ASSERT(timer);
+	ASSERT(timer->regs);
+	/* Enable overflow interrupt */
+	timer->regs->tier |= AMDM37x_GPT_TIER_OVF_IRQ_FLAG;
+	/* Start timer */
+	timer->regs->tclr |= AMDM37x_GPT_TCLR_ST_FLAG;
+}
+
+static inline void amdm37x_gpt_irq_ack(amdm37x_gpt_t* timer)
+{
+	ASSERT(timer);
+	ASSERT(timer->regs);
+	/* Clear all pending interrupts */
+	timer->regs->tisr = timer->regs->tisr;
+}
+
+#endif
+
+/**
+ * @}
+ */
Index: kernel/genarch/include/drivers/amdm37x/irc.h
===================================================================
--- kernel/genarch/include/drivers/amdm37x/irc.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
+++ kernel/genarch/include/drivers/amdm37x/irc.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2012 Jan Vesely
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM/DM37x MPU on-chip interrupt controller driver.
+ */
+
+#ifndef KERN_AMDM37x_IRQC_H_
+#define KERN_AMDM37x_IRQC_H_
+
+/* AMDM37x TRM p. 1079 */
+#define AMDM37x_IRC_BASE_ADDRESS 0x48200000
+#define AMDM37x_IRC_SIZE 4096
+
+#define AMDM37x_IRC_IRQ_COUNT 96
+
+#include <typedefs.h>
+
+typedef struct {
+	const ioport32_t revision; /**< Revision */
+#define AMDM37x_IRC_REV_MASK (0xff)
+
+	uint8_t padd0_[12];
+
+	ioport32_t sysconfig; /**< SYS config */
+#define AMDM37x_IRC_SYSCONFIG_AUTOIDLE_FLAG (1 << 0)
+#define AMDM37x_IRC_SYSCONFIG_SOFTRESET_FLAG (1 << 1)
+
+	const ioport32_t sysstatus; /**< SYS status */
+#define AMDM37x_IRC_SYSSTATUS_RESET_DONE_FLAG (1 << 0)
+
+	uint8_t padd1_[40];
+
+	const ioport32_t sir_irq;   /**< Currently active irq number */
+#define AMDM37x_IRC_SIR_IRQ_ACTIVEIRQ_MASK (0x7f)
+#define AMDM37x_IRC_SIR_IRQ_SPURIOUSIRQFLAG_MASK (0xfffffff8)
+
+	const ioport32_t sir_fiq;
+#define AMDM37x_IRC_SIR_FIQ_ACTIVEIRQ_MASK (0x7f)
+#define AMDM37x_IRC_SIR_FIQ_SPURIOUSIRQFLAG_MASK (0xfffffff8)
+
+	ioport32_t control;   /**< New interrupt agreement. */
+#define AMDM37x_IRC_CONTROL_NEWIRQAGR_FLAG (1 << 0)
+#define AMDM37x_IRC_CONTROL_NEWFIQAGR_FLAG (1 << 1)
+
+	ioport32_t protection;  /**< Protect other registers. */
+#define AMDM37x_IRC_PROTECTION_PROETCTION_FLAG (1 << 0)
+
+	ioport32_t idle;   /**< Idle and autogating */
+#define AMDM37x_IRC_IDLE_FUNCIDLE_FLAG (1 << 0)
+#define AMDM37x_IRC_IDLE_TURBO_FLAG (1 << 1)
+
+	uint8_t padd2_[12];
+
+	ioport32_t irq_priority; /**< Active IRQ priority */
+#define AMDM37x_IRC_IRQ_PRIORITY_IRQPRIORITY_MASK (0x7f)
+#define AMDM37x_IRC_IRQ_PRIORITY_SPURIOUSIRQFLAG_MASK (0xfffffff8)
+
+	ioport32_t fiq_priority; /**< Active FIQ priority */
+#define AMDM37x_IRC_FIQ_PRIORITY_FIQPRIORITY_MASK (0x7f)
+#define AMDM37x_IRC_FIQ_PRIORITY_SPURIOUSFIQFLAG_MASK (0xfffffff8)
+
+	ioport32_t threshold; /**< Priority threshold */
+#define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_MASK (0xff)
+#define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_ENABLED (0x00)
+#define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_DISABLED (0xff)
+
+	uint8_t padd3__[20];
+
+	struct {
+		const ioport32_t itr;   /**< Interrupt input status before masking */
+		ioport32_t mir;   /**< Interrupt mask */
+		ioport32_t mir_clear; /**< Clear mir mask bits */
+		ioport32_t mir_set;   /**< Set mir mask bits */
+		ioport32_t isr_set;   /**< Set software interrupt bits */
+		ioport32_t isr_clear; /**< Clear software interrupt bits */
+		const ioport32_t pending_irq; /**< IRQ status after masking */
+		const ioport32_t pending_fiq; /**< FIQ status after masking */
+	} interrupts[3];
+
+	uint8_t padd4_[32];
+
+	ioport32_t ilr[96];   /**< FIQ/IRQ steering */
+#define AMDM37x_IRC_ILR_FIQNIRQ (1 << 0)
+#define AMDM37x_IRC_ILR_PRIORITY_MASK (0x3f)
+#define AMDM37x_IRC_ILR_PRIORITY_SHIFT (2)
+
+} amdm37x_irc_regs_t;
+
+static inline void amdm37x_irc_dump(amdm37x_irc_regs_t *regs)
+{
+#define DUMP_REG(name) \
+	printf("%s %p(%x).\n", #name, &regs->name, regs->name);
+
+	DUMP_REG(revision);
+	DUMP_REG(sysconfig);
+	DUMP_REG(sysstatus);
+	DUMP_REG(sir_irq);
+	DUMP_REG(sir_fiq);
+	DUMP_REG(control);
+	DUMP_REG(protection);
+	DUMP_REG(idle);
+	DUMP_REG(irq_priority);
+	DUMP_REG(fiq_priority);
+	DUMP_REG(threshold);
+
+	for (int i = 0; i < 3; ++i) {
+		DUMP_REG(interrupts[i].itr);
+		DUMP_REG(interrupts[i].mir);
+		DUMP_REG(interrupts[i].isr_set);
+		DUMP_REG(interrupts[i].pending_irq);
+		DUMP_REG(interrupts[i].pending_fiq);
+	}
+	for (int i = 0; i < AMDM37x_IRC_IRQ_COUNT; ++i) {
+		DUMP_REG(ilr[i]);
+	}
+
+#undef DUMP_REG
+}
+
+static inline void amdm37x_irc_init(amdm37x_irc_regs_t *regs)
+{
+	/* AMDM37x TRM sec 12.5.1 p. 2425 */
+	/* Program system config register */
+	//TODO enable this when you know the meaning
+	//regs->sysconfig |= AMDM37x_IRC_SYSCONFIG_AUTOIDLE_FLAG;
+
+	/* Program idle register */
+	//TODO enable this when you know the meaning
+	//regs->sysconfig |= AMDM37x_IRC_IDLE_TURBO_FLAG;
+
+	/* Program ilr[m] assign priority, decide fiq */
+	for (unsigned i = 0; i < AMDM37x_IRC_IRQ_COUNT; ++i) {
+		regs->ilr[i] = 0; /* highest prio(default) route to irq */
+	}
+
+	/* Disable all interrupts */
+	regs->interrupts[0].mir_set = 0xffffffff;
+	regs->interrupts[1].mir_set = 0xffffffff;
+	regs->interrupts[2].mir_set = 0xffffffff;
+}
+
+static inline unsigned amdm37x_irc_inum_get(amdm37x_irc_regs_t *regs)
+{
+	return regs->sir_irq & AMDM37x_IRC_SIR_IRQ_ACTIVEIRQ_MASK;
+}
+
+static inline void amdm37x_irc_irq_ack(amdm37x_irc_regs_t *regs)
+{
+	regs->control = AMDM37x_IRC_CONTROL_NEWIRQAGR_FLAG;
+}
+
+static inline void amdm37x_irc_fiq_ack(amdm37x_irc_regs_t *regs)
+{
+	regs->control = AMDM37x_IRC_CONTROL_NEWFIQAGR_FLAG;
+}
+
+static inline void amdm37x_irc_enable(amdm37x_irc_regs_t *regs, unsigned inum)
+{
+	ASSERT(inum < AMDM37x_IRC_IRQ_COUNT);
+	const unsigned set = inum / 32;
+	const unsigned pos = inum % 32;
+	regs->interrupts[set].mir_clear = (1 << pos);
+}
+
+static inline void amdm37x_irc_disable(amdm37x_irc_regs_t *regs, unsigned inum)
+{
+	ASSERT(inum < AMDM37x_IRC_IRQ_COUNT);
+	const unsigned set = inum / 32;
+	const unsigned pos = inum % 32;
+	regs->interrupts[set].mir_set = (1 << pos);
+}
+
+#endif
+
+/**
+ * @}
+ */
Index: kernel/genarch/include/drivers/amdm37x/uart.h
===================================================================
--- kernel/genarch/include/drivers/amdm37x/uart.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
+++ kernel/genarch/include/drivers/amdm37x/uart.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2012 Jan Vesely
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AMDM37x UART driver
+ */
+
+#ifndef _AMDM37x_UART_H_
+#define _AMDM37x_UART_H_
+
+#include "uart_regs.h"
+
+/* AMDM37x TRM p. 2950 */
+#define AMDM37x_UART1_BASE_ADDRESS   0x4806a000
+#define AMDM37x_UART1_SIZE   1024
+#define AMDM37x_UART1_IRQ   72 /* AMDM37x TRM p. 2418 */
+
+#define AMDM37x_UART2_BASE_ADDRESS   0x4806b000
+#define AMDM37x_UART2_SIZE   1024
+#define AMDM37x_UART2_IRQ   73 /* AMDM37x TRM p. 2418 */
+
+#define AMDM37x_UART3_BASE_ADDRESS   0x49020000
+#define AMDM37x_UART3_SIZE   1024
+#define AMDM37x_UART3_IRQ   74 /* AMDM37x TRM p. 2418 */
+
+#define AMDM37x_UART4_BASE_ADDRESS   0x49042000
+#define AMDM37x_UART4_SIZE   1024
+#define AMDM37x_UART4_IRQ   80 /* AMDM37x TRM p. 2418 */
+
+typedef struct {
+	amdm37x_uart_regs_t *regs;
+	indev_t *indev;
+	outdev_t outdev;
+	irq_t irq;
+} amdm37x_uart_t;
+
+
+bool amdm37x_uart_init(amdm37x_uart_t *, inr_t, uintptr_t, size_t);
+void amdm37x_uart_input_wire(amdm37x_uart_t *, indev_t *);
+
+#endif
+
+/**
+ * @}
+ */
Index: kernel/genarch/include/drivers/amdm37x/uart_regs.h
===================================================================
--- kernel/genarch/include/drivers/amdm37x/uart_regs.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
+++ kernel/genarch/include/drivers/amdm37x/uart_regs.h	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -0,0 +1,431 @@
+/*
+ * Copyright (c) 2012 Jan Vesely
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AMDM37x UART memory mapped registers.
+ */
+
+#ifndef KERN_AMDM37x_UART_H_
+#define KERN_AMDM37x_UART_H_
+
+#include <typedefs.h>
+#include <console/chardev.h>
+#include <ddi/irq.h>
+
+typedef struct {
+	union {
+		/** Stores lower part of the 14-bit baud divisor */
+		ioport32_t dll;
+#define AMDM37x_UART_DLL_MASK   (0xff)
+
+		/** Receive holding register */
+		const ioport32_t rhr;
+#define AMDM37x_UART_RHR_MASK   (0xff)
+
+		/** Transmit holding register */
+		ioport32_t thr;
+#define AMDM37x_UART_THR_MASK   (0xff)
+	};
+
+	union {
+		/** Stores higher part of the 14-bit baud divisor */
+		ioport32_t dlh;
+#define AMDM37x_UART_DLH_MASK   (0x1f)
+
+		/** Interrupt enable registers */
+		ioport32_t ier;
+#define AMDM37x_UART_IER_RHR_IRQ_FLAG   (1 << 0)
+#define AMDM37x_UART_IER_THR_IRQ_FLAG   (1 << 1)
+#define AMDM37x_UART_IER_LINE_STS_IRQ_FLAG   (1 << 2)
+#define AMDM37x_UART_IER_MODEM_STS_IRQ_FLAG   (1 << 3)
+#define AMDM37x_UART_IER_SLEEP_MODE_FLAG   (1 << 4)
+#define AMDM37x_UART_IER_XOFF_IRQ_FLAG   (1 << 5)
+#define AMDM37x_UART_IER_RTS_IRQ_FLAG   (1 << 6)
+#define AMDM37x_UART_IER_CTS_IRQ_FLAG   (1 << 7)
+
+#define AMDM37x_CIR_IER_RHR_IRQ_FLAG   (1 << 0)
+#define AMDM37x_CIR_IER_THR_IRQ_FLAG   (1 << 1)
+#define AMDM37x_CIR_IER_RX_STOP_IRQ_FLAG   (1 << 2)
+#define AMDM37x_CIR_IER_RX_OVERRUN_IRQ_FLAG   (1 << 3)
+#define AMDM37x_CIR_IER_TX_STS_IRQ_FLAG   (1 << 5)
+
+#define AMDM37x_IRDA_IER_RHR_IRQ_FLAG   (1 << 0)
+#define AMDM37x_IRDA_IER_THR_IRQ_FLAG   (1 << 1)
+#define AMDM37x_IRDA_IER_LAST_RX_BYTE_IRQ_FLAG   (1 << 2)
+#define AMDM37x_IRDA_IER_RX_OVERRUN_IRQ_FLAG   (1 << 3)
+#define AMDM37x_IRDA_IER_STS_FIFO_TRIG_IRQ_FLAG   (1 << 4)
+#define AMDM37x_IRDA_IER_TX_STS_IRQ_FLAG   (1 << 5)
+#define AMDM37x_IRDA_IER_LINE_STS_IRQ_FLAG   (1 << 6)
+#define AMDM37x_IRDA_IER_EOF_IRQ_FLAG   (1 << 7)
+	};
+
+	union {
+		/** Interrupt identification register */
+		const ioport32_t iir;
+#define AMDM37x_UART_IIR_IRQ_PENDING_FLAG   (1 << 0)
+#define AMDM37x_UART_IIR_TYPE_MASK   (0x1f)
+#define AMDM37x_UART_IIR_TYPE_SHIFT   (1)
+#define AMDM37x_UART_IIR_FCR_MASK   (0x3)
+#define AMDM37x_UART_IIR_FCR_SHIFT   (6)
+
+#define AMDM37x_CIR_IIR_RHR_IRQ_FLAG   (1 << 0)
+#define AMDM37x_CIR_IIR_THR_IRQ_FLAG   (1 << 1)
+#define AMDM37x_CIR_IIR_RX_STOP_IRQ_FLAG   (1 << 2)
+#define AMDM37x_CIR_IIR_RX_OE_IRQ_FLAG   (1 << 3)
+#define AMDM37x_CIR_IIR_TX_STS_IRQ_FLAG   (1 << 5)
+
+#define AMDM37x_IRDA_IIR_RHR_IRQ_FLAG   (1 << 0)
+#define AMDM37x_IRDA_IIR_THR_IRQ_FLAG   (1 << 1)
+#define AMDM37x_IRDA_IIR_RX_FIFO_LB_IRQ_FLAG   (1 << 2)
+#define AMDM37x_IRDA_IIR_RX_OE_IRQ_FLAG   (1 << 3)
+#define AMDM37x_IRDA_IIR_STS_FIFO_IRQ_FLAG   (1 << 4)
+#define AMDM37x_IRDA_IIR_TX_STS_IRQ_FLAG   (1 << 5)
+#define AMDM37x_IRDA_IIR_LINE_STS_IRQ_FLAG   (1 << 6)
+#define AMDM37x_IRDA_IIR_EOF_IRQ_FLAG   (1 << 7)
+
+		/** FIFO control register */
+		ioport32_t fcr;
+#define AMDM37x_UART_FCR_FIFO_EN_FLAG   (1 << 0)
+#define AMDM37x_UART_FCR_RX_FIFO_CLR_FLAG   (1 << 1)
+#define AMDM37x_UART_FCR_TX_FIFO_CLR_FLAG   (1 << 3)
+#define AMDM37x_UART_FCR_DMA_MODE_FLAG   (1 << 4)
+
+#define AMDM37x_UART_FCR_TX_FIFO_TRIG_MASK   (0x3)
+#define AMDM37x_UART_FCR_TX_FIFO_TRIG_SHIFT   (4)
+
+#define AMDM37x_UART_FCR_RX_FIFO_TRIG_MASK   (0x3)
+#define AMDM37x_UART_FCR_RX_FIFO_TRIG_SHIFT   (6)
+
+		/** Enhanced feature register */
+		ioport32_t efr;
+#define AMDM37x_UART_EFR_SW_FLOW_CTRL_RX_MASK   (0x3)
+#define AMDM37x_UART_EFR_SW_FLOW_CTRL_RX_SHIFT   (0)
+#define AMDM37x_UART_EFR_SW_FLOW_CTRL_TX_MASK   (0x3)
+#define AMDM37x_UART_EFR_SW_FLOW_CTRL_TX_SHIFT   (2)
+
+#define AMDM37x_UART_EFR_SW_FLOW_CTRL_NONE   (0x0)
+#define AMDM37x_UART_EFR_SW_FLOW_CTRL_X2   (0x1)
+#define AMDM37x_UART_EFR_SW_FLOW_CTRL_X1   (0x2)
+#define AMDM37x_UART_EFR_SW_FLOW_CTRL_XBOTH   (0x3)
+
+#define AMDM37x_UART_EFR_ENH_FLAG   (1 << 4)
+#define AMDM37x_UART_EFR_SPEC_CHAR_FLAG   (1 << 5)
+#define AMDM37x_UART_EFR_AUTO_RTS_EN_FLAG   (1 << 6)
+#define AMDM37x_UART_EFR_AUTO_CTS_EN_FLAG   (1 << 7)
+	};
+
+	/** Line control register */
+	ioport32_t lcr;
+#define AMDM37x_UART_LCR_CHAR_LENGTH_MASK   (0x3)
+#define AMDM37x_UART_LCR_CHAR_LENGTH_SHIFT   (0)
+#define AMDM37x_UART_LCR_CHAR_LENGTH_5BITS   (0x0)
+#define AMDM37x_UART_LCR_CHAR_LENGTH_6BITS   (0x1)
+#define AMDM37x_UART_LCR_CHAR_LENGTH_7BITS   (0x2)
+#define AMDM37x_UART_LCR_CHAR_LENGTH_8BITS   (0x3)
+#define AMDM37x_UART_LCR_NB_STOP_FLAG   (1 << 2)
+#define AMDM37x_UART_LCR_PARITY_EN_FLAG   (1 << 3)
+#define AMDM37x_UART_LCR_PARITY_TYPE1_FLAG   (1 << 4)
+#define AMDM37x_UART_LCR_PARITY_TYPE2_FLAG   (1 << 5)
+#define AMDM37x_UART_LCR_BREAK_EN_FLAG   (1 << 6)
+#define AMDM37x_UART_LCR_DIV_EN_FLAG   (1 << 7)
+
+
+	union {
+		/** Modem control register */
+		ioport32_t mcr;
+#define AMDM37x_UART_MCR_DTR_FLAG   (1 << 0)
+#define AMDM37x_UART_MCR_RTS_FLAG   (1 << 1)
+#define AMDM37x_UART_MCR_RI_STS_CH_FLAG   (1 << 2)
+#define AMDM37x_UART_MCR_CD_STS_CH_FLAG   (1 << 3)
+#define AMDM37x_UART_MCR_LOOPBACK_EN_FLAG   (1 << 4)
+#define AMDM37x_UART_MCR_XON_EN_FLAG   (1 << 5)
+#define AMDM37x_UART_MCR_TCR_TLR_FLAG   (1 << 6)
+
+		/** UART: XON1 char, IRDA: ADDR1 address */
+		ioport32_t xon1_addr1;
+#define AMDM37x_UART_XON1_ADDR1_MASK   (0xff)
+	};
+
+	union {
+		/** Line status register */
+		const ioport32_t lsr;
+#define AMDM37x_UART_LSR_RX_FIFO_E_FLAG   (1 << 0)
+#define AMDM37x_UART_LSR_RX_OE_FLAG   (1 << 1)
+#define AMDM37x_UART_LSR_RX_PE_FLAG   (1 << 2)
+#define AMDM37x_UART_LSR_RX_FE_FLAG   (1 << 3)
+#define AMDM37x_UART_LSR_RX_BI_FLAG   (1 << 4)
+#define AMDM37x_UART_LSR_TX_FIFO_E_FLAG   (1 << 5)
+#define AMDM37x_UART_LSR_TX_SR_E_FLAG   (1 << 6)
+#define AMDM37x_UART_LSR_RX_FIFO_STS_FLAG   (1 << 7)
+
+#define AMDM37x_CIR_LSR_RX_FIFO_E_FLAG   (1 << 0)
+#define AMDM37x_CIR_LSR_RX_STOP_FLAG   (1 << 5)
+#define AMDM37x_CIR_LSR_THR_EMPTY_FLAG   (1 << 7)
+
+#define AMDM37x_IRDA_LSR_RX_FIFO_E_FLAG   (1 << 0)
+#define AMDM37x_IRDA_LSR_STS_FIFO_E_FLAG   (1 << 1)
+#define AMDM37x_IRDA_LSR_CRC_FLAG   (1 << 2)
+#define AMDM37x_IRDA_LSR_ABORT_FLAG   (1 << 3)
+#define AMDM37x_IRDA_LSR_FTL_FLAG   (1 << 4)
+#define AMDM37x_IRDA_LSR_RX_LAST_FLAG   (1 << 5)
+#define AMDM37x_IRDA_LSR_STS_FIFO_FULL_FLAG   (1 << 6)
+#define AMDM37x_IRDA_LSR_THR_EMPTY_FLAG   (1 << 7)
+
+		/** UART: XON2 char, IRDA: ADDR2 address */
+		ioport32_t xon2_addr2;
+	};
+
+	union {
+		/** Modem status register */
+		const ioport32_t msr;
+#define AMDM37x_UART_MSR_CTS_STS_FLAG   (1 << 0)
+#define AMDM37x_UART_MSR_DSR_STS_FLAG   (1 << 1)
+#define AMDM37x_UART_MSR_RI_STS_FLAG   (1 << 2)
+#define AMDM37x_UART_MSR_DCD_STS_FLAG   (1 << 3)
+#define AMDM37x_UART_MSR_NCTS_STS_FLAG   (1 << 4)
+#define AMDM37x_UART_MSR_NDSR_STS_FLAG   (1 << 5)
+#define AMDM37x_UART_MSR_NRI_STS_FLAG   (1 << 6)
+#define AMDM37x_UART_MSR_NCD_STS_FLAG   (1 << 7)
+
+		/** Transmission control register */
+		ioport32_t tcr;
+#define AMDM37x_UART_TCR_FIFO_TRIG_MASK   (0xf)
+#define AMDM37x_UART_TCR_FIFO_TRIG_HALT_SHIFT   (0)
+#define AMDM37x_UART_TCR_FIFO_TRIG_START_SHIFT   (4)
+
+		/** UART: XOFF1 char */
+		ioport32_t xoff1;
+#define AMDM37x_UART_XOFF1_MASK   (0xff)
+	};
+
+	union {
+		/* Scratchpad register, does nothing */
+		ioport32_t spr;
+#define AMDM37x_UART_SPR_MASK   (0xff)
+
+		/* Trigger level register */
+		ioport32_t tlr;
+#define AMDM37x_UART_TLR_LEVEL_MASK   (0xf)
+#define AMDM37x_UART_TLR_TX_FIFO_TRIG_SHIFT   (0)
+#define AMDM37x_UART_TLR_RX_FIFO_TRIG_SHIFT   (4)
+
+		/** UART: XOFF2 char */
+		ioport32_t xoff2;
+#define AMDM37x_UART_XOFF2_MASK   (0xff)
+	};
+
+	/** Mode definition register. */
+	ioport32_t mdr1;
+#define AMDM37x_UART_MDR_MS_MASK   (0x7)
+#define AMDM37x_UART_MDR_MS_SHIFT   (0)
+#define AMDM37x_UART_MDR_MS_UART16   (0x0)
+#define AMDM37x_UART_MDR_MS_SIR   (0x1)
+#define AMDM37x_UART_MDR_MS_UART16_AUTO   (0x2)
+#define AMDM37x_UART_MDR_MS_UART13   (0x3)
+#define AMDM37x_UART_MDR_MS_MIR   (0x4)
+#define AMDM37x_UART_MDR_MS_FIR   (0x5)
+#define AMDM37x_UART_MDR_MS_CIR   (0x6)
+#define AMDM37x_UART_MDR_MS_DISABLE   (0x7)
+
+#define AMDM37x_UART_MDR_IR_SLEEP_FLAG   (1 << 3)
+#define AMDM37x_UART_MDR_SET_TXIR_FLAG   (1 << 4)
+#define AMDM37x_UART_MDR_SCT_FLAG   (1 << 5)
+#define AMDM37x_UART_MDR_SIP_FLAG   (1 << 6)
+#define AMDM37x_UART_MDR_FRAME_END_MODE_FLAG   (1 << 7)
+
+	/** Mode definition register */
+	ioport32_t mdr2;
+#define AMDM37x_UART_MDR_IRTX_UNDERRUN_FLAG   (1 << 0)
+#define AMDM37x_UART_MDR_STS_FIFO_TRIG_MASK   (0x3)
+#define AMDM37x_UART_MDR_STS_FIFO_TRIG_SHIFT   (1)
+#define AMDM37x_UART_MDR_PULSE_SHAPING_FLAG   (1 << 3)
+#define AMDM37x_UART_MDR_CIR_PULSE_MODE_MASK   (0x3)
+#define AMDM37x_UART_MDR_CIR_PULSE_MODE_SHIFT   (4)
+#define AMDM37x_UART_MDR_IRRXINVERT_FLAG   (1 << 6)
+
+
+	/* UART3 specific */
+	union {
+		/** Status FIFO line status register (IrDA only) */
+		const ioport32_t sflsr;
+#define AMDM37x_IRDA_SFLSR_CRC_ERROR_FLAG   (1 << 1)
+#define AMDM37x_IRDA_SFLSR_ABORT_FLAG   (1 << 2)
+#define AMDM37x_IRDA_SFLSR_FTL_FLAG   (1 << 3)
+#define AMDM37x_IRDA_SFLSR_OE_FLAG   (1 << 4)
+
+		/** Transmit frame length low (IrDA only) */
+		ioport32_t txfll;
+#define AMDM37x_UART_TXFLL_MASK   (0xff)
+	};
+
+	/* UART3 specific */
+	union {
+		/** Dummy register to restart TX or RX (IrDA only) */
+		const ioport32_t resume;
+		/** Transmit frame length high (IrDA only) */
+		ioport32_t txflh;
+#define AMDM37x_UART_TXFLH_MASK   (0xff)
+	};
+
+	/* UART3 specific */
+	union {
+		/** Status FIFO register low (IrDA only) */
+		const ioport32_t sfregl;
+#define AMDM37x_UART_SFREGL_MASK   (0xff)
+		/** Received frame length low (IrDA only) */
+		ioport32_t rxfll;
+#define AMDM37x_UART_RXFLL_MASK   (0xff)
+	};
+
+	/* UART3 specific */
+	union {
+		/** Status FIFO register high (IrDA only) */
+		const ioport32_t sfregh;
+#define AMDM37x_UART_SFREGH_MASK   (0xf)
+		/** Received frame length high (IrDA only) */
+		ioport32_t rxflh;
+#define AMDM37x_UART_RXFLH_MASK   (0xf)
+	};
+
+	union {
+		/** UART autobauding status register */
+		const ioport32_t uasr;
+#define AMDM37x_UART_UASR_SPEED_MASK   (0x1f)
+#define AMDM37x_UART_UASR_SPEED_SHIFT   (0)
+#define AMDM37x_UART_UASR_8BIT_CHAR_FLAG   (1 << 5)
+#define AMDM37x_UART_UASR_PARITY_MASK   (0x3)
+#define AMDM37x_UART_UASR_PARITY_SHIFT   (6)
+
+		/** BOF control register (IrDA only) */
+		ioport32_t blr; /* UART3 specific */
+#define AMDM37x_IRDA_BLR_XBOF_TYPE_FLAG   (1 << 6)
+#define AMDM37x_IRDA_BLR_STS_FIFO_RESET   (1 << 7)
+	};
+
+	/** Auxiliary control register (IrDA only) */
+	ioport32_t acreg; /* UART3 specific */
+#define AMDM37x_IRDA_ACREG_EOT_EN_FLAG   (1 << 0)
+#define AMDM37x_IRDA_ACREG_ABORT_EN_FLAG   (1 << 1)
+#define AMDM37x_IRDA_ACREG_SCTX_EN_FLAG   (1 << 2)
+#define AMDM37x_IRDA_ACREG_SEND_SIP_FLAG   (1 << 3)
+#define AMDM37x_IRDA_ACREG_DIS_TX_UNDERRUN_FLAG   (1 << 4)
+#define AMDM37x_IRDA_ACREG_DIS_IR_RX_FLAG   (1 << 5)
+#define AMDM37x_IRDA_ACREG_SD_MOD_FLAG   (1 << 6)
+#define AMDM37x_IRDA_ACREG_PULSE_TYPE_FLAG   (1 << 7)
+
+	/** Supplementary control register */
+	ioport32_t scr;
+#define AMDM37x_UART_SCR_DMA_MODE_CTL_FLAG   (1 << 0)
+#define AMDM37x_UART_SCR_DMA_MODE_MASK   (0x3)
+#define AMDM37x_UART_SCR_DMA_MODE_SHIFT   (1)
+#define AMDM37x_UART_SCR_TX_EMPTY_CTL_IRQ_FLAG   (1 << 3)
+#define AMDM37x_UART_SCR_RX_CTS_WU_EN_FLAG   (1 << 4)
+#define AMDM37x_UART_SCR_TX_TRIG_GRANU1_FLAG   (1 << 6)
+#define AMDM37x_UART_SCR_RX_TRIG_GRANU1_FLAG   (1 << 7)
+
+	/** Supplementary status register */
+	const ioport32_t ssr;
+#define AMDM37x_UART_SSR_TX_FIFO_FULL_FLAG   (1 << 0)
+#define AMDM37x_UART_SSR_RX_CTS_WU_STS_FLAG   (1 << 1)
+#define AMDM37x_UART_SSR_DMA_COUNTER_RESET_FLAG   (1 << 2)
+
+	/** BOF Length register (IrDA only)*/
+	ioport32_t eblr; /* UART3 specific */
+#define AMDM37x_IRDA_EBLR_DISABLED   (0x00)
+#define AMDM37x_IRDA_EBLR_RX_STOP_BITS(bits)   (bits & 0xff)
+
+	uint32_t padd0_;
+
+	/** Module version register */
+	const ioport32_t mvr;
+#define AMDM37x_UART_MVR_MINOR_MASK   (0xf)
+#define AMDM37x_UART_MVR_MINOR_SHIFT   (0)
+#define AMDM37x_UART_MVR_MAJOR_MASK   (0xf)
+#define AMDM37x_UART_MVR_MAJOR_SHIFT   (4)
+
+	/** System configuration register */
+	ioport32_t sysc;
+#define AMDM37x_UART_SYSC_AUTOIDLE_FLAG   (1 << 0)
+#define AMDM37x_UART_SYSC_SOFTRESET_FLAG   (1 << 1)
+#define AMDM37x_UART_SYSC_ENWAKEUP_FLAG   (1 << 2)
+#define AMDM37x_UART_SYSC_IDLE_MODE_MASK   (0x3)
+#define AMDM37x_UART_SYSC_IDLE_MODE_SHIFT   (3)
+#define AMDM37x_UART_SYSC_IDLE_MODE_FORCE   (0x0)
+#define AMDM37x_UART_SYSC_IDLE_MODE_NO   (0x1)
+#define AMDM37x_UART_SYSC_IDLE_MODE_SMART   (0x2)
+
+	/** System status register */
+	const ioport32_t syss;
+#define AMDM37x_UART_SYSS_RESETDONE_FLAG   (1 << 0)
+
+	/** Wake-up enable register */
+	ioport32_t wer;
+#define AMDM37x_UART_WER_CTS_ACTIVITY_FLAG  (1 << 0)
+#define AMDM37x_UART_WER_RI_ACTIVITY_FLAG  (1 << 2)
+#define AMDM37x_UART_WER_RX_ACTIVITY_FLAG  (1 << 4)
+#define AMDM37x_UART_WER_RHR_IRQ_FLAG  (1 << 5)
+#define AMDM37x_UART_WER_RLS_IRQ_FLAG  (1 << 6)
+#define AMDM37x_UART_WER_TX_WAKEUP_EN_FLAG  (1 << 7)
+
+	/** Carrier frequency prescaler */
+	ioport32_t cfps;	/* UART3 specific */
+#define AMDM37x_UART_CFPS_MASK   (0xff)
+
+	/** Number of bytes in RX fifo */
+	const ioport32_t rx_fifo_lvl;
+#define AMDM37x_UART_RX_FIFO_LVL_MASK   (0xff)
+
+	/** Number of bytes in TX fifo */
+	const ioport32_t tx_fifo_lvl;
+#define AMDM37x_UART_TX_FIFO_LVL_MASK   (0xff)
+
+	/** RX/TX empty interrupts */
+	ioport32_t ier2;
+#define AMDM37x_UART_IER2_RX_FIFO_EMPTY_IRQ_EN_FLAG  (1 << 0)
+#define AMDM37x_UART_IER2_TX_FIFO_EMPTY_IRQ_EN_FLAG  (1 << 1)
+
+	/** RX/TX empty status */
+	ioport32_t isr2;
+#define AMDM37x_UART_ISR2_RX_FIFO_EMPTY_FLAG  (1 << 0)
+#define AMDM37x_UART_ISR2_TX_FIFO_EMPTY_FLAG  (1 << 1)
+
+	uint32_t padd2_[3];
+
+	/** Mode definition register 3 */
+	ioport32_t mdr3;
+#define AMDM37x_UART_MDR3_DIS_CIR_RX_DEMOD_FLAG   (1 << 0)
+} amdm37x_uart_regs_t;
+
+#endif
+
+/**
+ * @}
+ */
Index: rnel/genarch/include/drivers/amdm37x_gpt/amdm37x_gpt.h
===================================================================
--- kernel/genarch/include/drivers/amdm37x_gpt/amdm37x_gpt.h	(revision df64dbcec09ca6420de2c8c0944a17482cc56d6b)
+++ 	(revision )
@@ -1,255 +1,0 @@
-/*
- * Copyright (c) 2012 Jan Vesely
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/** @addtogroup genarch
- * @{
- */
-/**
- * @file
- * @brief Texas Instruments AM/DM37x MPU general purpose timer driver.
- */
-
-#ifndef KERN_AMDM37x_GPT_H_
-#define KERN_AMDM37x_GPT_H_
-
-#include <typedefs.h>
-#include <mm/km.h>
-
-/* AMDM37x TRM p. 2740 */
-#define AMDM37x_GPT1_BASE_ADDRESS  0x48318000
-#define AMDM37x_GPT1_SIZE  4096
-#define AMDM37x_GPT1_IRQ  37
-#define AMDM37x_GPT2_BASE_ADDRESS  0x49032000
-#define AMDM37x_GPT2_SIZE  4096
-#define AMDM37x_GPT2_IRQ  38
-#define AMDM37x_GPT3_BASE_ADDRESS  0x49034000
-#define AMDM37x_GPT3_SIZE  4096
-#define AMDM37x_GPT3_IRQ  39
-#define AMDM37x_GPT4_BASE_ADDRESS  0x49036000
-#define AMDM37x_GPT4_SIZE  4096
-#define AMDM37x_GPT4_IRQ  40
-#define AMDM37x_GPT5_BASE_ADDRESS  0x49038000
-#define AMDM37x_GPT5_SIZE  4096
-#define AMDM37x_GPT5_IRQ  41
-#define AMDM37x_GPT6_BASE_ADDRESS  0x4903a000
-#define AMDM37x_GPT6_SIZE  4096
-#define AMDM37x_GPT6_IRQ  42
-#define AMDM37x_GPT7_BASE_ADDRESS  0x4903c000
-#define AMDM37x_GPT7_SIZE  4096
-#define AMDM37x_GPT7_IRQ  43
-#define AMDM37x_GPT8_BASE_ADDRESS  0x4903e000
-#define AMDM37x_GPT8_SIZE  4096
-#define AMDM37x_GPT8_IRQ  44
-#define AMDM37x_GPT9_BASE_ADDRESS  0x49040000
-#define AMDM37x_GPT9_SIZE  4096
-#define AMDM37x_GPT9_IRQ  45
-#define AMDM37x_GPT10_BASE_ADDRESS  0x48086000
-#define AMDM37x_GPT10_SIZE  4096
-#define AMDM37x_GPT10_IRQ  46
-#define AMDM37x_GPT11_BASE_ADDRESS  0x48088000
-#define AMDM37x_GPT11_SIZE  4096
-#define AMDM37x_GPT11_IRQ  47
-
-
-/** GPT register map AMDM37x TRM p. 2740 */
-typedef struct {
-	/** IP revision */
-	const ioport32_t tidr;
-#define AMDM37x_GPT_TIDR_MINOR_MASK  (0xf)
-#define AMDM37x_GPT_TIDR_MINOR_SHIFT  (0)
-#define AMDM37x_GPT_TIDR_MAJOR_MASK  (0xf)
-#define AMDM37x_GPT_TIDR_MAJOR_SHIFT  (4)
-	uint32_t padd0_[3];
-
-	/** L4 Interface parameters */
-	ioport32_t tiocp_cfg;
-#define AMDM37x_GPT_TIOCP_CFG_AUTOIDLE_FLAG  (1 << 0)
-#define AMDM37x_GPT_TIOCP_CFG_SOFTRESET_FLAG  (1 << 1)
-#define AMDM37x_GPT_TIOCP_CFG_ENWAKEUP_FLAG  (1 << 2)
-#define AMDM37x_GPT_TIOCP_CFG_IDLEMODE_MASK  (0x3)
-#define AMDM37x_GPT_TIOCP_CFG_IDLEMODE_SHIFT  (3)
-#define AMDM37x_GPT_TIOCP_CFG_EMUFREE_FlAG  (1 << 5)
-#define AMDM37x_GPT_TIOCP_CFG_CLOCKACTIVITY_MASK  (0x3)
-#define AMDM37x_GPT_TIOCP_CFG_CLOCKACTIVITY_SHIFT (8)
-
-	/** Module status information, excluding irq */
-	const ioport32_t tistat;
-#define AMDM37x_GPT_TISTAT_RESET_DONE_FLAG  (1 << 0)
-
-	/** Interrupt status register */
-	ioport32_t tisr;
-#define AMDM37x_GPT_TISR_MAT_IRQ_FLAG  (1 << 0)
-#define AMDM37x_GPT_TISR_OVF_IRQ_FLAG  (1 << 1)
-#define AMDM37x_GPT_TISR_TCAR_IRQ_FLAG  (1 << 2)
-
-	/* Interrupt enable register */
-	ioport32_t tier;
-#define AMDM37x_GPT_TIER_MAT_IRQ_FLAG  (1 << 0)
-#define AMDM37x_GPT_TIER_OVF_IRQ_FLAG  (1 << 1)
-#define AMDM37x_GPT_TIER_TCAR_IRQ_FLAG  (1 << 2)
-
-	/** Wakeup enable register */
-	ioport32_t twer;
-#define AMDM37x_GPT_TWER_MAT_IRQ_FLAG  (1 << 0)
-#define AMDM37x_GPT_TWER_OVF_IRQ_FLAG  (1 << 1)
-#define AMDM37x_GPT_TWER_TCAR_IRQ_FLAG  (1 << 2)
-
-	/** Optional features control register */
-	ioport32_t tclr;
-#define AMDM37x_GPT_TCLR_ST_FLAG  (1 << 0)
-#define AMDM37x_GPT_TCLR_AR_FLAG  (1 << 1)
-#define AMDM37x_GPT_TCLR_PTV_MASK  (0x7)
-#define AMDM37x_GPT_TCLR_PTV_SHIFT  (2)
-#define AMDM37x_GPT_TCLR_PRE_FLAG  (1 << 5)
-#define AMDM37x_GPT_TCLR_CE_FLAG  (1 << 6)
-#define AMDM37x_GPT_TCLR_SCPWM  (1 << 7)
-#define AMDM37x_GPT_TCLR_TCM_MASK  (0x3)
-#define AMDM37x_GPT_TCLR_TCM_SHIFT  (8)
-#define AMDM37x_GPT_TCLR_TRG_MASK  (0x3)
-#define AMDM37x_GPT_TCLR_TRG_SHIFT (10)
-#define AMDM37x_GPT_TCLR_PT_FLAG  (1 << 12)
-#define AMDM37x_GPT_TCLR_CAPT_MODE_FLAG  (1 << 13)
-#define AMDM37x_GPT_TCLR_GPO_CFG_FLAG  (1 << 14)
-
-	/** Value of timer counter */
-	ioport32_t tccr;
-
-	/** Timer load register */
-	ioport32_t tldr;
-
-	/** Timer trigger register */
-	ioport32_t ttgr;
-
-	/** Write-posted pending register */
-	const ioport32_t twps;
-#define AMDM37x_GPT_TWPS_TCLR_FLAG  (1 << 0)
-#define AMDM37x_GPT_TWPS_TCRR_FLAG  (1 << 1)
-#define AMDM37x_GPT_TWPS_TLDR_FLAG  (1 << 2)
-#define AMDM37x_GPT_TWPS_TTGR_FLAG  (1 << 3)
-#define AMDM37x_GPT_TWPS_TMAR_FLAG  (1 << 4)
-#define AMDM37x_GPT_TWPS_TPIR_FLAG  (1 << 5)
-#define AMDM37x_GPT_TWPS_TNIR_FLAG  (1 << 6)
-#define AMDM37x_GPT_TWPS_TCVR_FLAG  (1 << 7)
-#define AMDM37x_GPT_TWPS_TOCR_FLAG  (1 << 8)
-#define AMDM37x_GPT_TWPS_TOWR_FLAG  (1 << 9)
-
-	/** Timer match register */
-	ioport32_t tmar;
-
-	/** Capture value 1 register */
-	const ioport32_t tcar1;
-
-	/** Software interface control register */
-	ioport32_t tsicr;
-#define AMDM37x_GPT_TSICR_SFT_FLAG  (1 << 1)
-#define AMDM37x_GPT_TSICR_POSTED_FLAG  (1 << 2)
-
-	/** Capture value 2 register */
-	const ioport32_t tcar2;
-
-	/* GPT1,2,10 only (used for 1ms time period generation)*/
-
-	/** Positive increment register */
-	ioport32_t tpir;
-
-	/** Negative increment register */
-	ioport32_t tnir;
-
-	/** Counter value register */
-	ioport32_t tcvr;
-
-	/** Mask the tick interrupt for selected number of ticks */
-	ioport32_t tocr;
-
-	/** Number of masked overflow interrupts */
-	ioport32_t towr;
-} amdm37x_gpt_regs_t;
-
-typedef struct {
-	amdm37x_gpt_regs_t *regs;
-	bool special_available;
-} amdm37x_gpt_t;
-
-static inline void amdm37x_gpt_timer_ticks_init(
-    amdm37x_gpt_t* timer, uintptr_t ioregs, size_t iosize, unsigned hz)
-{
-	/* Set 32768 Hz clock as source */
-	// TODO find a nicer way to setup 32kHz clock source for timer1
-	// reg 0x48004C40 is CM_CLKSEL_WKUP see page 485 of the manual
-	ioport32_t *clksel = (void*) km_map(0x48004C40, 4, PAGE_NOT_CACHEABLE);
-	*clksel &= ~1;
-	km_unmap((uintptr_t)clksel, 4);
-
-	ASSERT(timer);
-	/* Map control register */
-	timer->regs = (void*) km_map(ioregs, iosize, PAGE_NOT_CACHEABLE);
-
-	/* Set autoreload */
-	timer->regs->tclr = AMDM37x_GPT_TCLR_AR_FLAG;
-
-	timer->special_available = (
-	    (ioregs == AMDM37x_GPT1_BASE_ADDRESS) ||
-	    (ioregs == AMDM37x_GPT2_BASE_ADDRESS) ||
-	    (ioregs == AMDM37x_GPT10_BASE_ADDRESS));
-	timer->regs->tldr = 0xffffffff - (32768 / hz) + 1;
-	timer->regs->tccr = 0xffffffff - (32768 / hz) + 1;
-	if (timer->special_available) {
-		/* Set values for according to formula (manual p. 2733) */
-		/* Use temporary variables for easier debugging */
-		const uint32_t tpir =
-		    ((32768 / hz + 1) * 1000000) - (32768000L * (1000 / hz));
-		const uint32_t tnir =
-		    ((32768 / hz) * 1000000) - (32768000 * (1000 / hz));
-		timer->regs->tpir = tpir;
-		timer->regs->tnir = tnir;
-	}
-
-}
-
-static inline void amdm37x_gpt_timer_ticks_start(amdm37x_gpt_t* timer)
-{
-	ASSERT(timer);
-	ASSERT(timer->regs);
-	/* Enable overflow interrupt */
-	timer->regs->tier |= AMDM37x_GPT_TIER_OVF_IRQ_FLAG;
-	/* Start timer */
-	timer->regs->tclr |= AMDM37x_GPT_TCLR_ST_FLAG;
-}
-
-static inline void amdm37x_gpt_irq_ack(amdm37x_gpt_t* timer)
-{
-	ASSERT(timer);
-	ASSERT(timer->regs);
-	/* Clear all pending interrupts */
-	timer->regs->tisr = timer->regs->tisr;
-}
-
-#endif
-
-/**
- * @}
- */
Index: rnel/genarch/include/drivers/amdm37x_irc/amdm37x_irc.h
===================================================================
--- kernel/genarch/include/drivers/amdm37x_irc/amdm37x_irc.h	(revision df64dbcec09ca6420de2c8c0944a17482cc56d6b)
+++ 	(revision )
@@ -1,206 +1,0 @@
-/*
- * Copyright (c) 2012 Jan Vesely
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/** @addtogroup genarch
- * @{
- */
-/**
- * @file
- * @brief Texas Instruments AM/DM37x MPU on-chip interrupt controller driver.
- */
-
-#ifndef KERN_AMDM37x_IRQC_H_
-#define KERN_AMDM37x_IRQC_H_
-
-/* AMDM37x TRM p. 1079 */
-#define AMDM37x_IRC_BASE_ADDRESS 0x48200000
-#define AMDM37x_IRC_SIZE 4096
-
-#define AMDM37x_IRC_IRQ_COUNT 96
-
-#include <typedefs.h>
-
-typedef struct {
-	const ioport32_t revision; /**< Revision */
-#define AMDM37x_IRC_REV_MASK (0xff)
-
-	uint8_t padd0_[12];
-
-	ioport32_t sysconfig; /**< SYS config */
-#define AMDM37x_IRC_SYSCONFIG_AUTOIDLE_FLAG (1 << 0)
-#define AMDM37x_IRC_SYSCONFIG_SOFTRESET_FLAG (1 << 1)
-
-	const ioport32_t sysstatus; /**< SYS status */
-#define AMDM37x_IRC_SYSSTATUS_RESET_DONE_FLAG (1 << 0)
-
-	uint8_t padd1_[40];
-
-	const ioport32_t sir_irq;   /**< Currently active irq number */
-#define AMDM37x_IRC_SIR_IRQ_ACTIVEIRQ_MASK (0x7f)
-#define AMDM37x_IRC_SIR_IRQ_SPURIOUSIRQFLAG_MASK (0xfffffff8)
-
-	const ioport32_t sir_fiq;
-#define AMDM37x_IRC_SIR_FIQ_ACTIVEIRQ_MASK (0x7f)
-#define AMDM37x_IRC_SIR_FIQ_SPURIOUSIRQFLAG_MASK (0xfffffff8)
-
-	ioport32_t control;   /**< New interrupt agreement. */
-#define AMDM37x_IRC_CONTROL_NEWIRQAGR_FLAG (1 << 0)
-#define AMDM37x_IRC_CONTROL_NEWFIQAGR_FLAG (1 << 1)
-
-	ioport32_t protection;  /**< Protect other registers. */
-#define AMDM37x_IRC_PROTECTION_PROETCTION_FLAG (1 << 0)
-
-	ioport32_t idle;   /**< Idle and autogating */
-#define AMDM37x_IRC_IDLE_FUNCIDLE_FLAG (1 << 0)
-#define AMDM37x_IRC_IDLE_TURBO_FLAG (1 << 1)
-
-	uint8_t padd2_[12];
-
-	ioport32_t irq_priority; /**< Active IRQ priority */
-#define AMDM37x_IRC_IRQ_PRIORITY_IRQPRIORITY_MASK (0x7f)
-#define AMDM37x_IRC_IRQ_PRIORITY_SPURIOUSIRQFLAG_MASK (0xfffffff8)
-
-	ioport32_t fiq_priority; /**< Active FIQ priority */
-#define AMDM37x_IRC_FIQ_PRIORITY_FIQPRIORITY_MASK (0x7f)
-#define AMDM37x_IRC_FIQ_PRIORITY_SPURIOUSFIQFLAG_MASK (0xfffffff8)
-
-	ioport32_t threshold; /**< Priority threshold */
-#define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_MASK (0xff)
-#define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_ENABLED (0x00)
-#define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_DISABLED (0xff)
-
-	uint8_t padd3__[20];
-
-	struct {
-		const ioport32_t itr;   /**< Interrupt input status before masking */
-		ioport32_t mir;   /**< Interrupt mask */
-		ioport32_t mir_clear; /**< Clear mir mask bits */
-		ioport32_t mir_set;   /**< Set mir mask bits */
-		ioport32_t isr_set;   /**< Set software interrupt bits */
-		ioport32_t isr_clear; /**< Clear software interrupt bits */
-		const ioport32_t pending_irq; /**< IRQ status after masking */
-		const ioport32_t pending_fiq; /**< FIQ status after masking */
-	} interrupts[3];
-
-	uint8_t padd4_[32];
-
-	ioport32_t ilr[96];   /**< FIQ/IRQ steering */
-#define AMDM37x_IRC_ILR_FIQNIRQ (1 << 0)
-#define AMDM37x_IRC_ILR_PRIORITY_MASK (0x3f)
-#define AMDM37x_IRC_ILR_PRIORITY_SHIFT (2)
-
-} amdm37x_irc_regs_t;
-
-static inline void amdm37x_irc_dump(amdm37x_irc_regs_t *regs)
-{
-#define DUMP_REG(name) \
-	printf("%s %p(%x).\n", #name, &regs->name, regs->name);
-
-	DUMP_REG(revision);
-	DUMP_REG(sysconfig);
-	DUMP_REG(sysstatus);
-	DUMP_REG(sir_irq);
-	DUMP_REG(sir_fiq);
-	DUMP_REG(control);
-	DUMP_REG(protection);
-	DUMP_REG(idle);
-	DUMP_REG(irq_priority);
-	DUMP_REG(fiq_priority);
-	DUMP_REG(threshold);
-
-	for (int i = 0; i < 3; ++i) {
-		DUMP_REG(interrupts[i].itr);
-		DUMP_REG(interrupts[i].mir);
-		DUMP_REG(interrupts[i].isr_set);
-		DUMP_REG(interrupts[i].pending_irq);
-		DUMP_REG(interrupts[i].pending_fiq);
-	}
-	for (int i = 0; i < AMDM37x_IRC_IRQ_COUNT; ++i) {
-		DUMP_REG(ilr[i]);
-	}
-
-#undef DUMP_REG
-}
-
-static inline void amdm37x_irc_init(amdm37x_irc_regs_t *regs)
-{
-	/* AMDM37x TRM sec 12.5.1 p. 2425 */
-	/* Program system config register */
-	//TODO enable this when you know the meaning
-	//regs->sysconfig |= AMDM37x_IRC_SYSCONFIG_AUTOIDLE_FLAG;
-
-	/* Program idle register */
-	//TODO enable this when you know the meaning
-	//regs->sysconfig |= AMDM37x_IRC_IDLE_TURBO_FLAG;
-
-	/* Program ilr[m] assign priority, decide fiq */
-	for (unsigned i = 0; i < AMDM37x_IRC_IRQ_COUNT; ++i) {
-		regs->ilr[i] = 0; /* highest prio(default) route to irq */
-	}
-
-	/* Disable all interrupts */
-	regs->interrupts[0].mir_set = 0xffffffff;
-	regs->interrupts[1].mir_set = 0xffffffff;
-	regs->interrupts[2].mir_set = 0xffffffff;
-}
-
-static inline unsigned amdm37x_irc_inum_get(amdm37x_irc_regs_t *regs)
-{
-	return regs->sir_irq & AMDM37x_IRC_SIR_IRQ_ACTIVEIRQ_MASK;
-}
-
-static inline void amdm37x_irc_irq_ack(amdm37x_irc_regs_t *regs)
-{
-	regs->control = AMDM37x_IRC_CONTROL_NEWIRQAGR_FLAG;
-}
-
-static inline void amdm37x_irc_fiq_ack(amdm37x_irc_regs_t *regs)
-{
-	regs->control = AMDM37x_IRC_CONTROL_NEWFIQAGR_FLAG;
-}
-
-static inline void amdm37x_irc_enable(amdm37x_irc_regs_t *regs, unsigned inum)
-{
-	ASSERT(inum < AMDM37x_IRC_IRQ_COUNT);
-	const unsigned set = inum / 32;
-	const unsigned pos = inum % 32;
-	regs->interrupts[set].mir_clear = (1 << pos);
-}
-
-static inline void amdm37x_irc_disable(amdm37x_irc_regs_t *regs, unsigned inum)
-{
-	ASSERT(inum < AMDM37x_IRC_IRQ_COUNT);
-	const unsigned set = inum / 32;
-	const unsigned pos = inum % 32;
-	regs->interrupts[set].mir_set = (1 << pos);
-}
-
-#endif
-
-/**
- * @}
- */
Index: rnel/genarch/include/drivers/amdm37x_uart/amdm37x_uart.h
===================================================================
--- kernel/genarch/include/drivers/amdm37x_uart/amdm37x_uart.h	(revision df64dbcec09ca6420de2c8c0944a17482cc56d6b)
+++ 	(revision )
@@ -1,459 +1,0 @@
-/*
- * Copyright (c) 2012 Jan Vesely
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/** @addtogroup genarch
- * @{
- */
-/**
- * @file
- * @brief Texas Instruments AMDM37x on-chip interrupt controller driver.
- */
-
-#ifndef KERN_AMDM37x_UART_H_
-#define KERN_AMDM37x_UART_H_
-
-#include <typedefs.h>
-#include <console/chardev.h>
-#include <ddi/irq.h>
-
-/* AMDM37x TRM p. 2950 */
-#define AMDM37x_UART1_BASE_ADDRESS   0x4806a000
-#define AMDM37x_UART1_SIZE   1024
-#define AMDM37x_UART1_IRQ   72 /* AMDM37x TRM p. 2418 */
-
-#define AMDM37x_UART2_BASE_ADDRESS   0x4806b000
-#define AMDM37x_UART2_SIZE   1024
-#define AMDM37x_UART2_IRQ   73 /* AMDM37x TRM p. 2418 */
-
-#define AMDM37x_UART3_BASE_ADDRESS   0x49020000
-#define AMDM37x_UART3_SIZE   1024
-#define AMDM37x_UART3_IRQ   74 /* AMDM37x TRM p. 2418 */
-
-#define AMDM37x_UART4_BASE_ADDRESS   0x49042000
-#define AMDM37x_UART4_SIZE   1024
-#define AMDM37x_UART4_IRQ   80 /* AMDM37x TRM p. 2418 */
-
-typedef struct {
-	union {
-		/** Stores lower part of the 14-bit baud divisor */
-		ioport32_t dll;
-#define AMDM37x_UART_DLL_MASK   (0xff)
-
-		/** Receive holding register */
-		const ioport32_t rhr;
-#define AMDM37x_UART_RHR_MASK   (0xff)
-
-		/** Transmit holding register */
-		ioport32_t thr;
-#define AMDM37x_UART_THR_MASK   (0xff)
-	};
-
-	union {
-		/** Stores higher part of the 14-bit baud divisor */
-		ioport32_t dlh;
-#define AMDM37x_UART_DLH_MASK   (0x1f)
-
-		/** Interrupt enable registers */
-		ioport32_t ier;
-#define AMDM37x_UART_IER_RHR_IRQ_FLAG   (1 << 0)
-#define AMDM37x_UART_IER_THR_IRQ_FLAG   (1 << 1)
-#define AMDM37x_UART_IER_LINE_STS_IRQ_FLAG   (1 << 2)
-#define AMDM37x_UART_IER_MODEM_STS_IRQ_FLAG   (1 << 3)
-#define AMDM37x_UART_IER_SLEEP_MODE_FLAG   (1 << 4)
-#define AMDM37x_UART_IER_XOFF_IRQ_FLAG   (1 << 5)
-#define AMDM37x_UART_IER_RTS_IRQ_FLAG   (1 << 6)
-#define AMDM37x_UART_IER_CTS_IRQ_FLAG   (1 << 7)
-
-#define AMDM37x_CIR_IER_RHR_IRQ_FLAG   (1 << 0)
-#define AMDM37x_CIR_IER_THR_IRQ_FLAG   (1 << 1)
-#define AMDM37x_CIR_IER_RX_STOP_IRQ_FLAG   (1 << 2)
-#define AMDM37x_CIR_IER_RX_OVERRUN_IRQ_FLAG   (1 << 3)
-#define AMDM37x_CIR_IER_TX_STS_IRQ_FLAG   (1 << 5)
-
-#define AMDM37x_IRDA_IER_RHR_IRQ_FLAG   (1 << 0)
-#define AMDM37x_IRDA_IER_THR_IRQ_FLAG   (1 << 1)
-#define AMDM37x_IRDA_IER_LAST_RX_BYTE_IRQ_FLAG   (1 << 2)
-#define AMDM37x_IRDA_IER_RX_OVERRUN_IRQ_FLAG   (1 << 3)
-#define AMDM37x_IRDA_IER_STS_FIFO_TRIG_IRQ_FLAG   (1 << 4)
-#define AMDM37x_IRDA_IER_TX_STS_IRQ_FLAG   (1 << 5)
-#define AMDM37x_IRDA_IER_LINE_STS_IRQ_FLAG   (1 << 6)
-#define AMDM37x_IRDA_IER_EOF_IRQ_FLAG   (1 << 7)
-	};
-
-	union {
-		/** Interrupt identification register */
-		const ioport32_t iir;
-#define AMDM37x_UART_IIR_IRQ_PENDING_FLAG   (1 << 0)
-#define AMDM37x_UART_IIR_TYPE_MASK   (0x1f)
-#define AMDM37x_UART_IIR_TYPE_SHIFT   (1)
-#define AMDM37x_UART_IIR_FCR_MASK   (0x3)
-#define AMDM37x_UART_IIR_FCR_SHIFT   (6)
-
-#define AMDM37x_CIR_IIR_RHR_IRQ_FLAG   (1 << 0)
-#define AMDM37x_CIR_IIR_THR_IRQ_FLAG   (1 << 1)
-#define AMDM37x_CIR_IIR_RX_STOP_IRQ_FLAG   (1 << 2)
-#define AMDM37x_CIR_IIR_RX_OE_IRQ_FLAG   (1 << 3)
-#define AMDM37x_CIR_IIR_TX_STS_IRQ_FLAG   (1 << 5)
-
-#define AMDM37x_IRDA_IIR_RHR_IRQ_FLAG   (1 << 0)
-#define AMDM37x_IRDA_IIR_THR_IRQ_FLAG   (1 << 1)
-#define AMDM37x_IRDA_IIR_RX_FIFO_LB_IRQ_FLAG   (1 << 2)
-#define AMDM37x_IRDA_IIR_RX_OE_IRQ_FLAG   (1 << 3)
-#define AMDM37x_IRDA_IIR_STS_FIFO_IRQ_FLAG   (1 << 4)
-#define AMDM37x_IRDA_IIR_TX_STS_IRQ_FLAG   (1 << 5)
-#define AMDM37x_IRDA_IIR_LINE_STS_IRQ_FLAG   (1 << 6)
-#define AMDM37x_IRDA_IIR_EOF_IRQ_FLAG   (1 << 7)
-
-		/** FIFO control register */
-		ioport32_t fcr;
-#define AMDM37x_UART_FCR_FIFO_EN_FLAG   (1 << 0)
-#define AMDM37x_UART_FCR_RX_FIFO_CLR_FLAG   (1 << 1)
-#define AMDM37x_UART_FCR_TX_FIFO_CLR_FLAG   (1 << 3)
-#define AMDM37x_UART_FCR_DMA_MODE_FLAG   (1 << 4)
-
-#define AMDM37x_UART_FCR_TX_FIFO_TRIG_MASK   (0x3)
-#define AMDM37x_UART_FCR_TX_FIFO_TRIG_SHIFT   (4)
-
-#define AMDM37x_UART_FCR_RX_FIFO_TRIG_MASK   (0x3)
-#define AMDM37x_UART_FCR_RX_FIFO_TRIG_SHIFT   (6)
-
-		/** Enhanced feature register */
-		ioport32_t efr;
-#define AMDM37x_UART_EFR_SW_FLOW_CTRL_RX_MASK   (0x3)
-#define AMDM37x_UART_EFR_SW_FLOW_CTRL_RX_SHIFT   (0)
-#define AMDM37x_UART_EFR_SW_FLOW_CTRL_TX_MASK   (0x3)
-#define AMDM37x_UART_EFR_SW_FLOW_CTRL_TX_SHIFT   (2)
-
-#define AMDM37x_UART_EFR_SW_FLOW_CTRL_NONE   (0x0)
-#define AMDM37x_UART_EFR_SW_FLOW_CTRL_X2   (0x1)
-#define AMDM37x_UART_EFR_SW_FLOW_CTRL_X1   (0x2)
-#define AMDM37x_UART_EFR_SW_FLOW_CTRL_XBOTH   (0x3)
-
-#define AMDM37x_UART_EFR_ENH_FLAG   (1 << 4)
-#define AMDM37x_UART_EFR_SPEC_CHAR_FLAG   (1 << 5)
-#define AMDM37x_UART_EFR_AUTO_RTS_EN_FLAG   (1 << 6)
-#define AMDM37x_UART_EFR_AUTO_CTS_EN_FLAG   (1 << 7)
-	};
-
-	/** Line control register */
-	ioport32_t lcr;
-#define AMDM37x_UART_LCR_CHAR_LENGTH_MASK   (0x3)
-#define AMDM37x_UART_LCR_CHAR_LENGTH_SHIFT   (0)
-#define AMDM37x_UART_LCR_CHAR_LENGTH_5BITS   (0x0)
-#define AMDM37x_UART_LCR_CHAR_LENGTH_6BITS   (0x1)
-#define AMDM37x_UART_LCR_CHAR_LENGTH_7BITS   (0x2)
-#define AMDM37x_UART_LCR_CHAR_LENGTH_8BITS   (0x3)
-#define AMDM37x_UART_LCR_NB_STOP_FLAG   (1 << 2)
-#define AMDM37x_UART_LCR_PARITY_EN_FLAG   (1 << 3)
-#define AMDM37x_UART_LCR_PARITY_TYPE1_FLAG   (1 << 4)
-#define AMDM37x_UART_LCR_PARITY_TYPE2_FLAG   (1 << 5)
-#define AMDM37x_UART_LCR_BREAK_EN_FLAG   (1 << 6)
-#define AMDM37x_UART_LCR_DIV_EN_FLAG   (1 << 7)
-
-
-	union {
-		/** Modem control register */
-		ioport32_t mcr;
-#define AMDM37x_UART_MCR_DTR_FLAG   (1 << 0)
-#define AMDM37x_UART_MCR_RTS_FLAG   (1 << 1)
-#define AMDM37x_UART_MCR_RI_STS_CH_FLAG   (1 << 2)
-#define AMDM37x_UART_MCR_CD_STS_CH_FLAG   (1 << 3)
-#define AMDM37x_UART_MCR_LOOPBACK_EN_FLAG   (1 << 4)
-#define AMDM37x_UART_MCR_XON_EN_FLAG   (1 << 5)
-#define AMDM37x_UART_MCR_TCR_TLR_FLAG   (1 << 6)
-
-		/** UART: XON1 char, IRDA: ADDR1 address */
-		ioport32_t xon1_addr1;
-#define AMDM37x_UART_XON1_ADDR1_MASK   (0xff)
-	};
-
-	union {
-		/** Line status register */
-		const ioport32_t lsr;
-#define AMDM37x_UART_LSR_RX_FIFO_E_FLAG   (1 << 0)
-#define AMDM37x_UART_LSR_RX_OE_FLAG   (1 << 1)
-#define AMDM37x_UART_LSR_RX_PE_FLAG   (1 << 2)
-#define AMDM37x_UART_LSR_RX_FE_FLAG   (1 << 3)
-#define AMDM37x_UART_LSR_RX_BI_FLAG   (1 << 4)
-#define AMDM37x_UART_LSR_TX_FIFO_E_FLAG   (1 << 5)
-#define AMDM37x_UART_LSR_TX_SR_E_FLAG   (1 << 6)
-#define AMDM37x_UART_LSR_RX_FIFO_STS_FLAG   (1 << 7)
-
-#define AMDM37x_CIR_LSR_RX_FIFO_E_FLAG   (1 << 0)
-#define AMDM37x_CIR_LSR_RX_STOP_FLAG   (1 << 5)
-#define AMDM37x_CIR_LSR_THR_EMPTY_FLAG   (1 << 7)
-
-#define AMDM37x_IRDA_LSR_RX_FIFO_E_FLAG   (1 << 0)
-#define AMDM37x_IRDA_LSR_STS_FIFO_E_FLAG   (1 << 1)
-#define AMDM37x_IRDA_LSR_CRC_FLAG   (1 << 2)
-#define AMDM37x_IRDA_LSR_ABORT_FLAG   (1 << 3)
-#define AMDM37x_IRDA_LSR_FTL_FLAG   (1 << 4)
-#define AMDM37x_IRDA_LSR_RX_LAST_FLAG   (1 << 5)
-#define AMDM37x_IRDA_LSR_STS_FIFO_FULL_FLAG   (1 << 6)
-#define AMDM37x_IRDA_LSR_THR_EMPTY_FLAG   (1 << 7)
-
-		/** UART: XON2 char, IRDA: ADDR2 address */
-		ioport32_t xon2_addr2;
-	};
-
-	union {
-		/** Modem status register */
-		const ioport32_t msr;
-#define AMDM37x_UART_MSR_CTS_STS_FLAG   (1 << 0)
-#define AMDM37x_UART_MSR_DSR_STS_FLAG   (1 << 1)
-#define AMDM37x_UART_MSR_RI_STS_FLAG   (1 << 2)
-#define AMDM37x_UART_MSR_DCD_STS_FLAG   (1 << 3)
-#define AMDM37x_UART_MSR_NCTS_STS_FLAG   (1 << 4)
-#define AMDM37x_UART_MSR_NDSR_STS_FLAG   (1 << 5)
-#define AMDM37x_UART_MSR_NRI_STS_FLAG   (1 << 6)
-#define AMDM37x_UART_MSR_NCD_STS_FLAG   (1 << 7)
-
-		/** Transmission control register */
-		ioport32_t tcr;
-#define AMDM37x_UART_TCR_FIFO_TRIG_MASK   (0xf)
-#define AMDM37x_UART_TCR_FIFO_TRIG_HALT_SHIFT   (0)
-#define AMDM37x_UART_TCR_FIFO_TRIG_START_SHIFT   (4)
-
-		/** UART: XOFF1 char */
-		ioport32_t xoff1;
-#define AMDM37x_UART_XOFF1_MASK   (0xff)
-	};
-
-	union {
-		/* Scratchpad register, does nothing */
-		ioport32_t spr;
-#define AMDM37x_UART_SPR_MASK   (0xff)
-
-		/* Trigger level register */
-		ioport32_t tlr;
-#define AMDM37x_UART_TLR_LEVEL_MASK   (0xf)
-#define AMDM37x_UART_TLR_TX_FIFO_TRIG_SHIFT   (0)
-#define AMDM37x_UART_TLR_RX_FIFO_TRIG_SHIFT   (4)
-
-		/** UART: XOFF2 char */
-		ioport32_t xoff2;
-#define AMDM37x_UART_XOFF2_MASK   (0xff)
-	};
-
-	/** Mode definition register. */
-	ioport32_t mdr1;
-#define AMDM37x_UART_MDR_MS_MASK   (0x7)
-#define AMDM37x_UART_MDR_MS_SHIFT   (0)
-#define AMDM37x_UART_MDR_MS_UART16   (0x0)
-#define AMDM37x_UART_MDR_MS_SIR   (0x1)
-#define AMDM37x_UART_MDR_MS_UART16_AUTO   (0x2)
-#define AMDM37x_UART_MDR_MS_UART13   (0x3)
-#define AMDM37x_UART_MDR_MS_MIR   (0x4)
-#define AMDM37x_UART_MDR_MS_FIR   (0x5)
-#define AMDM37x_UART_MDR_MS_CIR   (0x6)
-#define AMDM37x_UART_MDR_MS_DISABLE   (0x7)
-
-#define AMDM37x_UART_MDR_IR_SLEEP_FLAG   (1 << 3)
-#define AMDM37x_UART_MDR_SET_TXIR_FLAG   (1 << 4)
-#define AMDM37x_UART_MDR_SCT_FLAG   (1 << 5)
-#define AMDM37x_UART_MDR_SIP_FLAG   (1 << 6)
-#define AMDM37x_UART_MDR_FRAME_END_MODE_FLAG   (1 << 7)
-
-	/** Mode definition register */
-	ioport32_t mdr2;
-#define AMDM37x_UART_MDR_IRTX_UNDERRUN_FLAG   (1 << 0)
-#define AMDM37x_UART_MDR_STS_FIFO_TRIG_MASK   (0x3)
-#define AMDM37x_UART_MDR_STS_FIFO_TRIG_SHIFT   (1)
-#define AMDM37x_UART_MDR_PULSE_SHAPING_FLAG   (1 << 3)
-#define AMDM37x_UART_MDR_CIR_PULSE_MODE_MASK   (0x3)
-#define AMDM37x_UART_MDR_CIR_PULSE_MODE_SHIFT   (4)
-#define AMDM37x_UART_MDR_IRRXINVERT_FLAG   (1 << 6)
-
-
-	/* UART3 specific */
-	union {
-		/** Status FIFO line status register (IrDA only) */
-		const ioport32_t sflsr;
-#define AMDM37x_IRDA_SFLSR_CRC_ERROR_FLAG   (1 << 1)
-#define AMDM37x_IRDA_SFLSR_ABORT_FLAG   (1 << 2)
-#define AMDM37x_IRDA_SFLSR_FTL_FLAG   (1 << 3)
-#define AMDM37x_IRDA_SFLSR_OE_FLAG   (1 << 4)
-
-		/** Transmit frame length low (IrDA only) */
-		ioport32_t txfll;
-#define AMDM37x_UART_TXFLL_MASK   (0xff)
-	};
-
-	/* UART3 specific */
-	union {
-		/** Dummy register to restart TX or RX (IrDA only) */
-		const ioport32_t resume;
-		/** Transmit frame length high (IrDA only) */
-		ioport32_t txflh;
-#define AMDM37x_UART_TXFLH_MASK   (0xff)
-	};
-
-	/* UART3 specific */
-	union {
-		/** Status FIFO register low (IrDA only) */
-		const ioport32_t sfregl;
-#define AMDM37x_UART_SFREGL_MASK   (0xff)
-		/** Received frame length low (IrDA only) */
-		ioport32_t rxfll;
-#define AMDM37x_UART_RXFLL_MASK   (0xff)
-	};
-
-	/* UART3 specific */
-	union {
-		/** Status FIFO register high (IrDA only) */
-		const ioport32_t sfregh;
-#define AMDM37x_UART_SFREGH_MASK   (0xf)
-		/** Received frame length high (IrDA only) */
-		ioport32_t rxflh;
-#define AMDM37x_UART_RXFLH_MASK   (0xf)
-	};
-
-	union {
-		/** UART autobauding status register */
-		const ioport32_t uasr;
-#define AMDM37x_UART_UASR_SPEED_MASK   (0x1f)
-#define AMDM37x_UART_UASR_SPEED_SHIFT   (0)
-#define AMDM37x_UART_UASR_8BIT_CHAR_FLAG   (1 << 5)
-#define AMDM37x_UART_UASR_PARITY_MASK   (0x3)
-#define AMDM37x_UART_UASR_PARITY_SHIFT   (6)
-
-		/** BOF control register (IrDA only) */
-		ioport32_t blr; /* UART3 sepcific */
-#define AMDM37x_IRDA_BLR_XBOF_TYPE_FLAG   (1 << 6)
-#define AMDM37x_IRDA_BLR_STS_FIFO_RESET   (1 << 7)
-	};
-
-	/** Auxiliary control register (IrDA only) */
-	ioport32_t acreg; /* UART3 specific */
-#define AMDM37x_IRDA_ACREG_EOT_EN_FLAG   (1 << 0)
-#define AMDM37x_IRDA_ACREG_ABORT_EN_FLAG   (1 << 1)
-#define AMDM37x_IRDA_ACREG_SCTX_EN_FLAG   (1 << 2)
-#define AMDM37x_IRDA_ACREG_SEND_SIP_FLAG   (1 << 3)
-#define AMDM37x_IRDA_ACREG_DIS_TX_UNDERRUN_FLAG   (1 << 4)
-#define AMDM37x_IRDA_ACREG_DIS_IR_RX_FLAG   (1 << 5)
-#define AMDM37x_IRDA_ACREG_SD_MOD_FLAG   (1 << 6)
-#define AMDM37x_IRDA_ACREG_PULSE_TYPE_FLAG   (1 << 7)
-
-	/** Supplementary control register */
-	ioport32_t scr;
-#define AMDM37x_UART_SCR_DMA_MODE_CTL_FLAG   (1 << 0)
-#define AMDM37x_UART_SCR_DMA_MODE_MASK   (0x3)
-#define AMDM37x_UART_SCR_DMA_MODE_SHIFT   (1)
-#define AMDM37x_UART_SCR_TX_EMPTY_CTL_IRQ_FLAG   (1 << 3)
-#define AMDM37x_UART_SCR_RX_CTS_WU_EN_FLAG   (1 << 4)
-#define AMDM37x_UART_SCR_TX_TRIG_GRANU1_FLAG   (1 << 6)
-#define AMDM37x_UART_SCR_RX_TRIG_GRANU1_FLAG   (1 << 7)
-
-	/** Supplementary status register */
-	const ioport32_t ssr;
-#define AMDM37x_UART_SSR_TX_FIFO_FULL_FLAG   (1 << 0)
-#define AMDM37x_UART_SSR_RX_CTS_WU_STS_FLAG   (1 << 1)
-#define AMDM37x_UART_SSR_DMA_COUNTER_RESET_FLAG   (1 << 2)
-
-	/** BOF Length register (IrDA only)*/
-	ioport32_t eblr; /* UART3 specific */
-#define AMDM37x_IRDA_EBLR_DISABLED   (0x00)
-#define AMDM37x_IRDA_EBLR_RX_STOP_BITS(bits)   (bits & 0xff)
-
-	uint32_t padd0_;
-
-	/** Module version register */
-	const ioport32_t mvr;
-#define AMDM37x_UART_MVR_MINOR_MASK   (0xf)
-#define AMDM37x_UART_MVR_MINOR_SHIFT   (0)
-#define AMDM37x_UART_MVR_MAJOR_MASK   (0xf)
-#define AMDM37x_UART_MVR_MAJOR_SHIFT   (4)
-
-	/** System configuration register */
-	ioport32_t sysc;
-#define AMDM37x_UART_SYSC_AUTOIDLE_FLAG   (1 << 0)
-#define AMDM37x_UART_SYSC_SOFTRESET_FLAG   (1 << 1)
-#define AMDM37x_UART_SYSC_ENWAKEUP_FLAG   (1 << 2)
-#define AMDM37x_UART_SYSC_IDLE_MODE_MASK   (0x3)
-#define AMDM37x_UART_SYSC_IDLE_MODE_SHIFT   (3)
-#define AMDM37x_UART_SYSC_IDLE_MODE_FORCE   (0x0)
-#define AMDM37x_UART_SYSC_IDLE_MODE_NO   (0x1)
-#define AMDM37x_UART_SYSC_IDLE_MODE_SMART   (0x2)
-
-	/** System status register */
-	const ioport32_t syss;
-#define AMDM37x_UART_SYSS_RESETDONE_FLAG   (1 << 0)
-
-	/** Wake-up enable register */
-	ioport32_t wer;
-#define AMDM37x_UART_WER_CTS_ACTIVITY_FLAG  (1 << 0)
-#define AMDM37x_UART_WER_RI_ACTIVITY_FLAG  (1 << 2)
-#define AMDM37x_UART_WER_RX_ACTIVITY_FLAG  (1 << 4)
-#define AMDM37x_UART_WER_RHR_IRQ_FLAG  (1 << 5)
-#define AMDM37x_UART_WER_RLS_IRQ_FLAG  (1 << 6)
-#define AMDM37x_UART_WER_TX_WAKEUP_EN_FLAG  (1 << 7)
-
-	/** Carrier frequency prescaler */
-	ioport32_t cfps;	/* UART3 specific */
-#define AMDM37x_UART_CFPS_MASK   (0xff)
-
-	/** Number of bytes in RX fifo */
-	const ioport32_t rx_fifo_lvl;
-#define AMDM37x_UART_RX_FIFO_LVL_MASK   (0xff)
-
-	/** Number of bytes in TX fifo */
-	const ioport32_t tx_fifo_lvl;
-#define AMDM37x_UART_TX_FIFO_LVL_MASK   (0xff)
-
-	/** RX/TX empty interrupts */
-	ioport32_t ier2;
-#define AMDM37x_UART_IER2_RX_FIFO_EMPTY_IRQ_EN_FLAG  (1 << 0)
-#define AMDM37x_UART_IER2_TX_FIFO_EMPTY_IRQ_EN_FLAG  (1 << 1)
-
-	/** RX/TX empty status */
-	ioport32_t isr2;
-#define AMDM37x_UART_ISR2_RX_FIFO_EMPTY_FLAG  (1 << 0)
-#define AMDM37x_UART_ISR2_TX_FIFO_EMPTY_FLAG  (1 << 1)
-
-	uint32_t padd2_[3];
-
-	/** Mode definition register 3 */
-	ioport32_t mdr3;
-#define AMDM37x_UART_MDR3_DIS_CIR_RX_DEMOD_FLAG   (1 << 0)
-} amdm37x_uart_regs_t;
-
-typedef struct {
-	amdm37x_uart_regs_t *regs;
-	indev_t *indev;
-	outdev_t outdev;
-	irq_t irq;
-} amdm37x_uart_t;
-
-
-bool amdm37x_uart_init(amdm37x_uart_t *, inr_t, uintptr_t, size_t);
-void amdm37x_uart_input_wire(amdm37x_uart_t *, indev_t *);
-
-#endif
-
-/**
- * @}
- */
Index: kernel/genarch/src/drivers/am335x/timer.c
===================================================================
--- kernel/genarch/src/drivers/am335x/timer.c	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
+++ kernel/genarch/src/drivers/am335x/timer.c	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2012 Maurizio Lombardi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM335x timer driver.
+ */
+
+#include <genarch/drivers/am335x/timer.h>
+#include <mm/km.h>
+#include <errno.h>
+
+typedef enum {
+	REG_TCLR = 0x00,
+	REG_TCRR = 0x01,
+	REG_TLDR = 0x02,
+	REG_TTGR = 0x04
+} timer_reg_t;
+
+typedef struct timer_regs_mmap {
+        uintptr_t base;
+        size_t size;
+} timer_regs_mmap_t;
+
+static const timer_regs_mmap_t regs_map[TIMERS_MAX] = {
+	{ .base = AM335x_DMTIMER0_BASE_ADDRESS, .size = AM335x_DMTIMER0_SIZE },
+	{0, 0}, /* DMTIMER1 is not supported by this driver */
+	{ .base = AM335x_DMTIMER2_BASE_ADDRESS, .size = AM335x_DMTIMER2_SIZE },
+	{ .base = AM335x_DMTIMER3_BASE_ADDRESS, .size = AM335x_DMTIMER3_SIZE },
+	{ .base = AM335x_DMTIMER4_BASE_ADDRESS, .size = AM335x_DMTIMER4_SIZE },
+	{ .base = AM335x_DMTIMER5_BASE_ADDRESS, .size = AM335x_DMTIMER5_SIZE },
+	{ .base = AM335x_DMTIMER6_BASE_ADDRESS, .size = AM335x_DMTIMER6_SIZE },
+	{ .base = AM335x_DMTIMER7_BASE_ADDRESS, .size = AM335x_DMTIMER7_SIZE },
+};
+
+static void
+write_register_posted(am335x_timer_t *timer, timer_reg_t reg, uint32_t value)
+{
+	am335x_timer_regs_t *regs = timer->regs;
+
+	while (regs->twps & reg);
+
+	switch (reg) {
+	default:
+		return;
+	case REG_TCLR:
+		regs->tclr = value;
+		break;
+	case REG_TCRR:
+		regs->tcrr = value;
+		break;
+	case REG_TLDR:
+		regs->tldr = value;
+		break;
+	}
+}
+
+int
+am335x_timer_init(am335x_timer_t *timer, am335x_timer_id_t id, unsigned hz,
+    unsigned srcclk_hz)
+{
+	uintptr_t base_addr;
+	size_t size;
+
+	ASSERT(id < TIMERS_MAX);
+	ASSERT(timer != NULL);
+
+	if (id == DMTIMER1_1MS)
+		return ENOTSUP; /* Not supported yet */
+
+	base_addr = regs_map[id].base;
+	size = regs_map[id].size;
+
+	timer->regs = (void *) km_map(base_addr, size, PAGE_NOT_CACHEABLE);
+	ASSERT(timer->regs != NULL);
+
+	timer->id = id;
+
+	am335x_timer_regs_t *regs = timer->regs;
+
+	/* Enable the posted mode of operation */
+	regs->tsicr |= AM335x_TIMER_TSICR_POSTED_FLAG;
+
+	/* Stop the timer */
+	am335x_timer_stop(timer);
+
+	/* Perform a soft reset */
+	am335x_timer_reset(timer);
+
+	unsigned tclr = regs->tclr;
+
+	/* Disable compare mode */
+	tclr &= ~AM335x_TIMER_TCLR_CE_FLAG;
+	/* Enable the prescaler, divisor = 2 */
+	tclr |= AM335x_TIMER_TCLR_PRE_FLAG;
+	tclr &= ~(AM335x_TIMER_TCLR_PTV_MASK << AM335x_TIMER_TCLR_PTV_SHIFT);
+	/* Enable auto-reload mode */
+	tclr |= AM335x_TIMER_TCLR_AR_FLAG;
+
+	write_register_posted(timer, REG_TCLR, tclr);
+
+	/* Disable the emulation mode */
+	regs->tiocp_cfg |= AM335x_TIMER_TIOCPCFG_EMUFREE_FLAG;
+
+	unsigned const count = 0xFFFFFFFF - (srcclk_hz / hz + 1);
+	write_register_posted(timer, REG_TCRR, count);
+	write_register_posted(timer, REG_TLDR, count);
+
+	return EOK;
+}
+
+void
+am335x_timer_intr_ack(am335x_timer_t *timer)
+{
+	/* Clear pending OVF event */
+	timer->regs->irqstatus |= AM335x_TIMER_IRQSTATUS_OVF_FLAG;
+}
+
+void
+am335x_timer_reset(am335x_timer_t *timer)
+{
+	/* Initiate soft reset */
+	timer->regs->tiocp_cfg |= AM335x_TIMER_TIOCPCFG_SOFTRESET_FLAG;
+	/* Wait until the reset is done */
+	while (timer->regs->tiocp_cfg & AM335x_TIMER_TIOCPCFG_SOFTRESET_FLAG);
+}
+
+void
+am335x_timer_stop(am335x_timer_t *timer)
+{
+	/* Disable the interrupt */
+	timer->regs->irqenable_clr |= AM335x_TIMER_IRQENABLE_CLR_OVF_FLAG;
+	timer->regs->irqwakeen &= ~AM335x_TIMER_IRQWAKEEN_OVF_FLAG;
+	/* Stop the timer */
+	write_register_posted(timer, REG_TCLR,
+	    timer->regs->tclr & ~AM335x_TIMER_TCLR_ST_FLAG);
+}
+
+void
+am335x_timer_start(am335x_timer_t *timer)
+{
+	/* Enable the interrupt */
+	timer->regs->irqenable_set |= AM335x_TIMER_IRQENABLE_SET_OVF_FLAG;
+	timer->regs->irqwakeen |= AM335x_TIMER_IRQWAKEEN_OVF_FLAG;
+	/* Start the clock */
+	write_register_posted(timer, REG_TCLR,
+	    timer->regs->tclr | AM335x_TIMER_TCLR_ST_FLAG);
+}
+
+/**
+ * @}
+ */
+
Index: kernel/genarch/src/drivers/am335x/uart.c
===================================================================
--- kernel/genarch/src/drivers/am335x/uart.c	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
+++ kernel/genarch/src/drivers/am335x/uart.c	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2012 Jan Vesely
+ * Copyright (c) 2013 Maurizio Lombardi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM335x on-chip uart serial line driver.
+ */
+
+#include <genarch/drivers/am335x/uart.h>
+#include <ddi/device.h>
+#include <str.h>
+#include <mm/km.h>
+
+static void am335x_uart_txb(am335x_uart_t *uart, uint8_t b)
+{
+	/* Wait for buffer */
+	while (uart->regs->ssr & AM335x_UART_SSR_TX_FIFO_FULL_FLAG);
+	/* Write to the outgoing fifo */
+	uart->regs->thr = b;
+}
+
+static void am335x_uart_putchar(outdev_t *dev, wchar_t ch)
+{
+	am335x_uart_t *uart = dev->data;
+	if (!ascii_check(ch)) {
+		am335x_uart_txb(uart, U_SPECIAL);
+	} else {
+		if (ch == '\n')
+			am335x_uart_txb(uart, '\r');
+		am335x_uart_txb(uart, ch);
+	}
+}
+
+static outdev_operations_t am335x_uart_ops = {
+	.redraw = NULL,
+	.write = am335x_uart_putchar,
+};
+
+static irq_ownership_t am335x_uart_claim(irq_t *irq)
+{
+	return IRQ_ACCEPT;
+}
+
+static void am335x_uart_handler(irq_t *irq)
+{
+	am335x_uart_t *uart = irq->instance;
+	while ((uart->regs->rx_fifo_lvl)) {
+		const uint8_t val = uart->regs->rhr;
+		if (uart->indev && val) {
+			indev_push_character(uart->indev, val);
+		}
+	}
+}
+
+bool am335x_uart_init(
+    am335x_uart_t *uart, inr_t interrupt, uintptr_t addr, size_t size)
+{
+	ASSERT(uart);
+	uart->regs = (void *)km_map(addr, size, PAGE_NOT_CACHEABLE);
+
+	ASSERT(uart->regs);
+
+	/* Soft reset the port */
+	uart->regs->sysc = AM335x_UART_SYSC_SOFTRESET_FLAG;
+	while (!(uart->regs->syss & AM335x_UART_SYSS_RESETDONE_FLAG));
+
+	/* Disable the UART module */
+	uart->regs->mdr1 |= AM335x_UART_MDR_MS_DISABLE;
+
+	/* Enable access to EFR register */
+	uart->regs->lcr = 0xbf;              /* Sets config mode B */
+
+	/* Enable access to TCL_TLR register */
+	const bool enhanced = uart->regs->efr & AM335x_UART_EFR_ENH_FLAG;
+	uart->regs->efr |= AM335x_UART_EFR_ENH_FLAG; /* Turn on enh. */
+	uart->regs->lcr = 0x80;              /* Config mode A */
+
+	/* Set default (val 0) triggers, disable DMA enable FIFOs */
+	const bool tcl_tlr = uart->regs->mcr & AM335x_UART_MCR_TCR_TLR_FLAG;
+	/* Enable access to tcr and tlr registers */
+	uart->regs->mcr |= AM335x_UART_MCR_TCR_TLR_FLAG;
+
+	/* Enable FIFOs */
+	uart->regs->fcr = AM335x_UART_FCR_FIFO_EN_FLAG;
+
+	/* Enable fine granularity for RX FIFO and set trigger level to 1,
+	 * TX FIFO, trigger level is irrelevant*/
+	uart->regs->lcr = 0xBF;              /* Sets config mode B */
+	uart->regs->scr = AM335x_UART_SCR_RX_TRIG_GRANU1_FLAG;
+	uart->regs->tlr = 1 << AM335x_UART_TLR_RX_FIFO_TRIG_SHIFT;
+
+	/* Sets config mode A */
+	uart->regs->lcr = 0x80;
+	/* Restore tcl_tlr access flag */
+	if (!tcl_tlr)
+		uart->regs->mcr &= ~AM335x_UART_MCR_TCR_TLR_FLAG;
+	/* Sets config mode B */
+	uart->regs->lcr = 0xBF;
+
+	/* Set the divisor value to get a baud rate of 115200 bps */
+	uart->regs->dll = 0x1A;
+	uart->regs->dlh = 0x00;
+
+	/* Restore enhanced */
+	if (!enhanced)
+		uart->regs->efr &= ~AM335x_UART_EFR_ENH_FLAG;
+
+	/* Set the DIV_EN bit to 0 */
+	uart->regs->lcr &= ~AM335x_UART_LCR_DIV_EN_FLAG;
+	/* Set the BREAK_EN bit to 0 */
+	uart->regs->lcr &= ~AM335x_UART_LCR_BREAK_EN_FLAG;
+	/* No parity */
+	uart->regs->lcr &= ~AM335x_UART_LCR_PARITY_EN_FLAG;
+	/* Stop = 1 bit */
+	uart->regs->lcr &= ~AM335x_UART_LCR_NB_STOP_FLAG;
+	/* Char length = 8 bits */
+	uart->regs->lcr |= AM335x_UART_LCR_CHAR_LENGTH_8BITS;
+
+	/* Enable the UART module */
+	uart->regs->mdr1 &= (AM335x_UART_MDR_MS_UART16 &
+	    ~AM335x_UART_MDR_MS_MASK);
+
+	/* Disable interrupts */
+	uart->regs->ier = 0;
+
+	/* Setup outdev */
+	outdev_initialize("am335x_uart_dev", &uart->outdev, &am335x_uart_ops);
+	uart->outdev.data = uart;
+
+	/* Initialize IRQ */
+	irq_initialize(&uart->irq);
+	uart->irq.devno = device_assign_devno();
+	uart->irq.inr = interrupt;
+	uart->irq.claim = am335x_uart_claim;
+	uart->irq.handler = am335x_uart_handler;
+	uart->irq.instance = uart;
+
+	return true;
+}
+
+void am335x_uart_input_wire(am335x_uart_t *uart, indev_t *indev)
+{
+	ASSERT(uart);
+	/* Set indev */
+	uart->indev = indev;
+	/* Register interrupt. */
+	irq_register(&uart->irq);
+	/* Enable interrupt on receive */
+	uart->regs->ier |= AM335x_UART_IER_RHR_IRQ_FLAG;
+}
+
+/**
+ * @}
+ */
+
Index: kernel/genarch/src/drivers/amdm37x/uart.c
===================================================================
--- kernel/genarch/src/drivers/amdm37x/uart.c	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
+++ kernel/genarch/src/drivers/amdm37x/uart.c	(revision 9ad289db625ec899a8601867483d89b8354a0f81)
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2012 Jan Vesely
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AMDM37x on-chip uart serial line driver.
+ */
+
+#include <genarch/drivers/amdm37x/uart.h>
+#include <ddi/device.h>
+#include <str.h>
+#include <mm/km.h>
+
+static void amdm37x_uart_txb(amdm37x_uart_t *uart, uint8_t b)
+{
+	/* Wait for buffer */
+	while (uart->regs->ssr & AMDM37x_UART_SSR_TX_FIFO_FULL_FLAG);
+	/* Write to the outgoing fifo */
+	uart->regs->thr = b;
+}
+
+static void amdm37x_uart_putchar(outdev_t *dev, wchar_t ch)
+{
+	amdm37x_uart_t *uart = dev->data;
+	if (!ascii_check(ch)) {
+		amdm37x_uart_txb(uart, U_SPECIAL);
+	} else {
+		if (ch == '\n')
+			amdm37x_uart_txb(uart, '\r');
+		amdm37x_uart_txb(uart, ch);
+	}
+}
+
+static outdev_operations_t amdm37x_uart_ops = {
+	.redraw = NULL,
+	.write = amdm37x_uart_putchar,
+};
+
+static irq_ownership_t amdm37x_uart_claim(irq_t *irq)
+{
+	return IRQ_ACCEPT;
+}
+
+static void amdm37x_uart_handler(irq_t *irq)
+{
+	amdm37x_uart_t *uart = irq->instance;
+	while ((uart->regs->rx_fifo_lvl)) {
+		const uint8_t val = uart->regs->rhr;
+		if (uart->indev && val) {
+			indev_push_character(uart->indev, val);
+		}
+	}
+}
+
+bool amdm37x_uart_init(
+    amdm37x_uart_t *uart, inr_t interrupt, uintptr_t addr, size_t size)
+{
+	ASSERT(uart);
+	uart->regs = (void *)km_map(addr, size, PAGE_NOT_CACHEABLE);
+
+	ASSERT(uart->regs);
+
+	/* See TI OMAP35X TRM ch 17.5.1.1 p. 2732 for startup routine */
+#if 0
+	/* Soft reset the port */
+	uart->regs->sysc = AMDM37x_UART_SYSC_SOFTRESET_FLAG;
+	while (!(uart->regs->syss & AMDM37x_UART_SYSS_RESETDONE_FLAG)) ;
+#endif
+
+	/* Enable access to EFR register */
+	const uint8_t lcr = uart->regs->lcr; /* Save old value */
+	uart->regs->lcr = 0xbf;              /* Sets config mode B */
+
+	/* Enable access to TCL_TLR register */
+	const bool enhanced = uart->regs->efr & AMDM37x_UART_EFR_ENH_FLAG;
+	uart->regs->efr |= AMDM37x_UART_EFR_ENH_FLAG; /* Turn on enh. */
+	uart->regs->lcr = 0x80;              /* Config mode A */
+
+	/* Set default (val 0) triggers, disable DMA enable FIFOs */
+	const bool tcl_tlr = uart->regs->mcr & AMDM37x_UART_MCR_TCR_TLR_FLAG;
+	/* Enable access to tcr and tlr registers */
+	uart->regs->mcr |= AMDM37x_UART_MCR_TCR_TLR_FLAG;
+
+	/* Enable FIFOs */
+	uart->regs->fcr = AMDM37x_UART_FCR_FIFO_EN_FLAG;
+
+	/* Eneble fine granularity for RX FIFO and set trigger level to 1,
+	 * TX FIFO, trigger level is irelevant*/
+	uart->regs->lcr = 0xbf;              /* Sets config mode B */
+	uart->regs->scr = AMDM37x_UART_SCR_RX_TRIG_GRANU1_FLAG;
+	uart->regs->tlr = 1 << AMDM37x_UART_TLR_RX_FIFO_TRIG_SHIFT;
+
+	/* Restore enhanced */
+	if (!enhanced)
+		uart->regs->efr &= ~AMDM37x_UART_EFR_ENH_FLAG;
+
+	uart->regs->lcr = 0x80;              /* Config mode A */
+	/* Restore tcl_lcr access flag*/
+	if (!tcl_tlr)
+		uart->regs->mcr &= ~AMDM37x_UART_MCR_TCR_TLR_FLAG;
+
+	/* Restore lcr */
+	uart->regs->lcr = lcr;
+
+	/* Disable interrupts */
+	uart->regs->ier = 0;
+
+	/* Setup outdev */
+	outdev_initialize("amdm37x_uart_dev", &uart->outdev, &amdm37x_uart_ops);
+	uart->outdev.data = uart;
+
+	/* Initialize IRQ */
+	irq_initialize(&uart->irq);
+	uart->irq.devno = device_assign_devno();
+	uart->irq.inr = interrupt;
+	uart->irq.claim = amdm37x_uart_claim;
+	uart->irq.handler = amdm37x_uart_handler;
+	uart->irq.instance = uart;
+
+	return true;
+}
+
+void amdm37x_uart_input_wire(amdm37x_uart_t *uart, indev_t *indev)
+{
+	ASSERT(uart);
+	/* Set indev */
+	uart->indev = indev;
+	/* Register interrupt. */
+	irq_register(&uart->irq);
+	/* Enable interrupt on receive */
+	uart->regs->ier |= AMDM37x_UART_IER_RHR_IRQ_FLAG;
+}
+
+/**
+ * @}
+ */
Index: rnel/genarch/src/drivers/amdm37x_uart/amdm37x_uart.c
===================================================================
--- kernel/genarch/src/drivers/amdm37x_uart/amdm37x_uart.c	(revision df64dbcec09ca6420de2c8c0944a17482cc56d6b)
+++ 	(revision )
@@ -1,163 +1,0 @@
-/*
- * Copyright (c) 2012 Jan Vesely
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/** @addtogroup genarch
- * @{
- */
-/**
- * @file
- * @brief Texas Instruments AMDM37x on-chip uart serial line driver.
- */
-
-#include <genarch/drivers/amdm37x_uart/amdm37x_uart.h>
-#include <ddi/device.h>
-#include <str.h>
-#include <mm/km.h>
-
-static void amdm37x_uart_txb(amdm37x_uart_t *uart, uint8_t b)
-{
-	/* Wait for buffer */
-	while (uart->regs->ssr & AMDM37x_UART_SSR_TX_FIFO_FULL_FLAG);
-	/* Write to the outgoing fifo */
-	uart->regs->thr = b;
-}
-
-static void amdm37x_uart_putchar(outdev_t *dev, wchar_t ch)
-{
-	amdm37x_uart_t *uart = dev->data;
-	if (!ascii_check(ch)) {
-		amdm37x_uart_txb(uart, U_SPECIAL);
-	} else {
-		if (ch == '\n')
-			amdm37x_uart_txb(uart, '\r');
-		amdm37x_uart_txb(uart, ch);
-	}
-}
-
-static outdev_operations_t amdm37x_uart_ops = {
-	.redraw = NULL,
-	.write = amdm37x_uart_putchar,
-};
-
-static irq_ownership_t amdm37x_uart_claim(irq_t *irq)
-{
-	return IRQ_ACCEPT;
-}
-
-static void amdm37x_uart_handler(irq_t *irq)
-{
-	amdm37x_uart_t *uart = irq->instance;
-	while ((uart->regs->rx_fifo_lvl)) {
-		const uint8_t val = uart->regs->rhr;
-		if (uart->indev && val) {
-			indev_push_character(uart->indev, val);
-		}
-	}
-}
-
-bool amdm37x_uart_init(
-    amdm37x_uart_t *uart, inr_t interrupt, uintptr_t addr, size_t size)
-{
-	ASSERT(uart);
-	uart->regs = (void *)km_map(addr, size, PAGE_NOT_CACHEABLE);
-
-	ASSERT(uart->regs);
-
-	/* See TI OMAP35X TRM ch 17.5.1.1 p. 2732 for startup routine */
-#if 0
-	/* Soft reset the port */
-	uart->regs->sysc = AMDM37x_UART_SYSC_SOFTRESET_FLAG;
-	while (!(uart->regs->syss & AMDM37x_UART_SYSS_RESETDONE_FLAG)) ;
-#endif
-
-	/* Enable access to EFR register */
-	const uint8_t lcr = uart->regs->lcr; /* Save old value */
-	uart->regs->lcr = 0xbf;              /* Sets config mode B */
-
-	/* Enable access to TCL_TLR register */
-	const bool enhanced = uart->regs->efr & AMDM37x_UART_EFR_ENH_FLAG;
-	uart->regs->efr |= AMDM37x_UART_EFR_ENH_FLAG; /* Turn on enh. */
-	uart->regs->lcr = 0x80;              /* Config mode A */
-
-	/* Set default (val 0) triggers, disable DMA enable FIFOs */
-	const bool tcl_tlr = uart->regs->mcr & AMDM37x_UART_MCR_TCR_TLR_FLAG;
-	/* Enable access to tcr and tlr registers */
-	uart->regs->mcr |= AMDM37x_UART_MCR_TCR_TLR_FLAG;
-
-	/* Enable FIFOs */
-	uart->regs->fcr = AMDM37x_UART_FCR_FIFO_EN_FLAG;
-
-	/* Eneble fine granularity for RX FIFO and set trigger level to 1,
-	 * TX FIFO, trigger level is irelevant*/
-	uart->regs->lcr = 0xbf;              /* Sets config mode B */
-	uart->regs->scr = AMDM37x_UART_SCR_RX_TRIG_GRANU1_FLAG;
-	uart->regs->tlr = 1 << AMDM37x_UART_TLR_RX_FIFO_TRIG_SHIFT;
-
-	/* Restore enhanced */
-	if (!enhanced)
-		uart->regs->efr &= ~AMDM37x_UART_EFR_ENH_FLAG;
-
-	uart->regs->lcr = 0x80;              /* Config mode A */
-	/* Restore tcl_lcr access flag*/
-	if (!tcl_tlr)
-		uart->regs->mcr &= ~AMDM37x_UART_MCR_TCR_TLR_FLAG;
-
-	/* Restore lcr */
-	uart->regs->lcr = lcr;
-
-	/* Disable interrupts */
-	uart->regs->ier = 0;
-
-	/* Setup outdev */
-	outdev_initialize("amdm37x_uart_dev", &uart->outdev, &amdm37x_uart_ops);
-	uart->outdev.data = uart;
-
-	/* Initialize IRQ */
-	irq_initialize(&uart->irq);
-	uart->irq.devno = device_assign_devno();
-	uart->irq.inr = interrupt;
-	uart->irq.claim = amdm37x_uart_claim;
-	uart->irq.handler = amdm37x_uart_handler;
-	uart->irq.instance = uart;
-
-	return true;
-}
-
-void amdm37x_uart_input_wire(amdm37x_uart_t *uart, indev_t *indev)
-{
-	ASSERT(uart);
-	/* Set indev */
-	uart->indev = indev;
-	/* Register interrupt. */
-	irq_register(&uart->irq);
-	/* Enable interrupt on receive */
-	uart->regs->ier |= AMDM37x_UART_IER_RHR_IRQ_FLAG;
-}
-
-/**
- * @}
- */
