Index: kernel/arch/ia64/include/arch/context.h
===================================================================
--- kernel/arch/ia64/include/arch/context.h	(revision 09ab0a9afc9379f1604c0fd75cac2d9287ba022c)
+++ kernel/arch/ia64/include/arch/context.h	(revision 9a5ae815b43ebe562be9124064e24c56f08f6b1e)
@@ -57,5 +57,5 @@
 		(c)->bsp = ((uintptr_t) stack) + ALIGN_UP((size / 2), REGISTER_STACK_ALIGNMENT); \
 		(c)->ar_pfs &= PFM_MASK; \
-		(c)->ar_fpsr = FPSR_TRAPS_ALL; \
+		(c)->ar_fpsr = FPSR_TRAPS_ALL | FPSR_SF1_CTRL; \
 		(c)->sp = ((uintptr_t) stack) + ALIGN_UP((size / 2), STACK_ALIGNMENT) - SP_DELTA; \
 		(c)->r1 = (uintptr_t) &__gp; \
Index: kernel/arch/ia64/include/arch/register.h
===================================================================
--- kernel/arch/ia64/include/arch/register.h	(revision 09ab0a9afc9379f1604c0fd75cac2d9287ba022c)
+++ kernel/arch/ia64/include/arch/register.h	(revision 9a5ae815b43ebe562be9124064e24c56f08f6b1e)
@@ -78,4 +78,14 @@
 #define FPSR_TRAPS_ALL (FPSR_TRAPS_VD | FPSR_TRAPS_DD | FPSR_TRAPS_ZD | \
     FPSR_TRAPS_OD | FPSR_TRAPS_UD | FPSR_TRAPS_ID)
+
+#define FPSR_SF1_SHIFT 19
+
+#define FPSR_CTRL_WRE           (1 << 1)
+#define FPSR_CTRL_PC_EXTENDED   (3 << 2)
+#define FPSR_CTRL_RC_NEAREST    (0 << 4)
+#define FPSR_CTRL_TD            (1 << 6)
+
+#define FPSR_SF1_CTRL ((FPSR_CTRL_WRE | FPSR_CTRL_PC_EXTENDED | \
+    FPSR_CTRL_RC_NEAREST | FPSR_CTRL_TD) << FPSR_SF1_SHIFT)
 
 /** Application registers. */
Index: kernel/arch/ia64/src/fpu_context.c
===================================================================
--- kernel/arch/ia64/src/fpu_context.c	(revision 09ab0a9afc9379f1604c0fd75cac2d9287ba022c)
+++ kernel/arch/ia64/src/fpu_context.c	(revision 9a5ae815b43ebe562be9124064e24c56f08f6b1e)
@@ -491,5 +491,5 @@
 	    "mov ar.fpsr = %0 ;;\n"
 	    : "+r" (a)
-	    : "r" (FPSR_TRAPS_ALL)
+	    : "r" (FPSR_TRAPS_ALL | FPSR_SF1_CTRL)
 	);